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allgemein: components fuer die module
[hwmod.git]
/
src
/
calc.vhd
diff --git
a/src/calc.vhd
b/src/calc.vhd
index 2175ee932086b666c40f8f46c77cfa78d855c23e..20d2027e62013e409327ac531a1f4792612e3207 100644
(file)
--- a/
src/calc.vhd
+++ b/
src/calc.vhd
@@
-14,7
+14,7
@@
entity calc is
sys_clk : in std_logic;
sys_res_n : in std_logic;
-- btnA
sys_clk : in std_logic;
sys_res_n : in std_logic;
-- btnA
- -- TODO: pins
+ btn_a : in std_logic;
-- rs232
rxd : in std_logic;
txd : out std_logic;
-- rs232
rxd : in std_logic;
txd : out std_logic;
@@
-31,6
+31,8
@@
entity calc is
end entity calc;
architecture top of calc is
end entity calc;
architecture top of calc is
+ constant CLK_FREQ : integer := 33000000;
+ constant BAUDRATE : integer := 115200;
-- ps/2
signal new_data : std_logic;
signal data : std_logic_vector(7 downto 0);
-- ps/2
signal new_data : std_logic;
signal data : std_logic_vector(7 downto 0);
@@
-56,10
+58,17
@@
architecture top of calc is
signal p_wdone : std_logic;
signal p_write : hbyte;
signal p_finished : std_logic;
signal p_wdone : std_logic;
signal p_write : hbyte;
signal p_finished : std_logic;
+ --history/pc_com
+ signal pc_get : std_logic;
+ signal pc_spalte : hspalte;
+ signal pc_zeile : hzeile;
+ signal pc_char : hbyte;
+ signal pc_done : std_logic;
-- parser/scanner
signal do_it, finished : std_logic;
-- debouncing
signal sys_res_n_sync : std_logic;
-- parser/scanner
signal do_it, finished : std_logic;
-- debouncing
signal sys_res_n_sync : std_logic;
+ signal btn_a_sync : std_logic;
-- rs232
signal rx_new, rxd_sync : std_logic;
signal rx_data : std_logic_vector (7 downto 0);
-- rs232
signal rx_new, rxd_sync : std_logic;
signal rx_data : std_logic_vector (7 downto 0);
@@
-67,7
+76,7
@@
architecture top of calc is
signal tx_data : std_logic_vector (7 downto 0);
begin
-- vga/ipcore
signal tx_data : std_logic_vector (7 downto 0);
begin
-- vga/ipcore
- textmode_vga_inst :
entity work.textmode_vga(struct)
+ textmode_vga_inst :
textmode_vga
generic map (
VGA_CLK_FREQ => 25000000,
BLINK_INTERVAL_MS => 500,
generic map (
VGA_CLK_FREQ => 25000000,
BLINK_INTERVAL_MS => 500,
@@
-89,14
+98,14
@@
begin
);
-- pll fuer vga
);
-- pll fuer vga
- vpll_inst :
entity work.vpll(syn)
+ vpll_inst :
vpll
port map (
inclk0 => sys_clk,
c0 => vga_clk
);
-- display
port map (
inclk0 => sys_clk,
c0 => vga_clk
);
-- display
- display_inst :
entity work.display(beh)
+ display_inst :
display
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n_sync,
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n_sync,
@@
-116,7
+125,7
@@
begin
);
-- history
);
-- history
- history_inst :
entity work.history(beh)
+ history_inst :
history
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n_sync,
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n_sync,
@@
-141,11
+150,17
@@
begin
p_wtake => p_wtake,
p_wdone => p_wdone,
p_write => p_write,
p_wtake => p_wtake,
p_wdone => p_wdone,
p_write => p_write,
- p_finished => p_finished
+ p_finished => p_finished,
+ -- pc communication
+ pc_get => pc_get,
+ pc_spalte => pc_spalte,
+ pc_zeile => pc_zeile,
+ pc_char => pc_char,
+ pc_done => pc_done
);
-- parser
);
-- parser
- parser_inst :
entity work.parser(beh)
+ parser_inst :
parser
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n_sync,
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n_sync,
@@
-163,7
+178,7
@@
begin
);
-- scanner
);
-- scanner
- scanner_inst :
entity work.scanner(beh)
+ scanner_inst :
scanner
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n_sync,
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n_sync,
@@
-181,9
+196,9
@@
begin
);
-- ps/2
);
-- ps/2
- ps2_inst :
entity work.ps2_keyboard_controller(beh)
+ ps2_inst :
ps2_keyboard_controller
generic map (
generic map (
- CLK_FREQ =>
33330000
,
+ CLK_FREQ =>
CLK_FREQ
,
SYNC_STAGES => 2
)
port map (
SYNC_STAGES => 2
)
port map (
@@
-199,7
+214,7
@@
begin
-- debouncer fuer sys_res_n
sys_res_n_debounce_inst : debounce
generic map (
-- debouncer fuer sys_res_n
sys_res_n_debounce_inst : debounce
generic map (
- CLK_FREQ =>
33330000
,
+ CLK_FREQ =>
CLK_FREQ
,
TIMEOUT => 1 ms,
RESET_VALUE => '1',
SYNC_STAGES => 2
TIMEOUT => 1 ms,
RESET_VALUE => '1',
SYNC_STAGES => 2
@@
-212,7
+227,7
@@
begin
);
-- synchronizer fuer rxd
);
-- synchronizer fuer rxd
- sync_rxd_inst :
entity work.sync(beh)
+ sync_rxd_inst :
sync
generic map (
SYNC_STAGES => 2,
RESET_VALUE => '1'
generic map (
SYNC_STAGES => 2,
RESET_VALUE => '1'
@@
-224,11
+239,26
@@
begin
data_out => rxd_sync
);
data_out => rxd_sync
);
+ -- debouncer fuer btn_a
+ btn_a_debounce_inst : debounce
+ generic map (
+ CLK_FREQ => CLK_FREQ,
+ TIMEOUT => 1 ms,
+ RESET_VALUE => '1',
+ SYNC_STAGES => 2
+ )
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n_sync,
+ data_in => btn_a,
+ data_out => btn_a_sync
+ );
+
-- rs232-rx
-- rs232-rx
- rs232rx_inst :
entity work.uart_rx(beh)
+ rs232rx_inst :
uart_rx
generic map (
generic map (
- CLK_FREQ =>
33330000
,
- BAUDRATE =>
115200
+ CLK_FREQ =>
CLK_FREQ
,
+ BAUDRATE =>
BAUDRATE
)
port map (
sys_clk => sys_clk,
)
port map (
sys_clk => sys_clk,
@@
-239,10
+269,10
@@
begin
);
-- rs232-tx
);
-- rs232-tx
- rs232tx_inst :
entity work.uart_tx(beh)
+ rs232tx_inst :
uart_tx
generic map (
generic map (
- CLK_FREQ =>
33330000
,
- BAUDRATE =>
115200
+ CLK_FREQ =>
CLK_FREQ
,
+ BAUDRATE =>
BAUDRATE
)
port map (
sys_clk => sys_clk,
)
port map (
sys_clk => sys_clk,
@@
-252,5
+282,26
@@
begin
tx_new => tx_new,
tx_done => tx_done
);
tx_new => tx_new,
tx_done => tx_done
);
-end architecture top;
+ pc_com_inst : pc_communication
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n,
+ --button
+ btn_a => btn_a_sync,
+ --uart_tx
+ tx_data => tx_data,
+ tx_new => tx_new,
+ tx_done => tx_done,
+ --uart_rx
+ rx_data => rx_data,
+ rx_new => rx_new,
+ -- History
+ pc_zeile => pc_zeile,
+ pc_spalte => pc_spalte,
+ pc_get => pc_get,
+ pc_done => pc_done,
+ pc_char => pc_char
+ );
+
+end architecture top;