+ if (wb_reg.address(DATA_ADDR_WIDTH+2) /= '1') then
+ data_out := data_ram_read;
+ else
+ reg_we_v := reg_we_v and ext_anysel;
+ data_out := data_ram_read_ext;
+ end if;
+
+ if wb_reg.byte_en(0) = '0' then
+ data_out(byte_t'range) := (others => '0');
+ end if;
+ if wb_reg.byte_en(1) = '0' then
+ data_out(2*byte_t'length-1 downto byte_t'length) := (others => '0');
+ end if;
+ if wb_reg.byte_en(2) = '0' then
+ data_out(3*byte_t'length-1 downto 2*byte_t'length) := (others => '0');
+ end if;
+ if wb_reg.byte_en(3) = '0' then
+ data_out(4*byte_t'length-1 downto 3*byte_t'length) := (others => '0');
+ end if;
+
+
+-- if wb_reg.hword = '1' or wb_reg.byte_s = '1' then
+-- if wb_reg.address(1)='1' then
+-- data_out(hword_t'range) := data_out(data_out'high downto (data_out'length/2));
+-- end if;
+-- data_out(data_out'high downto (data_out'length/2)) := (others => '0');
+-- if byte_s = '1' then
+-- if wb_reg.address(0) = '1' then
+-- data_out(byte_t'range) := data_out(hword_t'high downto (hword_t'length/2));
+-- end if;
+-- data_out(hword_t'high downto (hword_t'length/2)) := (others => '0');
+-- end if;
+-- end if;
+
+
+ data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length);
+