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spartan3e: at least it compiles
[calu.git]
/
cpu
/
src
/
writeback_stage.vhd
diff --git
a/cpu/src/writeback_stage.vhd
b/cpu/src/writeback_stage.vhd
index 73c5df43499e1401bc04a496f9cc5b941d0cab4a..9ec598638530aa97708967dca32b9ac78210de10 100644
(file)
--- a/
cpu/src/writeback_stage.vhd
+++ b/
cpu/src/writeback_stage.vhd
@@
-10,8
+10,8
@@
entity writeback_stage is
-- active reset value
RESET_VALUE : std_logic;
-- active logic value
-- active reset value
RESET_VALUE : std_logic;
-- active logic value
- LOGIC_ACT : std_logic
-
+ LOGIC_ACT : std_logic
;
+ FPGATYPE : string
);
port(
--System inputs
);
port(
--System inputs
@@
-37,11
+37,19
@@
entity writeback_stage is
jump : out std_logic;
-- hallo stefan mir adden da jetzt mal schnell an uart port :D
bus_tx : out std_logic;
jump : out std_logic;
-- hallo stefan mir adden da jetzt mal schnell an uart port :D
bus_tx : out std_logic;
+ bus_rx : in std_logic;
+ -- instruction memory program port :D
+ new_im_data_out : out std_logic;
+ im_addr : out gp_register_t;
+ im_data : out gp_register_t;
sseg0 : out std_logic_vector(0 to 6);
sseg1 : out std_logic_vector(0 to 6);
sseg2 : out std_logic_vector(0 to 6);
sseg0 : out std_logic_vector(0 to 6);
sseg1 : out std_logic_vector(0 to 6);
sseg2 : out std_logic_vector(0 to 6);
- sseg3 : out std_logic_vector(0 to 6)
+ sseg3 : out std_logic_vector(0 to 6);
+
+ int_req : out interrupt_t
+
);
end writeback_stage;
);
end writeback_stage;