projects
/
calu.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
lustiger modelsim fix...
[calu.git]
/
cpu
/
src
/
extension_uart_pkg.vhd
diff --git
a/cpu/src/extension_uart_pkg.vhd
b/cpu/src/extension_uart_pkg.vhd
index 2a4ca4b1ca2e24c187e0dfab761902dccefeab6b..a7f14d9442c611e0b4820308107ec3409b31afba 100644
(file)
--- a/
cpu/src/extension_uart_pkg.vhd
+++ b/
cpu/src/extension_uart_pkg.vhd
@@
-22,7
+22,9
@@
subtype baud_rate_l is std_logic_vector(BAUD_RATE_WIDTH-1 downto 0);
--constant CLK_FREQ_MHZ : real := 33.33;
--constant BAUD_RATE : integer := 115200;
--constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
--constant CLK_FREQ_MHZ : real := 33.33;
--constant BAUD_RATE : integer := 115200;
--constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
-constant CLK_PER_BAUD : integer := 434;
+-- constant CLK_PER_BAUD : integer := 434;
+constant CLK_PER_BAUD : integer := 2083; -- @uni, bei 20MHz und 9600 Baud
+-- constant CLK_PER_BAUD : integer := 50; -- @modelsim
component extension_uart is
--some modules won't need all inputs/outputs
component extension_uart is
--some modules won't need all inputs/outputs