+ exec_st : execute_stage
+ generic map('0')
+ port map(sys_clk, sys_res_n and soft_res_n, to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
+ data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
+
+
+ vers_nxt.result <= result_pin;
+ vers_nxt.result_addr <= result_addr_pin;
+ vers_nxt.address <= addr_pin;
+ vers_nxt.ram_data <= data_pin;
+ vers_nxt.alu_jmp <= alu_jump_pin;
+ vers_nxt.br_pred <= brpr_pin;
+ vers_nxt.write_en <= wr_en_pin;
+ vers_nxt.dmem_en <= dmem_pin;
+ vers_nxt.dmem_write_en <= dmem_wr_en_pin;
+ vers_nxt.hword <= hword_pin;
+ vers_nxt.byte_s <= byte_s_pin;
+
+-- writeback_st : writeback_stage
+-- generic map('0', '1')
+-- port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
+-- wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
+-- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
+--
+
+ writeback_st : writeback_stage
+ generic map('0', '1', "altera", 2083)
+ port map(sys_clk, sys_res_n and soft_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred,
+ vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
+ reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
+ -- instruction memory program port :D
+ new_im_data, im_addr, im_data,
+ sseg0, sseg1, sseg2, sseg3, int_req);
+
+
+syn: process(sys_clk, sys_res, soft_res)
+
+begin
+
+ if sys_res = '1' then
+-- vers.result <= (others => '0');
+-- vers.result_addr <= (others => '0');
+-- vers.address <= (others => '0');
+-- vers.ram_data <= (others => '0');
+-- vers.alu_jmp <= '0';
+-- vers.br_pred <= '0';
+-- vers.write_en <= '0';
+-- vers.dmem_en <= '0';
+-- vers.dmem_write_en <= '0';
+-- vers.hword <= '0';
+-- vers.byte_s <= '0';
+
+ sync <= (others => '0');
+ sync2 <= (others => '0');
+
+ elsif rising_edge(sys_clk) then
+-- vers <= vers_nxt;
+ sync(1) <= not sys_res;
+ for i in 2 to SYNC_STAGES loop
+ sync(i) <= sync(i - 1);
+ end loop;
+ sync2(1) <= not soft_res;
+ for i in 2 to SYNC_STAGES loop
+ sync2(i) <= sync2(i - 1);
+ end loop;
+ end if;
+
+
+end process;
+
+sys_res_n <= sync(SYNC_STAGES);
+soft_res_n <= sync2(SYNC_STAGES);
+