- and_inst : exec_op\r
- port map(clk,reset,left_operand, right_operand, op_detail, alu_state, and_result);\r
- or_inst : exec_op\r
- port map(clk,reset,left_operand, right_operand, op_detail, alu_state, or_result);\r
- xor_inst : exec_op\r
- port map(clk,reset,left_operand, right_operand, op_detail, alu_state, xor_result);\r
+ and_inst : entity work.exec_op(and_op)\r
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, and_result);\r
+\r
+ or_inst : entity work.exec_op(or_op)\r
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, or_result);\r
+\r
+ xor_inst : entity work.exec_op(xor_op)\r
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, xor_result);\r