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Fixed some bugs.
[calu.git]
/
cpu
/
src
/
alu_b.vhd
diff --git
a/cpu/src/alu_b.vhd
b/cpu/src/alu_b.vhd
index 78696f2e619635e818e91a10fd46c1e10d566e3a..3fb3434827af3647c95b48f6a2770de187f20901 100755
(executable)
--- a/
cpu/src/alu_b.vhd
+++ b/
cpu/src/alu_b.vhd
@@
-38,7
+38,7
@@
begin
shift_inst : exec_op
\r
port map(clk,reset,left_operand, right_operand, op_detail, alu_state, shift_result);
\r
\r
shift_inst : exec_op
\r
port map(clk,reset,left_operand, right_operand, op_detail, alu_state, shift_result);
\r
\r
-calc: process(cond
ition
, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)
\r
+calc: process(cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)
\r
variable result_v : alu_result_rec;
\r
variable res_prod : std_logic;
\r
variable cond_met : std_logic;
\r
variable result_v : alu_result_rec;
\r
variable res_prod : std_logic;
\r
variable cond_met : std_logic;
\r
@@
-49,9
+49,9
@@
begin
result_v.result := add_result.result;
\r
res_prod := '1';
\r
mem_en := '0';
result_v.result := add_result.result;
\r
res_prod := '1';
\r
mem_en := '0';
- addr <= add_result;
\r
+ addr <= add_result
.result
;
\r
\r
\r
- case cond
ition
is
\r
+ case cond is
\r
when COND_NZERO =>
\r
cond_met := not(alu_state.status.zero);
\r
when COND_ZERO =>
\r
when COND_NZERO =>
\r
cond_met := not(alu_state.status.zero);
\r
when COND_ZERO =>
\r
@@
-83,7
+83,8
@@
begin
when COND_ALWAYS =>
\r
cond_met := '1';
\r
when COND_NEVER =>
\r
when COND_ALWAYS =>
\r
cond_met := '1';
\r
when COND_NEVER =>
\r
- cond_met := '0';
\r
+ cond_met := '0';
+ when others => null;
\r
end case;
\r
\r
case op_group is
\r
end case;
\r
\r
case op_group is
\r
@@
-109,11
+110,11
@@
begin
result_v.status := alu_state.status;
\r
end if;
\r
\r
result_v.status := alu_state.status;
\r
end if;
\r
\r
- result_v.
new_val
:= not(op_detail(NO_DST_OPT)) and res_prod and cond_met;
\r
+ result_v.
reg_op
:= not(op_detail(NO_DST_OPT)) and res_prod and cond_met;
\r
result_v.mem_en := mem_en and cond_met;
\r
result_v.mem_en := mem_en and cond_met;
\r
- data <= add_result;
\r
+ data <= add_result
.result
;
\r
alu_result <= result_v;
\r
\r
end process calc;
\r
alu_result <= result_v;
\r
\r
end process calc;
\r