--System inputs
clk => sys_clk_pin, --: in std_logic;
reset => sys_res_n_pin, --: in std_logic;
-
+ s_reset => '0',
--Data inputs
jump_result => jump_result_pin, --: in instruction_addr_t;
prediction_result => prediction_result_pin, --: in instruction_addr_t;
data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
writeback_st : writeback_stage
- generic map('0', '1', "altera")
+ generic map('0', '1', "altera",50)
port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req_pin);