1 /* src/vm/jit/m68k/codegen.h
3 Copyright (C) 1996-2005, 2006, 2007, 2008
4 CACAOVM - Verein zur Foerderung der freien virtuellen Maschine CACAO
6 This file is part of CACAO.
8 This program is free software; you can redistribute it and/or
9 modify it under the terms of the GNU General Public License as
10 published by the Free Software Foundation; either version 2, or (at
11 your option) any later version.
13 This program is distributed in the hope that it will be useful, but
14 WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
34 #include "vm/jit/m68k/emit.h"
37 #define MCODECHECK(icnt) \
39 if ((cd->mcodeptr + (icnt) * 4) > cd->mcodeend) \
40 codegen_increase(cd); \
44 /* branch defines *************************************************************/
48 if (CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) { \
59 /* patcher defines ************************************************************/
61 #define PATCHER_NOPS \
62 do { M_TPFL; M_TPF; M_TPF } while (0);
64 #define PATCHER_CALL_SIZE 2
67 /* coldfire instruction format:
68 * -----------------------------
70 * |____________________________|
71 * | extension word 1(optional) |
72 * |____________________________|
73 * | extension word 2(optional) |
74 * |____________________________|
81 * x x x x x x x x x x | M M M | R R R
83 * MMM = 000 ---> data register direct: RRR = register
84 * MMM = 001 ---> addr register direct: RRR = register
85 * MMM = 010 ---> addr register indirect: RRR = register
86 * MMM = 011 ---> addr reg ind postincr : RRR = register
87 * MMM = 100 ---> addr reg ind predecr : RRR = register
88 * MMM = 101 ---> addr reg ind + displac: RRR = register + ext.wrd.1
89 * MMM = 110 ---> addr reg ind + scaled index and 8 bit displacement
90 * MMM = 111, RRR = 010 ---> PC ind. with displacement + ext.wrd.1
91 * MMM = 111, RRR = 011 ---> PC ind. with scaled inex + 8but displacement
92 * MMM = 111, RRR = 000 + ext.wrd.1 ---> absolute short
93 * MMM = 111, RRR = 001 + ext.wrd.1+2 -> absolute long
94 * MMM = 111, RRR = 100 + ext.wrd1/2 --> immediate data
97 /* one word opcodes */
98 #define OPWORD(op, mode, reg) \
100 *((u2*)cd->mcodeptr) = (u2) (((op) << 6) | ((mode)<<3) | (reg)); \
103 /* opword + one extension word */
104 /* usage of int16_t instead of s2 as is clashes with variable name */
105 #define OPWORD_IMM16(op, mode, reg, imm) \
107 *((u2*)cd->mcodeptr) = (u2) (((op) << 6) | ((mode)<<3) | (reg)); \
109 *((int16_t*)(cd->mcodeptr)) = imm; \
113 /* opword + two extension words */
114 /* usage of int32_t instead of s4 as is clashes with variable name */
115 #define OPWORD_IMM32(op, mode, reg, imm) \
117 *((u2*)cd->mcodeptr) = (u2) (((op) << 6) | ((mode)<<3) | (reg)); \
119 *((int32_t*)(cd->mcodeptr)) = imm; \
123 /* create NOPS to align basicblock boundaries
124 * using real nops here as they are not executed, so no performance penalty
126 #define ALIGNCODENOP \
128 for (s1 = 0; s1 < (s4) (((ptrint) cd->mcodeptr) & 7); s1++) \
135 #define M_NOP OPWORD(0x139,6,1) /* 0x4371 do not use as it syncs pipeline */
136 #define M_ILLEGAL OPWORD(0x12b,7,4) /* 0x4afc */
137 #define M_TPF OPWORD(0x147,7,4) /* tfp with no ext. word use instead of NOP*/
138 #define M_TPFW OPWORD(0x147,7,2) /* tfp with one ext. word */
139 #define M_TPFL OPWORD(0x147,7,3) /* tfp with two ext. word */
141 /*M_XMOVX....M_XMOVX(source, destination) */
142 #define M_IMOV(a,b) OPWORD( ( (2<<6) | ((b) << 3) | 0), 0, (a)) /* move.l */
143 #define M_AMOV(a,b) OPWORD( ( (2<<6) | ((b) << 3) | 1), 1, (a)) /* movea.l */
144 #define M_IMOV_IMM(a,b) emit_mov_imm_reg(cd, (a), (b))
145 #define M_AMOV_IMM(a,b) OPWORD_IMM32( ( (2<<6) | ((b) << 3) | 1), 7, 4, (a))
147 /* for sure generates a 32 bit immedeate form, needed when there are patchers involved */
148 #define M_IMOV_IMM32(a,b) OPWORD_IMM32(((2<<6) | ((b) << 3) | 0), 7, 4, (a))
150 #define M_ICLR(a) OPWORD(0x10a, 0, (a)) /* clr.l */
151 #define M_ISET(a) OPWORD( ( (0xa <<6) | (0 << 3) | 5), 0, (a)) /* mov3q #-1 */
153 #define M_JMP(a) OPWORD(0x13b,2,(a)) /* jmp %aX@ */
154 #define M_JMP_IMM(a) OPWORD_IMM32(0x13b,7,1,(a)) /* jmp.l */
155 #define M_JSR(a) OPWORD(0x13a,2,(a)) /* jsr %aX@ */
156 #define M_JSR_IMM(a) OPWORD_IMM32(0x13a,7,1,(a)) /* jsr.l */
157 #define M_BSR_IMM(a) OPWORD_IMM32(0x187,7,7,(a)) /* bsr.l */
158 #define M_JSR_PCREL(a) OPWORD_IMM16(0x13a,7,2,(a)) /* jsr.l (d16,PC) */
160 #define M_RET OPWORD(0x139,6,5) /* 0x4375 */
161 #define M_LINK(a,b) OPWORD_IMM16(0x139,2,(a), (b)) /* link */
162 #define M_UNLK(a) OPWORD(0x139, 3, (a)) /* unlk */
164 /* push and pop are implemented using move.l */
165 /* we need 3 variants, data, address and float registers */
166 /* also a POPALL and PUSHALL for verbose:call code, use them only there! */
167 #define M_IPUSH(a) OPWORD(0xbc,0,(a))
168 #define M_APUSH(a) OPWORD(0xbc,1,(a))
170 #define M_IPOP(a) OPWORD( ( (2<<6) | ((a) << 3) | 0 ), 3, REG_SP)
171 #define M_APOP(a) OPWORD( ( (2<<6) | ((a) << 3) | 1 ), 3, REG_SP) /* movea.l acutally */
174 #define M_IPUSH_IMM(a) OPWORD_IMM32(0x121,7,1, (a)) /* pea.l */
177 #define M_PUSHALL OPWORD_IMM16(0x123,2,REG_SP,0xFFFF) /* A0-A7, D0-D7 pushed onto stack */
178 #define M_POPALL OPWORD_IMM16(0x133,2,REG_SP,0xFFFF) /* A0-A7, D0-D7 poped off stack */
181 /* M_XLD(a,b,c)....M_XLD(destinationreg, addressbase, offset) */
182 #define M_ILD(a,b,c) OPWORD_IMM16( ( (2<<6) | ((a) << 3) | 0), 5, (b), (c))
183 #define M_ALD(a,b,c) OPWORD_IMM16( ( (2<<6) | ((a) << 3) | 1), 5, (b), (c))
184 #define M_LLD(a,b,c) do {\
185 M_ILD(GET_HIGH_REG(a), (b), (c));\
186 M_ILD(GET_LOW_REG (a), (b), (c)+4);\
189 #if !defined(ENABLE_SOFTFLOAT)
190 #define M_FLD(a,b,c) OPWORD_IMM32( 0x3c8, 5, (b), ( (( (0x11 << 10) | ((a)<<7) | 0x40 )<<16) | (((int16_t)(c)) & 0x0000ffff)) )
191 #define M_DLD(a,b,c) OPWORD_IMM32( 0x3c8, 5, (b), ( (( (0x15 << 10) | ((a)<<7) | 0x44 )<<16) | (((int16_t)(c)) & 0x0000ffff)) )
194 /* M_XST(a,b,c)....M_XST(sourceregister, addressbase, offset) */
195 #define M_IST(a,b,c) OPWORD_IMM16( ( (2<<6) | ((b) << 3) | 5), 0, (a), (c))
196 #define M_AST(a,b,c) OPWORD_IMM16( ( (2<<6) | ((b) << 3) | 5), 1, (a), (c))
197 #define M_LST(a,b,c) do {\
198 M_IST(GET_HIGH_REG(a), (b), (c));\
199 M_IST(GET_LOW_REG (a), (b), (c)+4);\
202 #if !defined(ENABLE_SOFTFLOAT)
203 #define M_FST(a,b,c) OPWORD_IMM32( 0x3c8, 5, (b), ( (( (0x19 <<10) | ((a)<<7) | 0 )<<16) | (((int16_t)(c)) & 0x0000ffff)) )
204 #define M_DST(a,b,c) OPWORD_IMM32( 0x3c8, 5, (b), ( (( (0x1d <<10) | ((a)<<7) | 0 )<<16) | (((int16_t)(c)) & 0x0000ffff)) )
205 #define M_FSTORE(a,b,c) OPWORD_IMM32( 0x3c8, 5, (b), ( ( (0xf << 12) | (1 << (7-(a))) ) <<16) | (((int16_t)(c)) & 0x0000ffff))
206 #define M_FLOAD(a,b,c) OPWORD_IMM32( 0x3c8, 5, (b), ( ( (0xd << 12) | (1 << (7-(a))) ) <<16) | (((int16_t)(c)) & 0x0000ffff))
209 /*M_XADD_IMM(a,b)...M_XADD_IMM(offset, reg) */
210 #define M_AADD_IMM(a,b) OPWORD_IMM32( ( (0xd<<6) | ((b)<<3) | 7), 7, 4, (a))
211 #define M_IADD_IMM(a,b) OPWORD_IMM32( ( (0xd<<6) | ((b)<<3) | 2), 7, 4, (a))
212 #define M_ISUB_IMM(a,b) M_IADD_IMM(-(a), (b))
214 /* M_OP(source, dest) ... dest (OP) source -> dest*/
215 #define M_ISUB(a,b) OPWORD ( ( (9<<6) | ((b)<<3) | 2), 0, (a)) /* sub.l */
216 #define M_ISUBX(a,b) OPWORD ( ( (9<<6) | ((b)<<3) | 6), 0, (a)) /* subx.l */
217 #define M_IADD(a,b) OPWORD ( ( (0xd<<6) | ((b)<<3) | 2), 0, (a)) /* add.l */
218 #define M_IADDX(a,b) OPWORD ( ( (0xd<<6) | ((b)<<3) | 6), 0, (a)) /* addx.l */
220 #define M_IMUL(a,b) OPWORD_IMM16 ( 0x130, 0, (a), ( ((b) << 12) | (1 << 11))) /* muls.l */
221 #define M_IDIV(a,b) OPWORD_IMM16 ( 0x131, 0, (a), ( ((b) << 12) | (1 << 11) | (b))) /* divs.l */
223 #define M_ISSL(a,b) OPWORD ( ( (0xe<<6) | ((a) << 3) | 6), 4, (b)) /* asl.l */
224 #define M_ISSR(a,b) OPWORD ( ( (0xe<<6) | ((a) << 3) | 2), 4, (b)) /* asr.l */
225 #define M_IUSR(a,b) OPWORD ( ( (0xe<<6) | ((a) << 3) | 2), 5, (b)) /* lsr.l */
227 #define M_IAND(a,b) OPWORD ( ( (0xc<<6) | ((b) << 3) | 2), 0, (a)) /* and.l */
228 #define M_IOR(a,b) OPWORD ( ( (0x8<<6) | ((b) << 3) | 2), 0, (a)) /* or.l */
229 #define M_IXOR(a,b) OPWORD ( ( (0xb<<6) | ((a) << 3) | 6), 0, (b)) /* eor.l */
232 /* M_IX_IMM(imm, register) */
233 #define M_IAND_IMM(a,b) OPWORD_IMM32( 0xa, 0, (b), (a)) /* andi.l # */
234 #define M_IOR_IMM(a,b) OPWORD_IMM32( 0x2, 0, (b), (a)) /* ori.l # */
235 #define M_IXOR_IMM(a,b) OPWORD_IMM32( 0x2a,0, (b), (a)) /* eori.l # */
238 /* ultra sepcial 3 register form, b%a = c, (a!=c) */
239 #define M_IREM(a,b,c) OPWORD_IMM16 ( 0x131, 0, (a), ( ((b) << 12) | (1 << 11) | (c))) /* rems.l */
242 #define M_INEG(a) OPWORD(0x112, 0, (a)) /* neg.l */
243 #define M_INEGX(a) OPWORD(0x102, 0, (a)) /* neg.l */
245 /* only generate opcode when condition true */
246 #define OPWORD_COND(c, u,v,w) \
248 if ( (c) ) { OPWORD( (u),(v),(w) ) } \
250 #define OPWORD_IMM16_COND(c, u,v,w,x) \
252 if ( (c) ) { OPWORD_IMM16( (u),(v),(w),(x) ) } \
254 /* assert on the opcode */
255 #define OPWORD_ASSERT(a, u,v,w) \
258 OPWORD( (u),(v),(w) ) \
261 /* M_XMOVE....M_XMOVE(sourcereg, destreg) */
262 #define M_INTMOVE(a,b) OPWORD_COND(((a) != (b)), ( ( 2<<6) | ((b) << 3) | 0), 0, (a));
263 #define M_ADRMOVE(a,b) OPWORD_COND(((a) != (b)), ( ( 2<<6) | ((b) << 3) | 1), 1, (a));
264 #define M_INT2ADRMOVE(a,b) OPWORD( ( (2<<6) | ((b) << 3) | 1), 0, (a));
265 #define M_ADR2INTMOVE(a,b) OPWORD( ( (2<<6) | ((b) << 3) | 0), 1, (a));
266 #define M_LNGMOVE(a,b) do {\
267 M_INTMOVE(GET_LOW_REG (a), GET_LOW_REG (b));\
268 M_INTMOVE(GET_HIGH_REG(a), GET_HIGH_REG(b));\
271 #if !defined(ENABLE_SOFTLFOAT)
272 #define M_FLTMOVE(a,b) OPWORD_IMM16_COND( ((a)!=(b)), 0x3c8, 0, 0, ((a)<<10) | ((b)<<7) | 0x40)
273 #define M_INT2FLTMOVE(a,b) OPWORD_IMM16( 0x3c8, 0, (a), ((0x11 << 10) | ((b) << 7) | 0x40 ))
274 #define M_DBLMOVE(a,b) OPWORD_IMM16_COND( ((a)!=(b)), 0x3c8, 0, 0, ((a)<<10) | ((b)<<7) | 0x44)
276 /* M_XTST....M_XTST(register) */
277 #define M_ITST(a) OPWORD(0x12a, 0, (a)) /* tst.l */
278 #define M_ATST(a) OPWORD(0x12a, 1, (a)) /* tst.l */
280 /* M_XCMPI....M_XMCPI(immideate, register) */
281 #define M_ICMP_IMM(a,b) OPWORD_IMM32( 0x32, 0, (b), (a))
283 #define M_ACMPI(a,b) OPWORD_IMM32( ( (0xb << 6) | ((b) << 3) | 7), 7, 4, (a)) /* cmpa.l # */
285 /* M_XCMP....M_XCMP(reg1, reg2) */
286 #define M_ICMP(b,a) OPWORD( ( (0xb << 6) | ((a) << 3) | 2), 0, (b)) /* cmp.l */
287 #define M_ACMP(b,a) OPWORD( ( (0xb << 6) | ((a) << 3) | 7), 1, (b)) /* cmpa.l */
290 /* All kind of branches one could ever possibly need, each with 16 and 32 bit displacement */
291 /* BRANCH16 and BRANCH32 are helpers */
292 #define BRANCH8(cond,imm) \
294 *((u2*)cd->mcodeptr) = (u2) (((0x6) << 12) | ((cond)<<8) | (int8_t)imm); \
298 #define BRANCH16(cond,imm) \
300 *((u2*)cd->mcodeptr) = (u2) (((0x6) << 12) | ((cond)<<8) | 0x00); \
302 *((int16_t*)(cd->mcodeptr)) = imm; \
305 #define BRANCH32(cond,imm) \
307 *((u2*)cd->mcodeptr) = (u2) (((0x6) << 12) | ((cond)<<8) | 0xff); \
309 *((int32_t*)(cd->mcodeptr)) = imm; \
313 #define M_BR_16(a) BRANCH16(0x0, (a)) /* branch always */
314 #define M_BR_32(a) BRANCH32(0x0, (a))
316 #define M_BCS(a) BRANCH8 (0x5, (a)) /* carry set */
318 #define M_BEQ(a) BRANCH8 (0x7, (a))
319 #define M_BEQ_16(a) BRANCH16(0x7, (a))
320 #define M_BEQ_32(a) BRANCH32(0x7, (a))
322 #define M_BNE(a) BRANCH8 (0x6, (a))
323 #define M_BNE_16(a) BRANCH16(0x6, (a))
324 #define M_BNE_32(a) BRANCH32(0x6, (a))
326 #define M_BLT(a) BRANCH8 (0xd, (a))
327 #define M_BLT_16(a) BRANCH16(0xd, (a))
328 #define M_BLT_32(a) BRANCH32(0xd, (a))
330 #define M_BGE(a) BRANCH8 (0xc, (a))
331 #define M_BGE_16(a) BRANCH16(0xc, (a))
332 #define M_BGE_32(a) BRANCH32(0xc, (a))
334 #define M_BGT(a) BRANCH8 (0xe, (a))
335 #define M_BGT_16(a) BRANCH16(0xe, (a))
336 #define M_BGT_32(a) BRANCH32(0xe, (a))
338 #define M_BLE(a) BRANCH8 (0xf, (a))
339 #define M_BLE_16(a) BRANCH16(0xf, (a))
340 #define M_BLE_32(a) BRANCH32(0xf, (a))
342 #define M_BHI(a) BRANCH8 (0x2, (a))
343 #define M_BHI_16(a) BRANCH16(0x2, (a))
344 #define M_BHI_32(a) BRANCH32(0x2, (a))
346 #define M_BLS(a) BRANCH8 (0x3, (a))
348 #define M_BMI(a) BRANCH8(0xb, (a))
349 #define M_BPL(a) BRANCH8(0xa, (a))
351 #define M_BNAN_16(a) M_ILLEGAL /* TODO */
352 #define M_BNAN_32(a) M_ILLEGAL
356 /* array store/load stuff */
357 /* M_LXXX(baseaddressregister, targetregister) */
358 /* M_SXXX(baseaddressregsiter, sourceregister) */
359 #define M_LBZX(a,c) OPWORD( ( (1<<6) | ((c) << 3) | 0), 2, (a)) /* move.l */
360 #define M_LHZX(a,c) OPWORD( ( (3<<6) | ((c) << 3) | 0), 2, (a))
361 #define M_LWZX(a,c) OPWORD( ( (2<<6) | ((c) << 3) | 0), 2, (a))
362 #define M_LAX(a,c) OPWORD( ( (2<<6) | ((c) << 3) | 1), 2, (a)) /* movea.l */
364 #define M_STBX(a,c) OPWORD( ( (1<<6) | ((a) << 3) | 2), 0, (c)) /* move.l */
365 #define M_STHX(a,c) OPWORD( ( (3<<6) | ((a) << 3) | 2), 0, (c))
366 #define M_STWX(a,c) OPWORD( ( (2<<6) | ((a) << 3) | 2), 0, (c))
367 #define M_STAX(a,c) OPWORD( ( (2<<6) | ((a) << 3) | 2), 1, (c)) /* movea.l */
370 #define M_BSEXT(a,b) OPWORD( ( (7<<6) | ((b) << 3) | 4), 0, (a)) /* mvs.b */
371 #define M_CZEXT(a,b) OPWORD( ( (7<<6) | ((b) << 3) | 7), 0, (a)) /* mvz.w */
372 #define M_SSEXT(a,b) OPWORD( ( (7<<6) | ((b) << 3) | 5), 0, (a)) /* mvs.w */
373 #define M_HSEXT(a,b) M_ILLEGAL
375 /* adds content of integer reg a to address register b, result is b */
376 #define M_AADDINT(a,b) OPWORD( ( (0xd<<6) | ((b) << 3) | 7), 0, (a)) /* adda.l */
377 #define M_ASUBINT(a,b) OPWORD( ( (0x9<<6) | ((b) << 3) | 7), 0, (a)) /* suba.l */
379 /* immideate a shift left int register b, immideate has 3 bits */
380 #define M_ISSL_IMM(a,b) OPWORD_ASSERT( ((a)<=7), ( (0xe<<6) | ((a) << 3) | 6), 1, (b)) /* lsl */
381 #define M_ISSR_IMM(a,b) OPWORD_ASSERT( ((a)<=7), ( (0xe<<6) | ((a) << 3) | 2), 0, (b)) /* lsl */
382 #define M_IUSR_IMM(a,b) OPWORD_ASSERT( ((a)<=7), ( (0xe<<6) | ((a) << 3) | 2), 1, (b)) /* lsl */
385 /* constant handling */
386 /* XCONST(constant value, register) */
387 #define LCONST(a,b) do {\
388 M_IMOV_IMM(((uint32_t)(a)), GET_LOW_REG((b)));\
389 M_IMOV_IMM(((uint32_t)(a>>32)), GET_HIGH_REG((b)));\
392 #if !defined(ENABLE_SOFTFLOAT)
393 #define FCONST(a,b) do {\
394 M_IMOV_IMM((a), REG_ITMP1);\
395 OPWORD_IMM16( 0x3c8, 0, REG_ITMP1, ( (0x11 << 10) | ((b)<<7) | 0x40) );\
399 #define M_TRAP_SETREGISTER(a) OPWORD( 0x128, 0, (a)) /* tst.b */
402 *((u2*)cd->mcodeptr) = (u2) ( 0x4e40 | (a) ); \
407 #if !defined(ENABLE_SOFTFLOAT)
409 #define M_FCMP(b,a) OPWORD_IMM16(0x3c8, 0, 0, ((a)<<10) | ((b)<<7) | 0x38 ) /* fcmp.d */
411 #define M_BFEQ(a) OPWORD_IMM16(0x3ca, 0, 0x01, (a))
412 #define M_BFLT(a) OPWORD_IMM16(0x3ca, 0, 0x14, (a))
413 #define M_BFGT(a) OPWORD_IMM16(0x3ca, 0, 0x12, (a))
414 #define M_BFUN(a) OPWORD_IMM16(0x3ca, 0, 0x10, (a))
416 #define M_FADD(a,b) OPWORD_IMM16(0x3c8, 0, 0, ((a) << 10) | ((b) << 7) | 0x62 ) /* fsadd */
417 #define M_DADD(a,b) OPWORD_IMM16(0x3c8, 0, 0, ((a) << 10) | ((b) << 7) | 0x66 ) /* fdadd */
419 #define M_FSUB(a,b) OPWORD_IMM16(0x3c8, 0, 0, ((a) << 10) | ((b) << 7) | 0x68 ) /* fssub */
420 #define M_DSUB(a,b) OPWORD_IMM16(0x3c8, 0, 0, ((a) << 10) | ((b) << 7) | 0x6c ) /* fdsub */
422 #define M_FMUL(a,b) OPWORD_IMM16(0x3c8, 0, 0, ((a) << 10) | ((b) << 7) | 0x63 ) /* fsmul */
423 #define M_DMUL(a,b) OPWORD_IMM16(0x3c8, 0, 0, ((a) << 10) | ((b) << 7) | 0x67 ) /* fdmul */
425 #define M_FDIV(a,b) OPWORD_IMM16(0x3c8, 0, 0, ((a) << 10) | ((b) << 7) | 0x60 ) /* fsdiv */
426 #define M_DDIV(a,b) OPWORD_IMM16(0x3c8, 0, 0, ((a) << 10) | ((b) << 7) | 0x64 ) /* fddiv */
428 #define M_D2F(a,b) OPWORD_IMM16(0x3c8, 0, 0, ((a) << 10) | ((b) << 7) | 0x44 ) /* fsmoved */
429 #define M_F2D(a,b) OPWORD_IMM16(0x3c8, 0, 0, ((a) << 10) | ((b) << 7) | 0x40 ) /* fdmoved */
431 #define M_FNEG(a,b) OPWORD_IMM16(0x3c8, 0, 0, ((a) << 10) | ((b) << 7) | 0x5a ) /* fneg.s */
432 #define M_DNEG(a,b) OPWORD_IMM16(0x3c8, 0, 0, ((a) << 10) | ((b) << 7) | 0x5e ) /* fneg.d */
435 #endif /* _CODEGEN_H */
438 * These are local overrides for various environment variables in Emacs.
439 * Please do not remove this and leave it at the end of the file, where
440 * Emacs will automagically detect them.
441 * ---------------------------------------------------------------------
444 * indent-tabs-mode: t
448 * vim:noexpandtab:sw=4:ts=4: