src/vendorcode/amd/cimx/sb900/SbType.h

   1
   2 /**
   3  * @file
   4  *
   5  * Southbridge CIMx configuration structure define
   6  *
   7  *
   8  *
   9  * @xrefitem bom "File Content Label" "Release Content"
  10  * @e project:      CIMx-SB
  11  * @e sub-project:
  12  * @e \$Revision:$   @e \$Date:$
  13  *
  14  */
  15 /*;********************************************************************************
  16 ;
  17 ; Copyright (c) 2011, Advanced Micro Devices, Inc.
  18 ; All rights reserved.
  19 ;
  20 ; Redistribution and use in source and binary forms, with or without
  21 ; modification, are permitted provided that the following conditions are met:
  22 ;     * Redistributions of source code must retain the above copyright
  23 ;       notice, this list of conditions and the following disclaimer.
  24 ;     * Redistributions in binary form must reproduce the above copyright
  25 ;       notice, this list of conditions and the following disclaimer in the
  26 ;       documentation and/or other materials provided with the distribution.
  27 ;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  28 ;       its contributors may be used to endorse or promote products derived
  29 ;       from this software without specific prior written permission.
  30 ;
  31 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  32 ; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  33 ; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  34 ; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  35 ; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  36 ; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  37 ; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  38 ; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  39 ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  40 ; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  41 ;
  42 ;*********************************************************************************/
  43
  44 #ifndef _AMD_SBTYPE_H_
  45 #define _AMD_SBTYPE_H_
  46
  47 #ifndef  LEGACY_BIOS_SUPPORT
  48   #pragma pack (push, 1)
  49 #endif
  50 /**
  51  * Entry point of Southbridge CIMx
  52  *
  53  *
  54  * @param[in] Param1  Southbridge CIMx Function ID.
  55  * @param[in] Param2  Southbridge Input Data.
  56  * @param[in] pConfig Southbridge configuration structure pointer.
  57  *
  58  */
  59 typedef unsigned int (*SBCIM_HOOK_ENTRY) (unsigned int Param1, unsigned int Param2, void* pConfig);
  60 /**
  61  * SMM_SERVICE_ROUTINE - Southbridge SMI service routine
  62  *
  63  */
  64 typedef  void (*SMM_SERVICE_ROUTINE) (void);
  65
  66
  67 /**
  68  * The STATIC platform information for CIMx Module.
  69  *
  70  */
  71 typedef struct _BUILDPARAM {
  72   unsigned char   BiosSize;           /**< BiosSize 00-00-01
  73                                    *   @par
  74                                    *   BIOSSize [2.0] - BIOS Image Size
  75                                    *    @li <b>0</b> - 1M
  76                                    *    @li <b>1</b> - 2M
  77                                    *    @li <b>3</b> - 4M
  78                                    *    @li <b>7</b> - 8M
  79                                    *  In Hudson-2, default ROM size is 1M Bytes, if your platform ROM bigger then 1M
  80                                    *  you have to set the ROM size outside CIMx module and before AGESA module get call
  81                                    *
  82                                    */
  83   unsigned char   LegacyFree;         /**< LegacyFree 00-00-02
  84                                    *   @par
  85                                    * Config Southbridge CIMx module for Legacy Free Mode
  86                                    */
  87   unsigned char   SpiSpeed;           /**< SpiSpeed  00-00-03
  88                                    *   @par
  89                                    *    SPI Speed [1.0] - the clock speed for non-fast read command
  90                                    *    @li <b>000</b> - Default
  91                                    *    @li <b>001</b> - 66Mhz
  92                                    *    @li <b>010</b> - 33Mhz
  93                                    *    @li <b>011</b> - 22Mhz
  94                                    *    @li <b>100</b> - 16.5Mhz
  95                                    *
  96                                    */
  97   unsigned char   ImcEnableOverWrite; /**< ImcEnableOverWrite  00-00-04
  98                                    *   @par
  99                                    *    Imc Enable OverWrite
 100                                    *    @li <b>00</b> - by default strapping
 101                                    *    @li <b>01</b> - On
 102                                    *    @li <b>10</b> - Off
 103                                    *
 104                                    */
 105   unsigned char   SpiFastSpeed;   /**< SpiFastSpeed  00-00-05
 106                                    *   @par
 107                                    *    SPI Speed [1.0] - the clock speed for fast read command
 108                                    *    @li <b>000</b> - Default
 109                                    *    @li <b>001</b> - 66Mhz
 110                                    *    @li <b>010</b> - 33Mhz
 111                                    *    @li <b>011</b> - 22Mhz
 112                                    *    @li <b>100</b> - 16.5Mhz
 113                                    *
 114                                    */
 115   unsigned char   SpiMode;   /**< SpiMode  00-00-06
 116                                    *   @par
 117                                    *     @li <b>000</b> - Default
 118                                    *     @li <b>101</b> - Qual-io 1-4-4
 119                                    *     @li <b>100</b> - Dual-io 1-2-2
 120                                    *     @li <b>011</b> - Qual-io 1-1-4
 121                                    *     @li <b>010</b> - Dual-io 1-1-2
 122                                    *     @li <b>111</b> - FastRead
 123                                    *     @li <b>110</b> - Normal
 124                                    */
 125   unsigned char   SpiAutoMode; /**< SpiAutoMode  00-00-07
 126                                    *   @par
 127                                    *    SPI Auto Mode
 128                                    *    @li <b>0</b> - Disabled
 129                                    *    @li <b>1</b> - Enabled
 130                                    */
 131 /** SpiBurstWrite - Reserved  00-00-08 */
 132   unsigned char   SpiBurstWrite;
 133   unsigned char   EcKbd;              /**< EcKbd  00-00-09
 134                                    *   @par
 135                                    *   EcKbd [16] - Platform use EC (as SIO) or SIO chip for PS/2 Keyboard and Mouse
 136                                    *    @li <b>0</b> - Use SIO PS/2 function.
 137                                    *    @li <b>1</b> - Use EC PS/2 function instead of SIO PS/2 function. **
 138                                    *    @li <b>**</b> When set 1, EC function have to enable, otherwise, CIMx treat as legacy-free system.
 139                                    */
 140 /** EcChannel0 - Reserved  00-00-10 */
 141   unsigned char   EcChannel0;
 142 /** UsbMsi - Reserved  00-00-11*/
 143   unsigned char   UsbMsi;
 144 /** HdAudioMsi - Reserved  00-00-12*/
 145   unsigned char   HdAudioMsi;
 146 /** LpcMsi - Reserved  00-00-13*/
 147   unsigned char   LpcMsi;
 148 /** PcibMsi - Reserved  00-00-14*/
 149   unsigned char   PcibMsi;
 150 /** AbMsi - Reserved  00-00-15*/
 151   unsigned char   AbMsi;
 152   unsigned char   SpiWriteSpeed;   /**< SpiReadSpeed  00-00-16
 153                                    *   @par
 154                                    *     TBD
 155                                    */
 156
 157   unsigned int   Smbus0BaseAddress;    /**< Smbus0BaseAddress  00-00-17
 158                                    *   @par
 159                                    * Smbus BASE Address
 160                                    */
 161   unsigned int   Smbus1BaseAddress;    /**< Smbus1BaseAddress  00-00-18
 162                                    *   @par
 163                                    * Smbus1 (ASF) BASE Address
 164                                    */
 165   unsigned int   SioPmeBaseAddress;    /**< SioPmeBaseAddress  00-00-19
 166                                    *   @par
 167                                    * SIO PME BASE Address
 168                                    */
 169   unsigned int   WatchDogTimerBase;    /**< WatchDogTimerBase  00-00-20
 170                                    *   @par
 171                                    *  Watch Dog Timer Address
 172                                    */
 173   unsigned int   GecShadowRomBase;     /**< GecShadowRomBase  00-00-21
 174                                    *   @par
 175                                    * GEC (NIC) SHADOWROM BASE Address
 176                                    */
 177   unsigned int   SpiRomBaseAddress;    /**< SpiRomBaseAddress  00-00-22
 178                                    *   @par
 179                                    * SPI ROM BASE Address
 180                                    */
 181   unsigned short   AcpiPm1EvtBlkAddr;    /**< AcpiPm1EvtBlkAddr  00-00-23
 182                                    *   @par
 183                                    * ACPI PM1 event block Address
 184                                    */
 185   unsigned short   AcpiPm1CntBlkAddr;    /**< AcpiPm1CntBlkAddr  00-00-24
 186                                    *   @par
 187                                    * ACPI PM1 Control block Address
 188                                    */
 189   unsigned short   AcpiPmTmrBlkAddr;     /**< AcpiPmTmrBlkAddr  00-00-25
 190                                    *   @par
 191                                    * ACPI PM timer block Address
 192                                    */
 193   unsigned short   CpuControlBlkAddr;    /**< CpuControlBlkAddr  00-00-26
 194                                    *   @par
 195                                    * ACPI CPU control block Address
 196                                    */
 197   unsigned short   AcpiGpe0BlkAddr;      /**< AcpiGpe0BlkAddr  00-00-27
 198                                    *   @par
 199                                    * ACPI GPE0 block Address
 200                                    */
 201   unsigned short   SmiCmdPortAddr;       /**< SmiCmdPortAddr  00-00-28
 202                                    *   @par
 203                                    * SMI command port Address
 204                                    */
 205   unsigned short   AcpiPmaCntBlkAddr;    /**< AcpiPmaCntBlkAddr  00-00-29
 206                                    *   @par
 207                                    * ACPI PMA Control block Address
 208                                    */
 209   unsigned int   HpetBase;             /**< HpetBase  00-00-30
 210                                    *   @par
 211                                    * HPET Base address
 212                                    */
 213   unsigned int   SataIDESsid;          /**< SataIDESsid  00-00-31
 214                                    *   @par
 215                                    * SATA IDE mode SSID
 216                                    */
 217   unsigned int   SataRAIDSsid;         /**< SataRAIDSsid  00-00-32
 218                                    *   @par
 219                                    *  SATA RAID mode SSID
 220                                    */
 221   unsigned int   SataRAID5Ssid;        /**< SataRAID5Ssid  00-00-33
 222                                    *   @par
 223                                    * SATA RAID5 mode SSID
 224                                    */
 225   unsigned int   SataAHCISsid;         /**< SataAHCISsid  00-00-34
 226                                    *   @par
 227                                    * SATA AHCI mode SSID
 228                                    */
 229   unsigned int   OhciSsid;             /**< OhciSsid  00-00-35
 230                                    *   @par
 231                                    * OHCI Controller SSID
 232                                    */
 233   unsigned int   EhciSsid;             /**< EhciSsid  00-00-36
 234                                    *   @par
 235                                    * EHCI Controller SSID
 236                                    */
 237   unsigned int   Ohci4Ssid;            /**< Ohci4Ssid  00-00-37
 238                                    *   @par
 239                                    * OHCI4 Controller SSID (Force USB 1.1 mode)
 240                                    */
 241   unsigned int   SmbusSsid;            /**< SmbusSsid  00-00-38
 242                                    *   @par
 243                                    *  SMBUS controller SSID
 244                                    */
 245   unsigned int   IdeSsid;              /**< IdeSsid  00-00-39
 246                                    *   @par
 247                                    * IDE (Sata) controller SSID
 248                                    */
 249   unsigned int   AzaliaSsid;           /**< AzaliaSsid  00-00-40
 250                                    *   @par
 251                                    * HD Audio controller SSID
 252                                    */
 253   unsigned int   LpcSsid;              /**< LpcSsid  00-00-41
 254                                    *   @par
 255                                    * LPC controller SSID
 256                                    */
 257   unsigned int   PCIBSsid;             /**< PCIBSsid  00-00-42
 258                                    *   @par
 259                                    * PCIB controller SSID
 260                                    */
 261 } BUILDPARAM;
 262
 263 /**
 264  * The Hwm temprature parameter  for CIMx Module. *
 265  */
 266 typedef struct _HWM_temp_par_struct {
 267   unsigned short At;            ///< At
 268   unsigned short Ct;          ///< Ct
 269   unsigned char Mode;             ///< Mode BIT0:HiRatio BIT1:HiCurrent
 270 } HWM_temp_par_struct;
 271
 272 /**
 273  * The Hwm current struct  for CIMx Module. *
 274  */
 275 typedef struct _HWM_cur_struct {
 276   unsigned short fanSpeed[5];            ///< fanSpeed
 277   unsigned short temperature[5];          ///< temperature
 278   unsigned short voltage[8];             ///< voltage
 279 } HWM_cur_struct;
 280
 281 /**
 282  * The Hwm control struct  for CIMx Module.
 283  *
 284  */
 285 typedef struct _HWM_fan_ctl_struct {
 286   unsigned char InputControl_reg00;       ///< InputControl_reg00
 287   unsigned char Control_reg01;            ///< Control_reg01
 288   unsigned char Freq_reg02;               ///< Freq_reg02
 289   unsigned char LowDuty_reg03;            ///< LowDuty_reg03
 290   unsigned char MedDuty_reg04;            ///< MedDuty_reg04
 291   unsigned char Multiplier_reg05;         ///< Multiplier_reg05
 292   unsigned short LowTemp_reg06;           ///< LowTemp_reg06
 293   unsigned short MedTemp_reg08;           ///< MedTemp_reg08
 294   unsigned short HighTemp_reg0A;          ///< HighTemp_reg0A
 295   unsigned char LinearRange_reg0C;        ///< LinearRange_reg0C
 296   unsigned char LinearHoldCount_reg0D;    ///< LinearHoldCount_reg0D
 297 } HWM_fan_ctl_struct;
 298
 299 /**
 300  * The Hwm struct  for CIMx Module. *
 301  */
 302 typedef struct _HWM_struct {
 303   unsigned char hwmEnable;            ///< hwmEnable
 304   unsigned int hwmControl;                    /**< hwmControl
 305                                         *   @par
 306                                         * HWM control configuration
 307                                         *    @li <b>0</b> - HWM is Enabled
 308                                         *    @li <b>1</b> - IMC is Enabled
 309                                         */
 310   unsigned char fanSampleFreqDiv;            ///< fanSampleFreqDiv
 311   unsigned char hwmSbtsiAutoPoll;            ///< hwmSbtsiAutoPoll
 312   unsigned char hwmSbtsiAutoPollStarted;            ///< hwmSbtsiAutoPollStarted
 313   unsigned char fanLinearEnhanceEn;          ///< fanLinearEnhanceEn
 314   unsigned char fanLinearHoldFix;            ///< fanLinearHoldFix
 315   unsigned char fanLinearRangeOutLimit;      ///< fanLinearRangeOutLimit
 316   unsigned char hwmSbtsiMode;            ///< hwmSbtsiMode
 317   unsigned short hwmCalibrationFactor;            ///< hwmEfuseFactor
 318   HWM_cur_struct hwmCurrent;            ///< hwmCurrent
 319   HWM_cur_struct hwmCurrentRaw;            ///< hwmCurrentRaw
 320   HWM_temp_par_struct hwmTempPar[5];          ///< hwmTempPar
 321   HWM_fan_ctl_struct hwmFanControl[5];             ///< hwmFanControl
 322   HWM_fan_ctl_struct hwmFanControlCooked[5];             ///< hwmFanControlCooked
 323 } HWM_struct;
 324
 325 /**
 326  * The IMC struct  for CIMx Module. *
 327  */
 328 typedef struct _IMC_struct {
 329   unsigned char imcEnable;            ///< imcEnable
 330   unsigned char imcEnabled;            ///< imcEnabled
 331   unsigned char imcSureBootTimer;            ///< imcSureBootTimer
 332 } IMC_struct;
 333
 334 /**
 335  * The EC fan MSGREG struct  for CIMx Module. *
 336  */
 337 typedef struct _EC_struct {
 338   unsigned char  MSGFun81zone0MSGREG0;  ///<Thermal zone
 339   unsigned char  MSGFun81zone0MSGREG1;  ///<Thermal zone
 340   unsigned char  MSGFun81zone0MSGREG2;  ///<Thermal zone control byte 1
 341   unsigned char  MSGFun81zone0MSGREG3;  ///<Thermal zone control byte 2
 342   unsigned char  MSGFun81zone0MSGREG4;  ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
 343   unsigned char  MSGFun81zone0MSGREG5;  ///<Hysteresis inforamtion
 344   unsigned char  MSGFun81zone0MSGREG6;  ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
 345   unsigned char  MSGFun81zone0MSGREG7;  ///<Bit[1:0]: 0 - 2,  SMBUS bus number where the SMBUS based temperature sensor is located.
 346   unsigned char  MSGFun81zone0MSGREG8;  ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
 347   unsigned char  MSGFun81zone0MSGREG9;  ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
 348
 349   //EC LDN9 funtion 81 zone 1
 350   unsigned char  MSGFun81zone1MSGREG0;  ///<Thermal zone
 351   unsigned char  MSGFun81zone1MSGREG1;  ///<Thermal zone
 352   unsigned char  MSGFun81zone1MSGREG2;  ///<Thermal zone control byte 1
 353   unsigned char  MSGFun81zone1MSGREG3;  ///<Thermal zone control byte 2
 354   unsigned char  MSGFun81zone1MSGREG4;  ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
 355   unsigned char  MSGFun81zone1MSGREG5;  ///<Hysteresis inforamtion
 356   unsigned char  MSGFun81zone1MSGREG6;  ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
 357   unsigned char  MSGFun81zone1MSGREG7;  ///<Bit[1:0]: 0 - 2,  SMBUS bus number where the SMBUS based temperature sensor is located.
 358   unsigned char  MSGFun81zone1MSGREG8;  ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
 359   unsigned char  MSGFun81zone1MSGREG9;  ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
 360
 361   //EC LDN9 funtion 81 zone 2
 362   unsigned char  MSGFun81zone2MSGREG0;  ///<Thermal zone
 363   unsigned char  MSGFun81zone2MSGREG1;  ///<Thermal zone
 364   unsigned char  MSGFun81zone2MSGREG2;  ///<Thermal zone control byte 1
 365   unsigned char  MSGFun81zone2MSGREG3;  ///<Thermal zone control byte 2
 366   unsigned char  MSGFun81zone2MSGREG4;  ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
 367   unsigned char  MSGFun81zone2MSGREG5;  ///<Hysteresis inforamtion
 368   unsigned char  MSGFun81zone2MSGREG6;  ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
 369   unsigned char  MSGFun81zone2MSGREG7;  ///<Bit[1:0]: 0 - 2,  SMBUS bus number where the SMBUS based temperature sensor is located.
 370   unsigned char  MSGFun81zone2MSGREG8;  ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
 371   unsigned char  MSGFun81zone2MSGREG9;  ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
 372
 373   //EC LDN9 funtion 81 zone 3
 374   unsigned char  MSGFun81zone3MSGREG0;  ///<Thermal zone
 375   unsigned char  MSGFun81zone3MSGREG1;  ///<Thermal zone
 376   unsigned char  MSGFun81zone3MSGREG2;  ///<Thermal zone control byte 1
 377   unsigned char  MSGFun81zone3MSGREG3;  ///<Thermal zone control byte 2
 378   unsigned char  MSGFun81zone3MSGREG4;  ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
 379   unsigned char  MSGFun81zone3MSGREG5;  ///<Hysteresis inforamtion
 380   unsigned char  MSGFun81zone3MSGREG6;  ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
 381   unsigned char  MSGFun81zone3MSGREG7;  ///<Bit[1:0]: 0 - 2,  SMBUS bus number where the SMBUS based temperature sensor is located.
 382   unsigned char  MSGFun81zone3MSGREG8;  ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
 383   unsigned char  MSGFun81zone3MSGREG9;  ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
 384
 385   //EC LDN9 funtion 83 zone 0
 386   unsigned char  MSGFun83zone0MSGREG0;  ///<Thermal zone
 387   unsigned char  MSGFun83zone0MSGREG1;  ///<Thermal zone
 388   unsigned char  MSGFun83zone0MSGREG2;  ///<_AC0
 389   unsigned char  MSGFun83zone0MSGREG3;  ///<_AC1
 390   unsigned char  MSGFun83zone0MSGREG4;  ///<_AC2
 391   unsigned char  MSGFun83zone0MSGREG5;  ///<_AC3
 392   unsigned char  MSGFun83zone0MSGREG6;  ///<_AC4
 393   unsigned char  MSGFun83zone0MSGREG7;  ///<_AC5
 394   unsigned char  MSGFun83zone0MSGREG8;  ///<_AC6
 395   unsigned char  MSGFun83zone0MSGREG9;  ///<_AC7
 396   unsigned char  MSGFun83zone0MSGREGA;  ///<_CRT
 397   unsigned char  MSGFun83zone0MSGREGB;  ///<_PSV
 398
 399   //EC LDN9 funtion 83 zone 1
 400   unsigned char  MSGFun83zone1MSGREG0;  ///<Thermal zone
 401   unsigned char  MSGFun83zone1MSGREG1;  ///<Thermal zone
 402   unsigned char  MSGFun83zone1MSGREG2;  ///<_AC0
 403   unsigned char  MSGFun83zone1MSGREG3;  ///<_AC1
 404   unsigned char  MSGFun83zone1MSGREG4;  ///<_AC2
 405   unsigned char  MSGFun83zone1MSGREG5;  ///<_AC3
 406   unsigned char  MSGFun83zone1MSGREG6;  ///<_AC4
 407   unsigned char  MSGFun83zone1MSGREG7;  ///<_AC5
 408   unsigned char  MSGFun83zone1MSGREG8;  ///<_AC6
 409   unsigned char  MSGFun83zone1MSGREG9;  ///<_AC7
 410   unsigned char  MSGFun83zone1MSGREGA;  ///<_CRT
 411   unsigned char  MSGFun83zone1MSGREGB;  ///<_PSV
 412
 413   //EC LDN9 funtion 83 zone 2
 414   unsigned char  MSGFun83zone2MSGREG0;  ///<Thermal zone
 415   unsigned char  MSGFun83zone2MSGREG1;  ///<Thermal zone
 416   unsigned char  MSGFun83zone2MSGREG2;  ///<_AC0
 417   unsigned char  MSGFun83zone2MSGREG3;  ///<_AC1
 418   unsigned char  MSGFun83zone2MSGREG4;  ///<_AC2
 419   unsigned char  MSGFun83zone2MSGREG5;  ///<_AC3
 420   unsigned char  MSGFun83zone2MSGREG6;  ///<_AC4
 421   unsigned char  MSGFun83zone2MSGREG7;  ///<_AC5
 422   unsigned char  MSGFun83zone2MSGREG8;  ///<_AC6
 423   unsigned char  MSGFun83zone2MSGREG9;  ///<_AC7
 424   unsigned char  MSGFun83zone2MSGREGA;  ///<_CRT
 425   unsigned char  MSGFun83zone2MSGREGB;  ///<_PSV
 426
 427   //EC LDN9 funtion 83 zone 3
 428   unsigned char  MSGFun83zone3MSGREG0;  ///<Thermal zone
 429   unsigned char  MSGFun83zone3MSGREG1;  ///<Thermal zone
 430   unsigned char  MSGFun83zone3MSGREG2;  ///<_AC0
 431   unsigned char  MSGFun83zone3MSGREG3;  ///<_AC1
 432   unsigned char  MSGFun83zone3MSGREG4;  ///<_AC2
 433   unsigned char  MSGFun83zone3MSGREG5;  ///<_AC3
 434   unsigned char  MSGFun83zone3MSGREG6;  ///<_AC4
 435   unsigned char  MSGFun83zone3MSGREG7;  ///<_AC5
 436   unsigned char  MSGFun83zone3MSGREG8;  ///<_AC6
 437   unsigned char  MSGFun83zone3MSGREG9;  ///<_AC7
 438   unsigned char  MSGFun83zone3MSGREGA;  ///<_CRT
 439   unsigned char  MSGFun83zone3MSGREGB;  ///<_PSV
 440
 441   //EC LDN9 funtion 85 zone 0
 442   unsigned char  MSGFun85zone0MSGREG0;  ///<Thermal zone
 443   unsigned char  MSGFun85zone0MSGREG1;  ///<Thermal zone
 444   unsigned char  MSGFun85zone0MSGREG2;  ///<AL0 PWM level in percentage (0 - 100%)
 445   unsigned char  MSGFun85zone0MSGREG3;  ///<AL1 PWM level in percentage (0 - 100%)
 446   unsigned char  MSGFun85zone0MSGREG4;  ///<AL2 PWM level in percentage (0 - 100%)
 447   unsigned char  MSGFun85zone0MSGREG5;  ///<AL3 PWM level in percentage (0 - 100%)
 448   unsigned char  MSGFun85zone0MSGREG6;  ///<AL4 PWM level in percentage (0 - 100%)
 449   unsigned char  MSGFun85zone0MSGREG7;  ///<AL5 PWM level in percentage (0 - 100%)
 450   unsigned char  MSGFun85zone0MSGREG8;  ///<AL6 PWM level in percentage (0 - 100%)
 451   unsigned char  MSGFun85zone0MSGREG9;  ///<AL7 PWM level in percentage (0 - 100%)
 452
 453   //EC LDN9 funtion 85 zone 1
 454   unsigned char  MSGFun85zone1MSGREG0;  ///<Thermal zone
 455   unsigned char  MSGFun85zone1MSGREG1;  ///<Thermal zone
 456   unsigned char  MSGFun85zone1MSGREG2;  ///<AL0 PWM level in percentage (0 - 100%)
 457   unsigned char  MSGFun85zone1MSGREG3;  ///<AL1 PWM level in percentage (0 - 100%)
 458   unsigned char  MSGFun85zone1MSGREG4;  ///<AL2 PWM level in percentage (0 - 100%)
 459   unsigned char  MSGFun85zone1MSGREG5;  ///<AL3 PWM level in percentage (0 - 100%)
 460   unsigned char  MSGFun85zone1MSGREG6;  ///<AL4 PWM level in percentage (0 - 100%)
 461   unsigned char  MSGFun85zone1MSGREG7;  ///<AL5 PWM level in percentage (0 - 100%)
 462   unsigned char  MSGFun85zone1MSGREG8;  ///<AL6 PWM level in percentage (0 - 100%)
 463   unsigned char  MSGFun85zone1MSGREG9;  ///<AL7 PWM level in percentage (0 - 100%)
 464
 465   //EC LDN9 funtion 85 zone 2
 466   unsigned char  MSGFun85zone2MSGREG0;  ///<Thermal zone
 467   unsigned char  MSGFun85zone2MSGREG1;  ///<Thermal zone
 468   unsigned char  MSGFun85zone2MSGREG2;  ///<AL0 PWM level in percentage (0 - 100%)
 469   unsigned char  MSGFun85zone2MSGREG3;  ///<AL1 PWM level in percentage (0 - 100%)
 470   unsigned char  MSGFun85zone2MSGREG4;  ///<AL2 PWM level in percentage (0 - 100%)
 471   unsigned char  MSGFun85zone2MSGREG5;  ///<AL3 PWM level in percentage (0 - 100%)
 472   unsigned char  MSGFun85zone2MSGREG6;  ///<AL4 PWM level in percentage (0 - 100%)
 473   unsigned char  MSGFun85zone2MSGREG7;  ///<AL5 PWM level in percentage (0 - 100%)
 474   unsigned char  MSGFun85zone2MSGREG8;  ///<AL6 PWM level in percentage (0 - 100%)
 475   unsigned char  MSGFun85zone2MSGREG9;  ///<AL7 PWM level in percentage (0 - 100%)
 476
 477   //EC LDN9 funtion 85 zone 3
 478   unsigned char  MSGFun85zone3MSGREG0;  ///<Thermal zone
 479   unsigned char  MSGFun85zone3MSGREG1;  ///<Thermal zone
 480   unsigned char  MSGFun85zone3MSGREG2;  ///<AL0 PWM level in percentage (0 - 100%)
 481   unsigned char  MSGFun85zone3MSGREG3;  ///<AL1 PWM level in percentage (0 - 100%)
 482   unsigned char  MSGFun85zone3MSGREG4;  ///<AL2 PWM level in percentage (0 - 100%)
 483   unsigned char  MSGFun85zone3MSGREG5;  ///<AL3 PWM level in percentage (0 - 100%)
 484   unsigned char  MSGFun85zone3MSGREG6;  ///<AL4 PWM level in percentage (0 - 100%)
 485   unsigned char  MSGFun85zone3MSGREG7;  ///<AL5 PWM level in percentage (0 - 100%)
 486   unsigned char  MSGFun85zone3MSGREG8;  ///<AL6 PWM level in percentage (0 - 100%)
 487   unsigned char  MSGFun85zone3MSGREG9;  ///<AL7 PWM level in percentage (0 - 100%)
 488
 489   //EC LDN9 funtion 89 TEMPIN channel 0
 490   unsigned char  MSGFun89zone0MSGREG0;  ///<Thermal zone
 491   unsigned char  MSGFun89zone0MSGREG1;  ///<Thermal zone
 492   unsigned char  MSGFun89zone0MSGREG2;  ///<At DWORD bit 0-7
 493   unsigned char  MSGFun89zone0MSGREG3;  ///<At DWORD bit 15-8
 494   unsigned char  MSGFun89zone0MSGREG4;  ///<At DWORD bit 23-16
 495   unsigned char  MSGFun89zone0MSGREG5;  ///<At DWORD bit 31-24
 496   unsigned char  MSGFun89zone0MSGREG6;  ///<Ct DWORD bit 0-7
 497   unsigned char  MSGFun89zone0MSGREG7;  ///<Ct DWORD bit 15-8
 498   unsigned char  MSGFun89zone0MSGREG8;  ///<Ct DWORD bit 23-16
 499   unsigned char  MSGFun89zone0MSGREG9;  ///<Ct DWORD bit 31-24
 500   unsigned char  MSGFun89zone0MSGREGA;  ///<Mode bit 0-7
 501
 502   //EC LDN9 funtion 89 TEMPIN channel 1
 503   unsigned char  MSGFun89zone1MSGREG0;  ///<Thermal zone
 504   unsigned char  MSGFun89zone1MSGREG1;  ///<Thermal zone
 505   unsigned char  MSGFun89zone1MSGREG2;  ///<At DWORD bit 0-7
 506   unsigned char  MSGFun89zone1MSGREG3;  ///<At DWORD bit 15-8
 507   unsigned char  MSGFun89zone1MSGREG4;  ///<At DWORD bit 23-16
 508   unsigned char  MSGFun89zone1MSGREG5;  ///<At DWORD bit 31-24
 509   unsigned char  MSGFun89zone1MSGREG6;  ///<Ct DWORD bit 0-7
 510   unsigned char  MSGFun89zone1MSGREG7;  ///<Ct DWORD bit 15-8
 511   unsigned char  MSGFun89zone1MSGREG8;  ///<Ct DWORD bit 23-16
 512   unsigned char  MSGFun89zone1MSGREG9;  ///<Ct DWORD bit 31-24
 513   unsigned char  MSGFun89zone1MSGREGA;  ///<Mode bit 0-7
 514
 515   //EC LDN9 funtion 89 TEMPIN channel 2
 516   unsigned char  MSGFun89zone2MSGREG0;  ///<Thermal zone
 517   unsigned char  MSGFun89zone2MSGREG1;  ///<Thermal zone
 518   unsigned char  MSGFun89zone2MSGREG2;  ///<At DWORD bit 0-7
 519   unsigned char  MSGFun89zone2MSGREG3;  ///<At DWORD bit 15-8
 520   unsigned char  MSGFun89zone2MSGREG4;  ///<At DWORD bit 23-16
 521   unsigned char  MSGFun89zone2MSGREG5;  ///<At DWORD bit 31-24
 522   unsigned char  MSGFun89zone2MSGREG6;  ///<Ct DWORD bit 0-7
 523   unsigned char  MSGFun89zone2MSGREG7;  ///<Ct DWORD bit 15-8
 524   unsigned char  MSGFun89zone2MSGREG8;  ///<Ct DWORD bit 23-16
 525   unsigned char  MSGFun89zone2MSGREG9;  ///<Ct DWORD bit 31-24
 526   unsigned char  MSGFun89zone2MSGREGA;  ///<Mode bit 0-7
 527
 528   //EC LDN9 funtion 89 TEMPIN channel 3
 529   unsigned char  MSGFun89zone3MSGREG0;  ///<Thermal zone
 530   unsigned char  MSGFun89zone3MSGREG1;  ///<Thermal zone
 531   unsigned char  MSGFun89zone3MSGREG2;  ///<At DWORD bit 0-7
 532   unsigned char  MSGFun89zone3MSGREG3;  ///<At DWORD bit 15-8
 533   unsigned char  MSGFun89zone3MSGREG4;  ///<At DWORD bit 23-16
 534   unsigned char  MSGFun89zone3MSGREG5;  ///<At DWORD bit 31-24
 535   unsigned char  MSGFun89zone3MSGREG6;  ///<Ct DWORD bit 0-7
 536   unsigned char  MSGFun89zone3MSGREG7;  ///<Ct DWORD bit 15-8
 537   unsigned char  MSGFun89zone3MSGREG8;  ///<Ct DWORD bit 23-16
 538   unsigned char  MSGFun89zone3MSGREG9;  ///<Ct DWORD bit 31-24
 539   unsigned char  MSGFun89zone3MSGREGA;  ///<Mode bit 0-7
 540
 541   // FLAG for Fun83/85/89 support
 542   unsigned short IMCFUNSupportBitMap;   ///< Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3;
 543 } EC_struct;
 544
 545 /** SBGPPPORTCONFIG - Southbridge GPP port config structure */
 546 typedef struct {
 547   unsigned char   PortPresent;     /**< Port connection
 548                                    *   @par
 549                                    *    @li <b>0</b> - Port doesn't have slot. No need to train the link
 550                                    *    @li <b>1</b> - Port connection defined and needs to be trained
 551                                    */
 552   unsigned char   PortDetected;    /**< Link training status
 553                                    *   @par
 554                                    *    @li <b>0</b> - EP not detected
 555                                    *    @li <b>1</b> - EP detected
 556                                    */
 557   unsigned char   PortIsGen2;      /**< Port link speed configuration
 558                                    *   @par
 559                                    *    @li <b>00</b> - Auto
 560                                    *    @li <b>01</b> - Forced GEN1
 561                                    *    @li <b>10</b> - Forced GEN2
 562                                    *    @li <b>11</b> - Reserved
 563                                    */
 564
 565   unsigned char   PortHotPlug;     /**< Support hot plug?
 566                                    *   @par
 567                                    *    @li <b>0</b> - No support
 568                                    *    @li <b>1</b> - support
 569                                    */
 570 } SBGPPPORTCONFIG;
 571
 572 /** CODECENTRY - Southbridge HD Audio OEM Codec structure */
 573 typedef struct _CODECENTRY {
 574 /** Nid - Reserved ?? */
 575   unsigned char Nid;
 576 /** Byte40 - Reserved ?? */
 577   unsigned int Byte40;
 578 } CODECENTRY;
 579
 580 /** CODECTBLLIST - Southbridge HD Audio Codec table list */
 581 typedef struct _CODECTBLLIST {
 582 /** CodecID - Codec ID */
 583   unsigned int   CodecID;
 584 /** CodecTablePtr - Codec table pointer */
 585   CODECENTRY* CodecTablePtr;
 586 } CODECTBLLIST;
 587
 588 /** Sata Controller structure */
 589 typedef struct _SATAST {
 590   unsigned char   SataModeReg;               /** SataModeReg - Reserved 00-01-00*/
 591   unsigned char   SataController;            /**< SataController 00-01-01
 592                                         *   @par
 593                                         * Sata Controller
 594                                         *    @li <b>0</b> - disable
 595                                         *    @li <b>1</b> - enable
 596                                         */
 597   unsigned char   SataIdeCombMdPriSecOpt;    /**< SataIdeCombMdPriSecOpt - Reserved 00-01-02*/
 598   unsigned char   SataSetMaxGen2;            /**< SataSetMaxGen2 00-01-03
 599                                         *   @par
 600                                         * Sata Controller Set to Max Gen2 mode
 601                                         *    @li <b>0</b> - disable
 602                                         *    @li <b>1</b> - enable
 603                                         */
 604   unsigned char   SataIdeCombinedMode;       /**< SataIdeCombinedMode 00-01-04
 605                                         *   @par
 606                                         * Sata IDE Controller set to Combined Mode
 607                                         *    @li <b>0</b> - disable
 608                                         *    @li <b>1</b> - enable
 609                                         */
 610 /** SataClkMode - Reserved 00-01-05 */
 611   unsigned char   SataClkMode;              // 4:7
 612 } SATAST;
 613
 614 /** _USBST Controller structure
 615  *
 616  * Usb Ohci1 Contoller is define at BIT0
 617  *   - 0:disable 1:enable
 618  *                             (Bus 0 Dev 18 Func0) *
 619  * Usb Ehci1 Contoller is define at BIT1
 620  *   - 0:disable 1:enable
 621  *                             (Bus 0 Dev 18 Func2) *
 622  * Usb Ohci2 Contoller is define at BIT2
 623  *   - 0:disable 1:enable
 624  *                             (Bus 0 Dev 19 Func0) *
 625  * Usb Ehci2 Contoller is define at BIT3
 626  *   - 0:disable 1:enable
 627  *                             (Bus 0 Dev 19 Func2) *
 628  * Usb Ohci3 Contoller is define at BIT4
 629  *   - 0:disable 1:enable
 630  *                             (Bus 0 Dev 22 Func0) *
 631  * Usb Ehci3 Contoller is define at BIT5
 632  *   - 0:disable 1:enable
 633  *                             (Bus 0 Dev 22 Func2) *
 634  * Usb Ohci4 Contoller is define at BIT6
 635  *   - 0:disable 1:enable
 636  *                             (Bus 0 Dev 20 Func5) *
 637  */
 638 typedef struct _USBST {
 639   unsigned char   UsbModeReg;               /** UsbModeReg - Reserved */
 640   unsigned char  Ohci1;                      ///< Ohci0 controller - 0:disable, 1:enable
 641   unsigned char  Ehci1;                      ///< Ehci1 controller - 0:disable, 1:enable
 642   unsigned char  Ohci2;                      ///< Ohci2 controller - 0:disable, 1:enable
 643   unsigned char  Ehci2;                      ///< Ehci2 controller - 0:disable, 1:enable
 644   unsigned char  Ohci3;                      ///< Ohci3 controller - 0:disable, 1:enable
 645   unsigned char  Ehci3;                      ///< Ehci3 controller - 0:disable, 1:enable
 646   unsigned char  Ohci4;                      ///< Ohci4 controller - 0:disable, 1:enable
 647 } USBST;
 648
 649
 650 /** SATAPORTST - SATA PORT structure
 651  *
 652  */
 653 typedef struct _SATAPORTST {
 654   unsigned char    SataPortPowerReg;         /** SataPortPowerReg - Reserved */
 655   unsigned char  PORT0;                      ///< PORT0 - 0:disable, 1:enable
 656   unsigned char  PORT1;                      ///< PORT1 - 0:disable, 1:enable
 657   unsigned char  PORT2;                      ///< PORT2 - 0:disable, 1:enable
 658   unsigned char  PORT3;                      ///< PORT3 - 0:disable, 1:enable
 659   unsigned char  PORT4;                      ///< PORT4 - 0:disable, 1:enable
 660   unsigned char  PORT5;                      ///< PORT5 - 0:disable, 1:enable
 661   unsigned char  PORT6;                      ///< PORT6 - 0:disable, 1:enable
 662   unsigned char  PORT7;                      ///< PORT7 - 0:disable, 1:enable
 663 } SATAPORTST;
 664
 665
 666 ///< _SATAPORTMD - Force Each PORT to GEN1/GEN2 mode
 667 typedef struct _SATAPORTMD {
 668   unsigned short   SataPortMode;             /** SataPortMode - Reserved */
 669   unsigned short  PORT0;                     ///< PORT0 - set BIT0 to GEN1, BIT1 - PORT0 set to GEN2
 670   unsigned short  PORT1;                     ///< PORT1 - set BIT2 to GEN1, BIT3 - PORT1 set to GEN2
 671   unsigned short  PORT2;                     ///< PORT2 - set BIT4 to GEN1, BIT5 - PORT2 set to GEN2
 672   unsigned short  PORT3;                     ///< PORT3 - set BIT6 to GEN1, BIT7 - PORT3 set to GEN2
 673   unsigned short  PORT4;                     ///< PORT4 - set BIT8 to GEN1, BIT9 - PORT4 set to GEN2
 674   unsigned short  PORT5;                     ///< PORT5 - set BIT10 to GEN1, BIT11 - PORT5 set to GEN2
 675   unsigned short  PORT6;                     ///< PORT6 - set BIT12 to GEN1, BIT13 - PORT6 set to GEN2
 676   unsigned short  PORT7;                     ///< PORT7 - set BIT14 to GEN1, BIT15 - PORT7 set to GEN2
 677 } SATAPORTMD;
 678
 679 /**
 680  * _AZALIAPIN - HID Azalia or GPIO define structure.
 681  *
 682  */
 683 typedef struct _AZALIAPIN {
 684   unsigned char   AzaliaSdinPin;             ///< @todo Style_Analyzer: Add Doxygen comments to struct entry
 685   unsigned char   AzaliaSdin0;               /**< AzaliaSdin0
 686                                         *   @par
 687                                         * SDIN0 is define at BIT0 & BIT1
 688                                         *    @li <b>00</b> - GPIO PIN
 689                                         *    @li <b>10</b> - As a Azalia SDIN pin
 690                                         */
 691   unsigned char   AzaliaSdin1;               /**< AzaliaSdin1
 692                                         *   @par
 693                                         * SDIN0 is define at BIT2 & BIT3
 694                                         *    @li <b>00</b> - GPIO PIN
 695                                         *    @li <b>10</b> - As a Azalia SDIN pin
 696                                         */
 697   unsigned char   AzaliaSdin2;               /**< AzaliaSdin2
 698                                         *   @par
 699                                         * SDIN0 is define at BIT4 & BIT5
 700                                         *    @li <b>00</b> - GPIO PIN
 701                                         *    @li <b>10</b> - As a Azalia SDIN pin
 702                                         */
 703   unsigned char   AzaliaSdin3;               /**< AzaliaSdin3
 704                                         *   @par
 705                                         * SDIN0 is define at BIT6 & BIT7
 706                                         *    @li <b>00</b> - GPIO PIN
 707                                         *    @li <b>10</b> - As a Azalia SDIN pin
 708                                         */
 709 } AZALIAPIN;
 710
 711 /** AMDSBCFG - Southbridge CIMx configuration structure (Main) */
 712 typedef struct _AMDSBCFG {
 713 /** StdHeader - Standard header for all AGESA/CIMx services. */
 714   AMD_CONFIG_PARAMS   StdHeader;
 715
 716 /** BuildParameters - The STATIC platform information for CIMx Module. 00-00-00 */
 717   BUILDPARAM BuildParameters;
 718                                       //offset 90 bytes (32-121)
 719   //MsgXchgBiosCimx                   //offset 8 bytes (122-129)
 720   // SATA Configuration
 721
 722   union /**< union - Reserved 00-01-00 */
 723   {  /**< SATAMODE - Sata Controller structure */
 724 /** SataModeReg - Reserved */
 725     unsigned char   SataModeReg;
 726 /** SataMode - Reserved */
 727     SATAST  SataMode;
 728   } SATAMODE;
 729 /** S3Resume - Flag of ACPI S3 Resume. 00-02 Internal USED */
 730   unsigned char   S3Resume;                   // 8
 731 /** RebootRequired - Flag of Reboot system is required. 00-03 Internal USED (retired) */
 732   unsigned char   RebootRequired;             // 9
 733 /** SbSpiSpeedSupport - Reserved 00-04 (retired)*/
 734   unsigned char   SbSpiSpeedSupport;   // 10
 735 /**< SpreadSpectrum 00-05-00
 736  *   @par
 737  *   Spread Spectrum function
 738  *    @li <b>0</b> - disable
 739  *    @li <b>1</b> - enable
 740  */
 741   unsigned char   SpreadSpectrum;             // 11
 742 /** NbSbGen2 - Reserved 00-06-00 */
 743   unsigned char   NbSbGen2;                   // 12 00-07
 744   unsigned char   GppGen2;                    // 13 00-08
 745   unsigned char   GppMemWrImprove;            // 14 00-09
 746   unsigned char   S4Resume;                   // 15 00-10 Internal
 747   unsigned char   FchVariant;                 //
 748 /**< SataClass - SATA Controller mode [2:0] 00-11
 749  *   @par
 750  *    @li <b>000</b> - Native IDE mode
 751  *    @li <b>001</b> - RAID mode
 752  *    @li <b>010</b> - AHCI mode
 753  *    @li <b>011</b> - Legacy IDE mode
 754  *    @li <b>100</b> - IDE->AHCI mode
 755  *    @li <b>101</b> - AHCI mode as 7804 ID (AMD driver)
 756  *    @li <b>110</b> - IDE->AHCI mode as 7804 ID (AMD driver)
 757  */
 758   unsigned char   SataClass;                 // 2:0
 759 /**< SataIdeMode - Sata IDE Controller mode 00-12
 760  *   @par
 761  *    @li <b>0</b> - Legacy IDE mode
 762  *    @li <b>1</b> - Native IDE mode
 763  */
 764   unsigned char   SataIdeMode;               // 3
 765   unsigned char   sdConfig;        /**< sdMode 00-13
 766                                    *   @par
 767                                    *    SD Configuration
 768                                    *    @li <b>00</b> - Disabled
 769                                    *    @li <b>00</b> - AMDA,  set 24,18,16,  default
 770                                    *    @li <b>01</b> - DMA clear 24, 16, set 18
 771                                    *    @li <b>10</b> - PIO clear 24,18,16
 772                                    *
 773                                    */
 774   unsigned char   sdSpeed;        /**< sdSpeed 00-14
 775                                    *   @par
 776                                    *    SD Configuration
 777                                    *    @li <b>0</b> - Low speed clear 17
 778                                    *    @li <b>1</b> - High speed, set 17, default
 779                                    *
 780                                    */
 781   unsigned char   sdBitwidth;        /**< sdBitwidth 00-15
 782                                    *   @par
 783                                    *    SD Configuration
 784                                    *    @li <b>0</b> - 32BIT clear 23
 785                                    *    @li <b>1</b> - 64BIT, set 23,default
 786                                    *
 787                                    */
 788 /**< SataDisUnusedIdePChannel - Disable Unused IDE Primary Channel 00-16
 789  *   @par
 790  *    @li <b>0</b> - Channel Enable
 791  *    @li <b>1</b> - Channel Disable
 792  */
 793   unsigned char   SataDisUnusedIdePChannel;
 794 /**< SataDisUnusedIdeSChannel - Disable Unused IDE Secondary Channel 00-17
 795  *   @par
 796  *    @li <b>0</b> - Channel Enable
 797  *    @li <b>1</b> - Channel Disable
 798  */
 799   unsigned char   SataDisUnusedIdeSChannel;
 800 /**< IdeDisUnusedIdePChannel - Disable Unused IDE Primary Channel 00-18
 801  *   @par
 802  *    @li <b>0</b> - Channel Enable
 803  *    @li <b>1</b> - Channel Disable
 804  */
 805   unsigned char   IdeDisUnusedIdePChannel;
 806 /**< IdeDisUnusedIdeSChannel - Disable Unused IDE IDE Secondary Channel 00-19
 807  *   @par
 808  *    @li <b>0</b> - Channel Enable
 809  *    @li <b>1</b> - Channel Disable
 810  */
 811   unsigned char   IdeDisUnusedIdeSChannel;
 812
 813 /**<  SataEspPort - SATA port is external accessible on a signal only connector (eSATA:)  00-20
 814  *   @par
 815  *    @li <b> BIT0 </b> - PORT0 set as ESP port
 816  *    @li <b> BIT1 </b> - PORT1 set as ESP port
 817  *    @li <b> BIT2 </b> - PORT2 set as ESP port
 818  *    @li <b> BIT3 </b> - PORT3 set as ESP port
 819  *    @li <b> BIT4 </b> - PORT4 set as ESP port
 820  *    @li <b> BIT5 </b> - PORT5 set as ESP port
 821  *    @li <b> BIT6 </b> - PORT6 set as ESP port
 822  *    @li <b> BIT7 </b> - PORT7 set as ESP port
 823  */
 824   union /**< union - Reserved */
 825   { /**< SATAPORT - SATA Port Structure */
 826   /** SataPortReg - Reserved */
 827     unsigned char    SataPortReg;
 828     SATAPORTST SataEspPort;           // 23:16
 829   } SATAESPPORT;
 830
 831   union /**< union - Reserved  00-21*/
 832   { /**< SATAPORT - SATA Port Structure */
 833   /** SataPortPowerReg - Reserved */
 834     unsigned char    SataPortPowerReg;
 835     SATAPORTST SataPortPower;         // 31:24
 836   } SATAPORTPOWER;
 837
 838   // SATA Debug Option                //offset 4 bytes (130-133)
 839
 840   union /**< union - Reserved  00-22*/
 841   {
 842 /**< SataPortMode - Force Each PORT to GEN1/GEN2 mode
 843  *   @par
 844  *    @li <b> 0 </b> Auto for each PORTs
 845  *    @li <b> BIT0 = 1</b> - PORT0 set to GEN1
 846  *    @li <b> BIT1 = 1</b> - PORT0 set to GEN2
 847  *    @li <b> BIT2 = 1</b> - PORT1 set to GEN1
 848  *    @li <b> BIT3 = 1</b> - PORT1 set to GEN2
 849  *    @li <b> BIT4 = 1</b> - PORT2 set to GEN1
 850  *    @li <b> BIT5 = 1</b> - PORT2 set to GEN2
 851  *    @li <b> BIT6 = 1</b> - PORT3 set to GEN1
 852  *    @li <b> BIT7 = 1</b> - PORT3 set to GEN2
 853  *    @li <b> BIT8 = 1</b> - PORT4 set to GEN1
 854  *    @li <b> BIT9 = 1</b> - PORT4 set to GEN2
 855  *    @li <b> BIT10 = 1</b> - PORT5 set to GEN1
 856  *    @li <b> BIT11 = 1</b> - PORT5 set to GEN2
 857  *    @li <b> BIT12 = 1</b> - PORT6 set to GEN1
 858  *    @li <b> BIT13 = 1</b> - PORT6 set to GEN2
 859  *    @li <b> BIT14 = 1</b> - PORT7 set to GEN1
 860  *    @li <b> BIT15 = 1</b> - PORT7 set to GEN2
 861  */
 862     unsigned short   SataPortMode;               //15:0
 863     SATAPORTMD SataPortMd;
 864   } SATAPORTMODE;
 865 /** SATAClkSelOpt - Reserved  00-23*/
 866   unsigned char   SATAClkSelOpt;              //19:16  *Removed from coding side
 867 /** SataAggrLinkPmCap - Reserved  00-24*/
 868   unsigned char   SataAggrLinkPmCap;          //20, 0:OFF   1:ON
 869 /** SataPortMultCap - Reserved  00-25*/
 870   unsigned char   SataPortMultCap;            //21, 0:OFF   1:ON
 871 /** SataClkAutoOff - Reserved  00-26*/
 872   unsigned char   SataClkAutoOff;             //22, AutoClockOff 0:Disabled, 1:Enabled
 873 /** SataPscCap - Reserved  00-27*/
 874   unsigned char   SataPscCap;                 //23, 1:Enable PSC capability, 0:Disable PSC capability
 875 /** BIOSOSHandoff - Reserved  00-28*/
 876   unsigned char   BIOSOSHandoff;              //24
 877 /** SataFisBasedSwitching - Reserved  00-29*/
 878   unsigned char   SataFisBasedSwitching;      //25
 879 /** SataCccSupport - Reserved  00-30*/
 880   unsigned char   SataCccSupport;             //26
 881 /** SataSscCap - Reserved  00-31*/
 882   unsigned char   SataSscCap;                 //27, 1:Enable SSC capability, 0:Disable SSC capability
 883 /** SataMsiCapability - Reserved  00-32*/
 884   unsigned char   SataMsiCapability;          //28  0:Hidden 1:Visible
 885 /** SataForceRaid - Reserved  00-33*/
 886   unsigned char   SataForceRaid;              //29  0:No function 1:Force RAID
 887 /** SataInternal100Spread - Reserved  00-34*/
 888   unsigned char   SataInternal100Spread;      //30
 889
 890   // SATA Debug Option (2)          //offset 4 bytes (134-137)
 891
 892 /** SataTargetSupport8Device - Reserved  00-35*/
 893   unsigned char   SataTargetSupport8Device;   // 0
 894 /** SataDisableGenericMode - Reserved  00-36*/
 895   unsigned char   SataDisableGenericMode;     // 1
 896 /** SataAhciEnclosureManagement - Reserved  00-37 */
 897   unsigned char   SataAhciEnclosureManagement; // 2
 898 /** SataSgpio0 - Reserved  00-38*/
 899   unsigned char   SataSgpio0;                 // 3
 900 /** SataSgpio1 - Reserved  00-39*/
 901   unsigned char   SataSgpio1;                 // 4
 902 /** SataPhyPllShutDown - Reserved  00-40*/
 903   unsigned char   SataPhyPllShutDown;         // 5
 904 /** SataHotRemoveEnh - Reserved */
 905   unsigned char   SataHotRemoveEnh;           // 6
 906 /**< SataHotRemovelEnh for each ports - Hot-removal enhancementEnable for portN
 907  *   @par
 908  *    @li <b> BIT0 </b> - PORT0 set as HotRemovelEnh port
 909  *    @li <b> BIT1 </b> - PORT1 set as HotRemovelEnh port
 910  *    @li <b> BIT2 </b> - PORT2 set as HotRemovelEnh port
 911  *    @li <b> BIT3 </b> - PORT3 set as HotRemovelEnh port
 912  *    @li <b> BIT4 </b> - PORT4 set as HotRemovelEnh port
 913  *    @li <b> BIT5 </b> - PORT5 set as HotRemovelEnh port
 914  *    @li <b> BIT6 </b> - PORT6 set as HotRemovelEnh port
 915  *    @li <b> BIT7 </b> - PORT7 set as HotRemovelEnh port
 916  */
 917   union /**< union - Reserved  00-41*/
 918   { /**< SATAPORT - SATA Port Structure */
 919   /** SataHotRemovelEnh - Reserved */    // 31:24
 920     unsigned char    SataHotRemovelEnh:8;
 921     SATAPORTST SataHotRemoveEnhPort;
 922   } SATAHOTREMOVALENH;
 923
 924 //
 925 // USB Configuration                //offset 4 bytes (134-137)
 926 //
 927
 928 /** USBDeviceConfig - USB Controller Configuration
 929  *
 930  * Usb Ohci1 Contoller is define at BIT0
 931  *   - 0:disable 1:enable
 932  *                             (Bus 0 Dev 18 Func0) *
 933  * Usb Ehci1 Contoller is define at BIT1
 934  *   - 0:disable 1:enable
 935  *                             (Bus 0 Dev 18 Func2) *
 936  * Usb Ohci2 Contoller is define at BIT2
 937  *   - 0:disable 1:enable
 938  *                             (Bus 0 Dev 19 Func0) *
 939  * Usb Ehci2 Contoller is define at BIT3
 940  *   - 0:disable 1:enable
 941  *                             (Bus 0 Dev 19 Func2) *
 942  * Usb Ohci3 Contoller is define at BIT4
 943  *   - 0:disable 1:enable
 944  *                             (Bus 0 Dev 22 Func0) *
 945  * Usb Ehci3 Contoller is define at BIT5
 946  *   - 0:disable 1:enable
 947  *                             (Bus 0 Dev 22 Func2) *
 948  * Usb Ohci4 Contoller is define at BIT6
 949  *   - 0:disable 1:enable
 950  *                             (Bus 0 Dev 20 Func5) *
 951  */
 952
 953   union /**< union - Reserved */
 954   {  /**< USBMODE - USB Controller structure */
 955 /** SataModeReg - Reserved  00-42*/
 956     unsigned char   UsbModeReg;
 957 /** SataMode - Reserved */
 958     USBST  UsbMode;
 959   } USBMODE;
 960
 961 /**< GecConfig  00-43
 962  *   @par
 963  *   InChip Gbit NIC
 964  *    @li <b>0</b> - disable
 965  *    @li <b>1</b> - enable
 966  */
 967   unsigned char   GecConfig;                 //8
 968 /**< IrConfig  00-44
 969  *   @par
 970  *   Ir Controller
 971  *    @li <b>00 </b> - disable
 972  *    @li <b>01 </b> - Rx and Tx0
 973  *    @li <b>10 </b> - Rx and Tx1
 974  *    @li <b>11 </b> - Rx and both Tx0,Tx1
 975  */
 976   unsigned char   IrConfig;                  //9:10
 977   unsigned char   XhciSwitch;                 //11  00-45
 978
 979   //Azalia Configuration
 980
 981 /**< AzaliaController - Azalia Controller Configuration  00-46
 982  *   @par
 983  *   Azalia Controller [0-1]
 984  *    @li <b>0</b> - Auto   : Detect Azalia controller automatically.
 985  *    @li <b>1</b> - Diable : Disable Azalia controller.
 986  *    @li <b>2</b> - Enable : Enable Azalia controller.
 987  */
 988   unsigned char   AzaliaController;          //17:16
 989 /**< AzaliaPinCfg - Azalia Controller SDIN pin Configuration  00-47
 990  *   @par
 991  *    @li <b>0</b> - disable
 992  *    @li <b>1</b> - enable
 993  */
 994   unsigned char   AzaliaPinCfg;              //18
 995 /**< AzaliaFrontPanel - Azalia Controller Front Panel Configuration  00-48
 996  *   @par
 997  *   Support Front Panel configuration
 998  *    @li <b>0</b> - Auto
 999  *    @li <b>1</b> - disable
1000  *    @li <b>2</b> - enable
1001  */
1002   unsigned char   AzaliaFrontPanel;          //20:19
1003 /**< FrontPanelDetected - Force Azalia Controller Front Panel Configuration  00-49
1004  *   @par
1005  *   Force Front Panel configuration
1006  *    @li <b>0</b> - Not Detected
1007  *    @li <b>1</b> - Detected
1008  */
1009   unsigned char   FrontPanelDetected;        //21
1010 /**< AzaliaSnoop - Azalia Controller Snoop feature Configuration  00-59
1011  *   @par
1012  *   Azalia Controller Snoop feature Configuration
1013  *    @li <b>0</b> - disable
1014  *    @li <b>1</b> - enable
1015  */
1016   unsigned char   AzaliaSnoop;               //22
1017 /** AzaliaDummy - Reserved */
1018   unsigned char   AzaliaDummy;               //23
1019
1020   union
1021   {
1022 /**< AzaliaSdinPin - Azalia Controller SDIN pin Configuration  00-51
1023  *
1024  * SDIN0 is define at BIT0 & BIT1
1025  *   - 00: GPIO PIN
1026  *   - 01: Reserved
1027  *   - 10: As a Azalia SDIN pin
1028  *
1029  * SDIN1 is define at BIT2 & BIT3
1030  *      * Config same as SDIN0
1031  * SDIN2 is define at BIT4 & BIT5
1032  *      * Config same as SDIN0
1033  * SDIN3 is define at BIT6 & BIT7
1034  *      * Config same as SDIN0
1035  */
1036     unsigned char   AzaliaSdinPin;
1037     AZALIAPIN  AzaliaConfig;
1038   } AZALIACONFIG;
1039
1040 /** AZOEMTBL - Azalia Controller OEM Codec Table Pointer  00-52
1041  *
1042  */
1043   union
1044   {
1045     PLACEHOLDER  PlaceHolder;
1046     CODECTBLLIST*  pAzaliaOemCodecTablePtr;  //offset 4 bytes (138-141)
1047   } AZOEMTBL;
1048
1049 /** AZOEMFPTBL - Azalia Controller Front Panel OEM Table Pointer  00-53
1050  *
1051  */
1052   union
1053   {
1054     PLACEHOLDER  PlaceHolder;
1055     void*   pAzaliaOemFpCodecTablePtr;       //offset 4 bytes (142-145)
1056   } AZOEMFPTBL;
1057
1058   //Miscellaneous Configuration      //offset 4 bytes (146-149)
1059 /** AnyHT200MhzLink - Reserved  00-54 */
1060   unsigned char   AnyHT200MhzLink;             //0
1061 /**< HpetTimer - South Bridge Hpet Timer Configuration  00-56
1062  *   @par
1063  *    @li <b>0</b> - disable
1064  *    @li <b>1</b> - enable
1065  */
1066   unsigned char   HpetTimer;                 //1
1067 /**< PciClks - PCI Slot Clock Control  00-57
1068  *   @par
1069  * PCI SLOT 0 define at BIT0
1070  *   - 00: disable
1071  *   - 01: enable
1072  *
1073  * PCI SLOT 1 define at BIT1
1074  *      * Config same as PCI SLOT0
1075  * PCI SLOT 2 define at BIT2
1076  *      * Config same as PCI SLOT0
1077  * PCI SLOT 3 define at BIT3
1078  *      * Config same as PCI SLOT0
1079  * PCI SLOT 4 define at BIT4
1080  *      * Config same as PCI SLOT0
1081  */
1082   unsigned char   PciClks;                   //2:6
1083 /** MiscReserved1 - Reserved */
1084   unsigned char   MiscReserved1;             //9:7, Reserved
1085 /** MobilePowerSavings - Debug function Reserved  00-58*/
1086   unsigned char   MobilePowerSavings;        //11, 0:Disable, 1:Enable Power saving features especially for Mobile platform
1087 /** ExternalRTCClock - Debug function Reserved  00-59*/
1088   unsigned char   ExternalRTCClock;          //12, 0:Don't Shut Off, 1:Shut Off, external RTC clock
1089 /** NativePcieSupport - Debug function Reserved  00-60*/
1090   unsigned char   NativePcieSupport;         //13, 0:Disabled, 1:Enable
1091 /** FlashPinConfig - Debug function Reserved  00-61*/
1092   unsigned char   FlashPinConfig;            //14, 0:desktop mode 1:mobile mode
1093 /** UsbPhyPowerDown - Debug function Reserved  00-62*/
1094   unsigned char   UsbPhyPowerDown;           //15
1095 /** PcibClkStopOverride - Debug function Reserved  00-63*/
1096   unsigned short   PcibClkStopOverride;      //25:16
1097 /**< HpetMsiDis - South Bridge HPET MSI Configuration  00-64 (Retired)
1098  *   @par
1099  *    @li <b>1</b> - disable
1100  *    @li <b>0</b> - enable
1101  */
1102   unsigned char   HpetMsiDis;                //26
1103 /**< ResetCpuOnSyncFlood - Rest CPU on Sync Flood  00-65 (Retired)
1104  *   @par
1105  *    @li <b>0</b> - disable
1106  *    @li <b>1</b> - enable
1107  */
1108   unsigned char   ResetCpuOnSyncFlood;       //27
1109
1110   //DebugOptions                     //offset 4 bytes (150-153)
1111 /** PcibAutoClkCtr - Debug function Reserved  00-66*/
1112   unsigned char   PcibAutoClkCtr;
1113
1114 /**< OEMPROGTBL - ACPI MMIO register setting table OEM override  00-67
1115  *   @par
1116  *   OEM table for customer override ACPI MMIO register in their code.
1117  */
1118   union
1119   {
1120     PLACEHOLDER OemProgrammingTablePtr;  //offset 4 bytes (154-157)
1121     void   *OemProgrammingTablePtr_Ptr;
1122   } OEMPROGTBL;
1123
1124   //Gpp Configuration                   //offset 24 bytes total (158-181)  00-68
1125   union {
1126     unsigned int           PORTCFG32;
1127     SBGPPPORTCONFIG  PortCfg;
1128   } PORTCONFIG[4];          //offset 16 bytes
1129
1130   unsigned char           GppLinkConfig;       /**< GPP_LINK_CONFIG = PCIE_GPP_Enable[3:0]  00-69
1131                                          * @li  <b>0000</b> - Port ABCD -> 4:0:0:0
1132                                          * @li  <b>0001</b> - N/A
1133                                          * @li  <b>0010</b> - Port ABCD -> 2:2:0:0
1134                                          * @li  <b>0011</b> - Port ABCD -> 2:1:1:0
1135                                          * @li  <b>0100</b> - Port ABCD -> 1:1:1:1
1136                                          */
1137   unsigned char   GppFoundGfxDev;            ///< 3:0 If port A-D (mapped to bit [3:0]) has GFX EP detected  00-70
1138   unsigned char   GppGen2Strap;              ///< 4   LC_GEN2_EN_STRAP  00-71 (internal used)
1139   unsigned char   GppFunctionEnable;         ///< 5  00-72
1140   unsigned char   GppUnhidePorts;            ///< 6  00-73
1141   unsigned char   AlinkPhyPllPowerDown;      ///< 7  00-74
1142   unsigned char   GppPortAspm;               /**< 9:8 ASPM state for all GPP ports  00-75
1143                                          * @li   <b>01</b> - Disabled
1144                                          * @li   <b>01</b> - L0s
1145                                          * @li   <b>10</b> - L1
1146                                          * @li   <b>11</b> - L0s + L1
1147                                          */
1148   unsigned char   GppLaneReversal;           ///< 10  00-76
1149   unsigned char   GppPhyPllPowerDown;        ///< 11  00-77
1150   unsigned char   GppDynamicPowerSaving;     ///< 12  00-78
1151   unsigned char   PcieAER;                   ///< 13 Advanced Error Report: 0/1-disable/enable  00-79
1152 /** UmiDynamicSpeedChange - Reserved */
1153   unsigned char   PcieRAS;                   // 14  00-80
1154   unsigned char   GppHardwareDowngrade;      // 20:18: 0:Disable, 1-4: portA-D  00-83
1155   unsigned char   GppToggleReset;            // 21  00-84
1156   unsigned char   sdbEnable;                 // 22  00-85
1157
1158   //TempMMIO                            //offset 4 bytes (190-193)  00-86
1159   unsigned int   TempMMIO;
1160
1161   // DebugOption2
1162   unsigned char   GecPhyStatus;              //  00-86
1163   unsigned char   GecDebugOptionDummy;       //  00-87
1164   unsigned char   SBGecPwr;                  //  00-88
1165   unsigned char   SBGecDebugBus;             //  00-89
1166   unsigned char   SbPcieOrderRule;           //  00-90
1167   unsigned char   AcDcMsg;                   //  00-91
1168   unsigned char   TimerTickTrack;            //  00-92
1169   unsigned char   ClockInterruptTag;         //  00-93
1170   unsigned char   OhciTrafficHanding;        //  00-94
1171   unsigned char   EhciTrafficHanding;        //  00-95
1172   unsigned char   FusionMsgCMultiCore;       //  00-95A
1173   unsigned char   FusionMsgCStage;           //  00-96
1174   unsigned char   ALinkClkGateOff;           //  00-97
1175   unsigned char   BLinkClkGateOff;           //  00-98
1176   unsigned char   Sdb;                       //  00-99
1177   unsigned char   SlowSpeedABlinkClock;      //  01-00
1178   unsigned char   MtC1eEnable;               //  01-00
1179   union
1180   {
1181     PLACEHOLDER DynamicGecRomAddressPtr;  //offset 4 bytes (194-201)  01-01
1182     void   *DynamicGecRomAddress_Ptr;
1183   } DYNAMICGECROM;
1184 //  unsigned int   UmiCommon;                   //offset 4 bytes (202-205)
1185 /** AbGppClockGating - Reserved */
1186   unsigned char   AbClockGating;   // 01-02
1187   unsigned char   GppClockGating;   // 01-03
1188
1189 //  unsigned int   UmiDebug;
1190
1191 /** L1TimerOverwrite - Reserved */
1192   unsigned char   L1TimerOverwrite;     // 01-04
1193 /** UmiLinkWidth - Reserved */
1194   unsigned char   UmiLinkWidth; // 4:3  01-05
1195 /** UmiDynamicSpeedChange - Reserved */
1196   unsigned char   UmiDynamicSpeedChange;                 // 01-06
1197 /** PcieRefClockOverclocking - Reserved */
1198   unsigned char   PcieRefClockOverclocking;                 // 9:6 01-07
1199 /** PcieRefClockOverclocking - Reserved */
1200   unsigned char   SbAlinkGppTxDriverStrength;                 // 12:10 01-08
1201   unsigned char   PwrFailShadow;               /**< PwrFailShadow = PM_Reg: 5Bh [3:0] 01-09
1202                                          * @li  <b>00</b> - Always off
1203                                          * @li  <b>01</b> - Always on
1204                                          * @li  <b>10</b> - Always off
1205                                          * @li  <b>11</b> - Use previous
1206                                          */
1207   unsigned char   StressResetMode;               /**< StressResetMode 01-10
1208                                          * @li  <b>00</b> - Disabed
1209                                          * @li  <b>01</b> - Io Write 0x64 with 0xfe
1210                                          * @li  <b>10</b> - Io Write 0xcf9 with 0x06
1211                                          * @li  <b>11</b> - Io Write 0xcf9 with 0x0e
1212                                          */
1213   EC_struct Pecstruct;  // 01-11 (Internal USED)
1214   HWM_struct hwm;       // 01-12
1215   IMC_struct imc;       // 01-13
1216   unsigned char    Cg2Pll;      // 01-14
1217   unsigned char    ClockRun;      // 01-15
1218   unsigned char   Debug_Reg00;                 // 01-16
1219   unsigned char   Debug_Reg01;                 // 01-17
1220   unsigned char   Debug_Reg02;                 // 01-18
1221   unsigned char   Debug_Reg03;                 // 01-19
1222   unsigned char   Debug_Reg04;                 // 01-20
1223   unsigned char   Debug_Reg05;                 // 01-21
1224   unsigned char   EhciDataCacheDis;            // 01-22
1225   unsigned char   EfuseByte [0x20];
1226   unsigned char   EfuseRemainder ;
1227   unsigned char   EfuseSum ;
1228   unsigned char   L1ImmediateAck;
1229 } AMDSBCFG;
1230
1231 /** SMMSERVICESTRUC- Southbridge SMI service structure */
1232 typedef  struct   _SMMSERVICESTRUC {
1233 /** enableRegNum - Reserved */
1234   unsigned char enableRegNum;
1235 /** enableBit - Reserved */
1236   unsigned char enableBit;
1237 /** statusRegNum - Reserved */
1238   unsigned char statusRegNum;
1239 /** statusBit - Reserved */
1240   unsigned char statusBit;
1241 /** *debugMessage- Reserved */
1242   signed char *debugMessage;
1243 /** serviceRoutine - Reserved */
1244   SMM_SERVICE_ROUTINE  serviceRoutine;
1245 } SMMSERVICESTRUC;
1246
1247 #ifndef _NB_REG8MASK_
1248
1249 /**
1250  *  - Byte Register R/W structure
1251  *
1252  */
1253   typedef struct _Reg8Mask {
1254 /** bRegIndex - Reserved */
1255     unsigned char bRegIndex;
1256 /** bANDMask - Reserved */
1257     unsigned char bANDMask;
1258 /** bORMask - Reserved */
1259     unsigned char bORMask;
1260   } REG8MASK;
1261 #endif
1262
1263 /**
1264  *  - SATA Phy setting structure
1265  *
1266  */
1267 typedef struct _SATAPHYSETTING {
1268 /** wPhyCoreControl - Reserved */
1269   unsigned short wPhyCoreControl;
1270 /** dwPhyFineTune - Reserved */
1271   unsigned int dwPhyFineTune;
1272 } SATAPHYSETTING;
1273
1274 /**
1275  * _ABTblEntry - AB link register table R/W structure
1276  *
1277  */
1278 typedef struct _ABTblEntry {
1279   /** regType  : AB Register Type (ABCFG, AXCFG and so on) */
1280   unsigned char    regType;
1281   /** regIndex : AB Register Index */
1282   unsigned int   regIndex;
1283   /** regMask  : AB Register Mask */
1284   unsigned int   regMask;
1285   /** regData  : AB Register Data */
1286   unsigned int   regData;
1287 } ABTBLENTRY;
1288
1289 /**
1290  * _AcpiRegWrite - ACPI MMIO register R/W structure
1291  *
1292  */
1293 typedef struct _AcpiRegWrite {
1294   /** MmioBase     : Index of Southbridge block (For instance GPIO_BASE:0x01 SMI_BASE:0x02) */
1295   unsigned char MmioBase;
1296   /** MmioReg      : Register index */
1297   unsigned char MmioReg;
1298   /** DataANDMask  : AND Register Data */
1299   unsigned char DataANDMask;
1300   /** DataOrMask   : Or Register Data */
1301   unsigned char DataOrMask;
1302 } AcpiRegWrite;
1303
1304 /**
1305  * PCI_ADDRESS - PCI access structure
1306  *
1307  */
1308 #define PCI_ADDRESS(bus, dev, func, reg) \
1309 (unsigned int) ( (((unsigned int)bus) << 24) + (((unsigned int)dev) << 19) + (((unsigned int)func) << 16) + ((unsigned int)reg) )
1310
1311 /**
1312  * CIM_STATUS - CIMx module function return code
1313  */
1314 typedef unsigned int    CIM_STATUS;
1315 /**
1316  * CIM_SUCCESS - Executed without error
1317  */
1318 #define CIM_SUCCESS 0x00000000
1319 /**
1320  * CIM_ERROR - call error
1321  */
1322 #define CIM_ERROR 0x80000000
1323 /**
1324  * CIM_UNSUPPORTED - function does not support
1325  */
1326 #define CIM_UNSUPPORTED 0x80000001
1327
1328 #ifndef  LEGACY_BIOS_SUPPORT
1329   #pragma pack (pop)
1330 #endif
1331
1332 /**
1333  * DISABLED - Define disable in module
1334  */
1335 #define DISABLED   0
1336 /**
1337  * ENABLED - Define enable in module
1338  */
1339 #define ENABLED    1
1340
1341 /// PCIE Reset Block
1342 typedef enum {
1343   NbBlock,                        ///< Reset for NB PCIE
1344   SbBlock                         ///< Reset for FCH GPP
1345 } RESET_BLOCK;
1346
1347 /// PCIE Reset Operation
1348 typedef enum {
1349   DeassertReset,                  ///< Deassert reset
1350   AssertReset                     ///< Assert reset
1351 } RESET_OP;
1352
1353 /**
1354  * SB_GPIO_INIT_ENTRY
1355  *
1356  */
1357 typedef struct _SB_GPIO_INIT_ENTRY {
1358   unsigned char GpioPin;                  ///< Gpio Pin
1359   unsigned char GpioMux;                  ///< Gpio Mux
1360   unsigned char GpioOutEnB;               ///< Gpio Out EnB
1361   unsigned char GpioOut;                  ///< Gpio Out
1362 } SB_GPIO_INIT_ENTRY;
1363
1364 /**
1365  * SB_GPIO_CONTROL_ENTRY
1366  *
1367  */
1368 typedef struct _SB_GPIO_CONTROL_ENTRY {
1369   unsigned char GpioPin;                  ///< Gpio Pin
1370   unsigned char GpioControl;              ///< Gpio Control
1371 } SB_GPIO_CONTROL_ENTRY;
1372
1373 /**
1374  * SB_SPREAD_SPECTRUM_ENTRY
1375  *
1376  */
1377 typedef struct _SB_SPREAD_SPECTRUM_ENTRY {
1378   unsigned int P_40_25;                  ///< P_10_25_24
1379   unsigned int P_18_15_5;              ///< P_10_25_24
1380   unsigned int P_18_19_16;              ///< P_10_25_24
1381   unsigned int P_10_23_8;              ///< P_10_25_24
1382   unsigned int P_10_7_0;              ///< P_10_25_24
1383   unsigned int P_1C_5_0;              ///< P_10_25_24
1384   unsigned int P_08_31_28;              ///< P_10_25_24
1385   unsigned int P_08_7;              ///< P_10_25_24
1386   unsigned int P_08_8;              ///< P_10_25_24
1387   unsigned int P_10_25_24;              ///< P_10_25_24
1388 } SB_SPREAD_SPECTRUM_ENTRY;
1389 #endif // _AMD_SBTYPE_H_