2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
8 CLK_FREQ : integer := 33000000;
9 BAUDRATE : integer := 115200
12 sys_clk : in std_logic;
13 sys_res_n : in std_logic;
15 rx_data : out std_logic_vector(7 downto 0);
16 rx_new : out std_logic
20 architecture beh of uart_rx is
21 constant BAUD : integer := CLK_FREQ/BAUDRATE;
23 type STATE_UART_RX is (IDLE, STARTBIT, DBITS, STOPBIT);
24 signal state_int, state_next : STATE_UART_RX;
26 signal rx_data_next, rx_data_int : std_logic_vector(7 downto 0);
27 signal rx_new_next, rx_new_int : std_logic;
28 signal startbitdetection : std_logic_vector(1 downto 0);
29 signal bitcnt_int, bitcnt_next : integer range 0 to 7;
30 signal baudcnt_int, baudcnt_next : integer range 0 to BAUD;
33 rx_data <= rx_data_int;
35 process(sys_clk, sys_res_n)
37 if (sys_res_n = '0') then
39 rx_data_int <= (others => '0');
43 startbitdetection <= b"11";
44 elsif rising_edge(sys_clk) then
45 state_int <= state_next;
46 rx_data_int <= rx_data_next;
47 rx_new_int <= rx_new_next;
48 bitcnt_int <= bitcnt_next;
49 baudcnt_int <= baudcnt_next;
50 startbitdetection(0) <= rxd;
51 startbitdetection(1) <= startbitdetection(0);
55 process(state_int, rx_data_int, rxd, bitcnt_int, baudcnt_int,
58 state_next <= state_int;
59 rx_data_next <= rx_data_int;
61 bitcnt_next <= bitcnt_int;
62 baudcnt_next <= baudcnt_int;
66 -- bei fallender flanke koennte starbit folgen
67 if startbitdetection = b"10" then
68 state_next <= STARTBIT;
72 rx_data_next <= (others => '0');
74 -- halbe BAUDTIME warten, um immer in der mitte abzutasten
75 -- vgl. http://upload.wikimedia.org/wikipedia/de/d/de/RS-232_timing.png
76 if baudcnt_int < BAUD/2 then
77 baudcnt_next <= baudcnt_int + 1;
81 -- starbit (= '0')? dann kommen daten
86 -- sonst war das nix...
91 if baudcnt_int < BAUD then
92 baudcnt_next <= baudcnt_int + 1;
96 rx_data_next <= rxd & rx_data_int(7 downto 1);
98 if bitcnt_int = 7 then
99 state_next <= STOPBIT;
101 bitcnt_next <= bitcnt_int + 1;
105 if baudcnt_int < BAUD then
106 baudcnt_next <= baudcnt_int + 1;
115 end architecture beh;