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3 -- Filename: textmode_vga_v_sm.vhd
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6 -- Short Description:
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7 -- ==================
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8 -- Entity declaration of the vertical VGA timing finite state machine
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10 -------------------------------------------------------------------------
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13 use ieee.std_logic_1164.all;
14 use work.math_pkg.all;
15 use work.textmode_vga_pkg.all;
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16 use work.font_pkg.all;
18 entity textmode_vga_v_sm is
21 sys_clk, sys_res_n : in std_logic;
23 is_data_line : out std_logic;
24 char_line_cnt : out std_logic_vector(log2c(LINE_COUNT) - 1 downto 0);
25 char_height_pixel : out std_logic_vector(log2c(CHAR_HEIGHT) - 1 downto 0);
26 is_eol : in std_logic;
28 vsync_n : out std_logic
30 end entity textmode_vga_v_sm;