2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * Generic driver for pretty much all known Standard Microsystems Corporation
23 * (SMSC) Super I/O chips.
25 * Datasheets are available from: http://www.smsc.com/main/datasheet.html
27 * Most of the SMSC Super I/O chips seem to be similar enough (for our
28 * purposes) so that we can handle them with a unified driver.
30 * So far only the ASUS A8000 has been tested on real hardware!
32 * The floppy disk controller, the parallel port, the serial ports, and the
33 * keyboard controller should work with all the chips. For the more advanced
34 * stuff (e.g. HWM, ACPI, SMBus) more work is probably required.
38 #include <device/device.h>
39 #include <device/pnp.h>
40 #include <console/console.h>
42 #include <pc80/keyboard.h>
46 /* The following Super I/O chips are currently supported by this driver: */
47 #define LPC47M172 0x14
48 #define FDC37B80X 0x42 /* Same ID: FDC37M70X (a.k.a. FDC37M707) */
49 #define FDC37B78X 0x44
50 #define FDC37B72X 0x4c
51 #define FDC37M81X 0x4d
52 #define FDC37M60X 0x47
53 #define LPC47B27X 0x51 /* a.k.a. LPC47B272 */
54 #define LPC47M10X 0x59 /* Same ID: LPC47M112, LPC47M13X */
55 #define LPC47M15X 0x60 /* Same ID: LPC47M192 */
56 #define LPC47S45X 0x62
57 #define LPC47B397 0x6f
58 #define A8000 0x77 /* ASUS A8000, a rebranded DME1737(?) */
61 #define SCH5307 0x81 /* Rebranded LPC47B397(?) */
63 /* Register defines */
64 #define DEVICE_ID_REG 0x20 /* Device ID register */
65 #define DEVICE_REV_REG 0x21 /* Device revision register */
66 #define DEVICE_TEST7_REG 0x29 /* Device test 7 register */
68 /* Static variables for the Super I/O device ID and revision. */
69 static int first_time = 1;
70 static uint8_t superio_id = 0;
71 static uint8_t superio_rev = 0;
74 * A list of all possible logical devices which may be supported by at least
75 * one of the Super I/O chips. These values are used as index into the
76 * logical_device_table[i].devs array(s).
78 * If you change this enum, you must also adapt the logical_device_table[]
79 * array and MAX_LOGICAL_DEVICES!
82 LD_FDC, /* Floppy disk controller */
83 LD_PP, /* Parallel port */
84 LD_SP1, /* Serial port 1 (COM1) */
85 LD_SP2, /* Serial port 2 (COM2) */
86 LD_RTC, /* Real-time clock */
87 LD_KBC, /* Keyboard controller */
88 LD_AUX, /* Auxiliary I/O */
90 LD_HWM, /* Hardware monitor */
91 LD_GAME, /* Game port */
92 LD_PME, /* Power management events */
93 LD_MPU401, /* MPU-401 MIDI UART */
94 LD_RT, /* Runtime registers / security key registers */
99 /* Note: This value must match the number of items in the enum above! */
100 #define MAX_LOGICAL_DEVICES 15
103 * A table describing the logical devices which are present on the
104 * supported Super I/O chips.
106 * The first entry (superio_id) is the device ID of the Super I/O chip
107 * as stored in the (read-only) DEVICE_ID_REG register.
109 * The second entry (devs) is the list of logical device IDs which are
110 * present on that particular Super I/O chip. A value of -1 means the
111 * device is not present on that chip.
113 * Note: Do _not_ list chips with different name but same device ID twice!
114 * The result would be that the init code would be executed twice!
116 static const struct logical_devices {
118 int devs[MAX_LOGICAL_DEVICES];
119 } logical_device_table[] = {
120 // Chip FDC PP SP1 SP2 RTC KBC AUX XBUS HWM GAME PME MPU RT ACPI SMB
121 {LPC47M172,{0, 3, 4, 2, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}},
122 {FDC37B80X,{0, 3, 4, 5, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1}},
123 {FDC37B78X,{0, 3, 4, 5, 6, 7, 8, -1, -1, -1, -1, -1, -1, 10, -1}},
124 {FDC37B72X,{0, 3, 4, 5, -1, 7, 8, -1, -1, -1, -1, -1, -1, 10, -1}},
125 {FDC37M81X,{0, 3, 4, 5, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1}},
126 {FDC37M60X,{0, 3, 4, 5, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1}},
127 {LPC47B27X,{0, 3, 4, 5, -1, 7, -1, -1, -1, 9, -1, 11, 10, -1, -1}},
128 {LPC47M10X,{0, 3, 4, 5, -1, 7, -1, -1, -1, 9, 10, 11, -1, -1, -1}},
129 {LPC47M15X,{0, 3, 4, 5, -1, 7, -1, -1, -1, 9, 10, 11, -1, -1, -1}},
130 {LPC47S45X,{0, 3, 4, 5, 6, 7, -1, 8, -1, -1, -1, -1, 10, -1, 11}},
131 {LPC47B397,{0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10, -1, -1}},
132 {A8000, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}},
133 {DME1737, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}},
134 {SCH3112, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}},
135 {SCH5307, {0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10, -1, -1}},
139 * Enter the configuration state by writing 0x55 to the config port.
141 * The Super I/O configuration registers can only be modified when the chip
142 * is in the configuration state. Thus, to program the registers you have
143 * to a) enter config mode, b) program the registers, c) exit config mode.
145 * @param dev The device to use.
147 static inline void smsc_pnp_enter_conf_state(device_t dev)
149 outb(0x55, dev->path.pnp.port);
153 * Exit the configuration state by writing 0xaa to the config port.
155 * This puts the chip into the 'run' state again.
157 * @param dev The device to use.
159 static inline void smsc_pnp_exit_conf_state(device_t dev)
161 outb(0xaa, dev->path.pnp.port);
164 /** Wrapper for pnp_set_resources(). */
165 static void smsc_pnp_set_resources(device_t dev)
167 smsc_pnp_enter_conf_state(dev);
168 pnp_set_resources(dev);
169 smsc_pnp_exit_conf_state(dev);
172 /** Wrapper for pnp_enable_resources(). */
173 static void smsc_pnp_enable_resources(device_t dev)
175 smsc_pnp_enter_conf_state(dev);
176 pnp_enable_resources(dev);
177 smsc_pnp_exit_conf_state(dev);
181 * If so configured, enable the specified device, otherwise
182 * explicitly disable it.
184 * @param dev The device to use.
186 static void smsc_pnp_enable(device_t dev)
188 smsc_pnp_enter_conf_state(dev);
189 pnp_set_logical_device(dev);
190 (dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0);
191 smsc_pnp_exit_conf_state(dev);
195 * Initialize those logical devices which need a special init.
197 * @param dev The device to use.
199 static void smsc_init(device_t dev)
201 struct superio_smsc_smscsuperio_config *conf = dev->chip_info;
202 struct resource *res0, *res1;
205 /* Do not initialize disabled devices. */
209 /* Find the correct Super I/O. */
210 for (i = 0; i < ARRAY_SIZE(logical_device_table); i++)
211 if (logical_device_table[i].superio_id == superio_id)
214 /* If no Super I/O was found, return. */
215 if (i == ARRAY_SIZE(logical_device_table))
218 /* A Super I/O was found, so initialize the respective device. */
219 ld = dev->path.pnp.device;
220 if (ld == logical_device_table[i].devs[LD_SP1]) {
221 res0 = find_resource(dev, PNP_IDX_IO0);
222 init_uart8250(res0->base, &conf->com1);
223 } else if (ld == logical_device_table[i].devs[LD_SP2]) {
224 res0 = find_resource(dev, PNP_IDX_IO0);
225 init_uart8250(res0->base, &conf->com2);
226 } else if (ld == logical_device_table[i].devs[LD_KBC]) {
227 res0 = find_resource(dev, PNP_IDX_IO0);
228 res1 = find_resource(dev, PNP_IDX_IO1);
229 init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
233 /** Standard device operations. */
234 static struct device_operations ops = {
235 .read_resources = pnp_read_resources,
236 .set_resources = smsc_pnp_set_resources,
237 .enable_resources = smsc_pnp_enable_resources,
238 .enable = smsc_pnp_enable,
245 * This table should contain all possible entries for any of the supported
246 * Super I/O chips, even if some of them don't have the respective logical
247 * devices. That will be handled correctly by our code.
249 * The LD_FOO entries are device markers which tell you the type of the logical
250 * device (e.g. whether it's a floppy disk controller or a serial port etc.).
252 * Before using pnp_dev_info[] in pnp_enable_devices() these markers have
253 * to be replaced with the real logical device IDs of the respective
254 * Super I/O chip. This is done in enable_dev().
256 * TODO: FDC, PP, SP1, SP2, and KBC should work, the rest probably not (yet).
258 static struct pnp_info pnp_dev_info[] = {
259 { &ops, LD_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
260 { &ops, LD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
261 { &ops, LD_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
262 { &ops, LD_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
264 { &ops, LD_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 },
268 { &ops, LD_HWM, PNP_IO0, { 0x7f0, 0 }, },
271 { &ops, LD_MPU401, },
272 { &ops, LD_RT, PNP_IO0, { 0x780, 0 }, },
278 * Enable the logical devices of the Super I/O chip.
280 * TODO: Think about how to handle the case when a mainboard has multiple
281 * Super I/O chips soldered on.
282 * TODO: Can this code be simplified a bit?
284 * @param dev The device to use.
286 static void enable_dev(device_t dev)
289 int tmp[MAX_LOGICAL_DEVICES];
293 /* Read the device ID and revision of the Super I/O chip. */
294 smsc_pnp_enter_conf_state(dev);
295 superio_id = pnp_read_config(dev, DEVICE_ID_REG);
296 superio_rev = pnp_read_config(dev, DEVICE_REV_REG);
297 smsc_pnp_exit_conf_state(dev);
299 /* TODO: Error handling? */
301 printk_info("Found SMSC Super I/O (ID=0x%02x, rev=0x%02x)\n",
302 superio_id, superio_rev);
305 if(superio_id == LPC47M172) {
306 /* Do not use the default logical device number
307 * but instead the standard smsc registers set
310 /* TEST7 configuration register (0x29)
311 * bit 0 : LD_NUM (0 = new, 1 = std smsc)
313 test7 = pnp_read_config(dev, DEVICE_TEST7_REG);
315 pnp_write_config(dev, DEVICE_TEST7_REG, test7);
319 /* Find the correct Super I/O. */
320 for (i = 0; i < ARRAY_SIZE(logical_device_table); i++)
321 if (logical_device_table[i].superio_id == superio_id)
324 /* If no Super I/O was found, return. */
325 if (i == ARRAY_SIZE(logical_device_table))
328 /* Temporarily save the LD_FOO values. */
329 for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++)
330 tmp[j] = pnp_dev_info[j].function;
332 /* Replace the LD_FOO markers in pnp_dev_info[] with
333 * the real logical device IDs of this Super I/O chip.
335 for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++) {
336 fn = pnp_dev_info[j].function;
337 pnp_dev_info[j].function = logical_device_table[i].devs[fn];
340 /* Enable the specified devices (if present on the chip). */
341 pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info),
344 /* Restore LD_FOO values. */
345 for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++)
346 pnp_dev_info[j].function = tmp[j];
349 struct chip_operations superio_smsc_smscsuperio_ops = {
350 CHIP_NAME("Various SMSC Super I/Os")
351 .enable_dev = enable_dev