src/superio/smsc/lpc47b397/superio.c

   1 /* Copyright 2000  AG Electronics Ltd. */
   2 /* Copyright 2003-2004 Linux Networx */
   3 /* Copyright 2004 Tyan
   4  */
   5
   6 /* This code is distributed without warranty under the GPL v2 (see COPYING) */
   7
   8 #include <arch/io.h>
   9 #include <device/device.h>
  10 #include <device/pnp.h>
  11 #include <console/console.h>
  12 #include <device/smbus.h>
  13 #include <string.h>
  14 #include <bitops.h>
  15 #include <uart8250.h>
  16 #include <pc80/keyboard.h>
  17 #include <stdlib.h>
  18 #include "chip.h"
  19 #include "lpc47b397.h"
  20
  21
  22 static void pnp_enter_conf_state(device_t dev) {
  23         outb(0x55, dev->path.pnp.port);
  24 }
  25 static void pnp_exit_conf_state(device_t dev) {
  26         outb(0xaa, dev->path.pnp.port);
  27 }
  28
  29 static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t value)
  30 {
  31         outb(reg, port_base);
  32         outb(value, port_base + 1);
  33 }
  34
  35 static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg)
  36 {
  37         outb(reg, port_base);
  38         return inb(port_base + 1);
  39 }
  40
  41 static void enable_hwm_smbus(device_t dev) {
  42         /* enable SensorBus register access */
  43         uint8_t reg, value;
  44         reg = 0xf0;
  45         value = pnp_read_config(dev, reg);
  46         value |= 0x01;
  47         pnp_write_config(dev, reg, value);
  48 }
  49
  50
  51 static void lpc47b397_init(device_t dev)
  52 {
  53         struct superio_smsc_lpc47b397_config *conf;
  54         struct resource *res0, *res1;
  55         if (!dev->enabled) {
  56                 return;
  57         }
  58         conf = dev->chip_info;
  59         switch(dev->path.pnp.device) {
  60         case LPC47B397_SP1:
  61                 res0 = find_resource(dev, PNP_IDX_IO0);
  62                 init_uart8250(res0->base, &conf->com1);
  63                 break;
  64         case LPC47B397_SP2:
  65                 res0 = find_resource(dev, PNP_IDX_IO0);
  66                 init_uart8250(res0->base, &conf->com2);
  67                 break;
  68         case LPC47B397_KBC:
  69                 res0 = find_resource(dev, PNP_IDX_IO0);
  70                 res1 = find_resource(dev, PNP_IDX_IO1);
  71                 init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
  72                 break;
  73         }
  74
  75 }
  76
  77 void lpc47b397_pnp_set_resources(device_t dev)
  78 {
  79
  80         pnp_enter_conf_state(dev);
  81
  82         pnp_set_resources(dev);
  83
  84 #if 0
  85         dump_pnp_device(dev);
  86 #endif
  87
  88         pnp_exit_conf_state(dev);
  89
  90 }
  91
  92 void lpc47b397_pnp_enable_resources(device_t dev)
  93 {
  94
  95         pnp_enter_conf_state(dev);
  96
  97         pnp_enable_resources(dev);
  98
  99         switch(dev->path.pnp.device) {
 100         case LPC47B397_HWM:
 101                 printk_debug("lpc47b397 SensorBus Register Access enabled\r\n");
 102                 pnp_set_logical_device(dev);
 103                 enable_hwm_smbus(dev);
 104                 break;
 105         }
 106
 107 #if 0
 108         dump_pnp_device(dev);
 109 #endif
 110
 111         pnp_exit_conf_state(dev);
 112
 113 }
 114
 115 void lpc47b397_pnp_enable(device_t dev)
 116 {
 117
 118         pnp_enter_conf_state(dev);
 119
 120         pnp_set_logical_device(dev);
 121
 122         if(dev->enabled) {
 123                 pnp_set_enable(dev, 1);
 124         }
 125         else {
 126                 pnp_set_enable(dev, 0);
 127         }
 128
 129         pnp_exit_conf_state(dev);
 130
 131 }
 132
 133 static struct device_operations ops = {
 134         .read_resources   = pnp_read_resources,
 135         .set_resources    = lpc47b397_pnp_set_resources,
 136         .enable_resources = lpc47b397_pnp_enable_resources,
 137         .enable           = lpc47b397_pnp_enable,
 138         .init             = lpc47b397_init,
 139 };
 140
 141
 142 #define HWM_INDEX 0
 143 #define HWM_DATA  1
 144 #define SB_INDEX  0x0b
 145 #define SB_DATA0  0x0c
 146 #define SB_DATA1  0x0d
 147 #define SB_DATA2  0x0e
 148 #define SB_DATA3  0x0f
 149
 150 static int lsmbus_read_byte(device_t dev, uint8_t address)
 151 {
 152         unsigned device;
 153         struct resource *res;
 154         int result;
 155
 156         device = dev->path.i2c.device;
 157
 158         res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
 159
 160         pnp_write_index(res->base+HWM_INDEX, 0, device); // why 0?
 161
 162         result = pnp_read_index(res->base+SB_INDEX, address); // we only read it one byte one time
 163
 164         return result;
 165 }
 166
 167 static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
 168 {
 169         unsigned device;
 170         struct resource *res;
 171
 172         device = dev->path.i2c.device;
 173         res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
 174
 175         pnp_write_index(res->base+HWM_INDEX, 0, device); // why 0?
 176
 177         pnp_write_index(res->base+SB_INDEX, address, val); // we only write it one byte one time
 178
 179         return 0;
 180 }
 181
 182 static struct smbus_bus_operations lops_smbus_bus = {
 183 //      .recv_byte  = lsmbus_recv_byte,
 184 //      .send_byte  = lsmbus_send_byte,
 185         .read_byte  = lsmbus_read_byte,
 186         .write_byte = lsmbus_write_byte,
 187 };
 188 static struct device_operations ops_hwm = {
 189         .read_resources   = pnp_read_resources,
 190         .set_resources    = lpc47b397_pnp_set_resources,
 191         .enable_resources = lpc47b397_pnp_enable_resources,
 192         .enable           = lpc47b397_pnp_enable,
 193         .init             = lpc47b397_init,
 194         .scan_bus         = scan_static_bus,
 195         .ops_smbus_bus    = &lops_smbus_bus,
 196 };
 197
 198 static struct pnp_info pnp_dev_info[] = {
 199         { &ops, LPC47B397_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
 200         { &ops, LPC47B397_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
 201         { &ops, LPC47B397_SP1,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 202         { &ops, LPC47B397_SP2,  PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 203         { &ops, LPC47B397_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
 204         { &ops_hwm, LPC47B397_HWM,  PNP_IO0, { 0x7f0, 0 }, },
 205         { &ops, LPC47B397_RT,   PNP_IO0, { 0x780, 0 }, },
 206 };
 207
 208 static void enable_dev(struct device *dev)
 209 {
 210         pnp_enable_devices(dev, &pnp_ops,
 211                 ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 212 }
 213
 214 struct chip_operations superio_smsc_lpc47b397_ops = {
 215         CHIP_NAME("SMSC LPC47B397 Super I/O")
 216         .enable_dev = enable_dev,
 217 };
 218