2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Corey Osgood <corey_osgood@verizon.net>
5 * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <device/pci_ids.h>
28 * Print an error, should it occur. If no error, just exit.
30 * @param host_status The data returned on the host status register after
31 * a transaction is processed.
32 * @param loops The number of times a transaction was attempted.
34 static void smbus_print_error(u8 host_status, int loops)
36 /* Check if there actually was an error. */
37 if ((host_status == 0x00 || host_status == 0x40 ||
38 host_status == 0x42) && (loops < SMBUS_TIMEOUT))
41 if (loops >= SMBUS_TIMEOUT)
42 print_err("SMBus timeout\r\n");
43 if (host_status & (1 << 4))
44 print_err("Interrupt/SMI# was Failed Bus Transaction\r\n");
45 if (host_status & (1 << 3))
46 print_err("Bus error\r\n");
47 if (host_status & (1 << 2))
48 print_err("Device error\r\n");
49 if (host_status & (1 << 1))
50 print_debug("Interrupt/SMI# completed successfully\r\n");
51 if (host_status & (1 << 0))
52 print_err("Host busy\r\n");
56 * Wait for the SMBus to become ready to process the next transaction.
58 static void smbus_wait_until_ready(void)
62 PRINT_DEBUG("Waiting until SMBus ready\r\n");
65 /* Yes, this is a mess, but it's the easiest way to do it. */
66 while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT)
69 smbus_print_error(inb(SMBHSTSTAT), loops);
73 * Reset and take ownership of the SMBus.
75 static void smbus_reset(void)
77 outb(HOST_RESET, SMBHSTSTAT);
79 /* Datasheet says we have to read it to take ownership of SMBus. */
82 PRINT_DEBUG("After reset status: ");
83 PRINT_DEBUG_HEX16(inb(SMBHSTSTAT));
88 * Read a byte from the SMBus.
90 * @param dimm The address location of the DIMM on the SMBus.
91 * @param offset The offset the data is located at.
93 u8 smbus_read_byte(u8 dimm, u8 offset)
98 PRINT_DEBUG_HEX16(dimm);
99 PRINT_DEBUG(" OFFSET ");
100 PRINT_DEBUG_HEX16(offset);
105 /* Clear host data port. */
106 outb(0x00, SMBHSTDAT0);
108 smbus_wait_until_ready();
110 /* Actual addr to reg format. */
113 outb(dimm, SMBXMITADD);
114 outb(offset, SMBHSTCMD);
116 /* Start transaction, byte data read. */
117 outb(0x48, SMBHSTCTL);
119 smbus_wait_until_ready();
121 val = inb(SMBHSTDAT0);
122 PRINT_DEBUG("Read: ");
123 PRINT_DEBUG_HEX16(val);
126 /* Probably don't have to do this, but it can't hurt. */
133 * Enable the SMBus on VT8237R-based systems.
135 void enable_smbus(void)
139 /* Power management controller */
140 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
141 PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
142 if (dev == PCI_DEV_INVALID) {
143 /* Power management controller */
144 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
145 PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
146 if (dev == PCI_DEV_INVALID)
147 die("Power management controller not found\r\n");
151 * 7 = SMBus Clock from RTC 32.768KHz
152 * 5 = Internal PLL reset from susp
154 pci_write_config8(dev, VT8237R_POWER_WELL, 0xa0);
157 pci_write_config16(dev, VT8237R_SMBUS_IO_BASE_REG,
158 VT8237R_SMBUS_IO_BASE | 0x1);
160 /* SMBus Host Configuration, enable. */
161 pci_write_config8(dev, VT8237R_SMBUS_HOST_CONF, 0x01);
163 /* Make it work for I/O. */
164 pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
168 /* Reset the internal pointer. */
173 * A fixup for some systems that need time for the SMBus to "warm up". This is
174 * needed on some VT823x based systems, where the SMBus spurts out bad data for
175 * a short time after power on. This has been seen on the VIA Epia series and
176 * Jetway J7F2-series. It reads the ID byte from SMBus, looking for
177 * known-good data from a slot/address. Exits on either good data or a timeout.
179 * TODO: This should probably go into some global file, but one would need to
180 * be created just for it. If some other chip needs/wants it, we can
181 * worry about it then.
183 * @param ctrl The memory controller and SMBus addresses.
185 void smbus_fixup(const struct mem_controller *ctrl)
187 int i, ram_slots, current_slot = 0;
190 ram_slots = ARRAY_SIZE(ctrl->channel0);
192 print_err("smbus_fixup() thinks there are no RAM slots!\r\n");
196 PRINT_DEBUG("Waiting for SMBus to warm up");
199 * Bad SPD data should be either 0 or 0xff, but YMMV. So we look for
200 * the ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between).
201 * VT8237R has only been seen on DDR and DDR2 based systems, so far.
203 for (i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) ||
204 (result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++) {
206 if (current_slot > ram_slots)
209 result = smbus_read_byte(ctrl->channel0[current_slot],
215 if (i >= SMBUS_TIMEOUT)
216 print_err("SMBus timed out while warming up\r\n");
218 PRINT_DEBUG("Done\r\n");
221 /* FIXME: Better separate the NB and SB, will be done once it works. */
223 void vt8237_sb_enable_fid_vid(void)
225 device_t dev, devctl;
227 /* Power management controller */
228 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
229 PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
230 if (dev == PCI_DEV_INVALID) {
231 /* Power management controller */
232 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
233 PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
234 if (dev == PCI_DEV_INVALID)
237 devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
238 PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);
239 if (devctl == PCI_DEV_INVALID)
242 /* TODO: Why is this an extra block? */
245 tmp = pci_read_config8(devctl, 0xec);
246 print_debug("EC is ");
247 print_debug_hex8(tmp);
248 print_debug(" E5 is ");
249 tmp = pci_read_config8(dev, 0xe5);
250 print_debug_hex8(tmp);
253 /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
254 pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
256 /* Enable ACPI accessm RTC signal gated with PSON. */
257 pci_write_config8(dev, 0x81, 0x84);
260 * Allow SLP# signal to assert LDTSTOP_L.
261 * Will work for C3 and for FID/VID change.
265 outb(0xff, VT8237R_ACPI_IO_BASE + 0x50); /* Maybe unneeded? */
266 // outb(0x4, VT8237R_ACPI_IO_BASE + 0x50); /* Maybe unneeded? */
268 /* It seems for AMD LDTSTP is connected not to SLP anymore. */
269 /* Enable 0: DPSLP# / DPRSTP# / VRDSLP */
272 * Enable SATA LED, VR timer = 100us.
273 * Enable DPSLP# / DPRSTP# / VRDSLP - WARNING LDTSTP connetcs
274 * to some of those pins! (and not to SLP as on R ver).
276 pci_write_config8(dev, 0xe5, 0x69); /* FIXME */
279 * REQ5 as PCI request input - should be together with
280 * INTE-INTH. Fast VR timer disable - need for LDTSTP signal.
282 pci_write_config8(dev, 0xe4, 0xa5);
284 /* Reduce further the STPCLK/LDTSTP signal to 5us. */
285 pci_write_config8(dev, 0xec, 0x4);
287 /* Host Bus Power Management Control, maybe not needed. */
288 pci_write_config8(dev, 0x8c, 0x5);
290 /* So the chip knows we are on AMD. */
291 pci_write_config8(devctl, 0x7c, 0x77);
293 devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
295 if (devctl == PCI_DEV_INVALID)
299 * Enable C2NOW delay to PSTATECTL VID / FID Change Delay
300 * to P-State Control.
302 pci_write_config8(devctl, 0xa6, 0x83);
304 // return; // FIXME: Fall through some revs have it old way.
307 /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
308 pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
310 /* Enable ACPI accessm RTC signal gated with PSON. */
311 pci_write_config8(dev, 0x81, 0x84);
314 * Allow SLP# signal to assert LDTSTOP_L.
315 * Will work for C3 and for FID/VID change.
317 outb(0x1, VT8237R_ACPI_IO_BASE + 0x11);
320 void enable_rom_decode(void)
324 /* Power management controller */
325 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
326 PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
327 if (dev == PCI_DEV_INVALID) {
328 /* Power management controller */
329 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
330 PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
331 if (dev == PCI_DEV_INVALID)
335 /* ROM decode last 1MB FFC00000 - FFFFFFFF. */
336 pci_write_config8(dev, 0x41, 0x7f);
339 #if defined(__GNUC__)
340 void vt8237_early_spi_init(void)
343 volatile u16 *spireg;
346 /* Bus Control and Power Management */
347 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
348 PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
350 if (dev == PCI_DEV_INVALID)
351 die("SB not found\r\n");
353 /* Put SPI base 20 d0 fe. */
354 tmp = pci_read_config32(dev, 0xbc);
355 pci_write_config32(dev, 0xbc,
356 (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000));
358 /* Set SPI clock to 33MHz. */
359 spireg = (u16 *) (VT8237S_SPI_MEM_BASE + 0x6c);
364 /* This #if is special. ROMCC chokes on the (rom == NULL) comparison.
365 * Since the whole function is only called for one target and that target
366 * is compiled with GCC, hide the function from ROMCC and be happy.
368 #if defined(__GNUC__)
372 * 19:16 4 bit position in shadow EEPROM
377 * 27 ERDBG - enable read from 0x5c
380 * 24 SEEPR - write 1 when done updating, wait until SEELD is
382 * cleared by reset, if it is 1 writing is disabled
383 * 19:16 4 bit position in shadow EEPROM
384 * 15:0 data from shadow EEPROM
386 * After PCIRESET SEELD and SEEPR must be 1 and 1.
389 /* 1 = needs PCI reset, 0 don't reset, network initialized. */
391 /* FIXME: Maybe close the debug register after use? */
393 #define LAN_TIMEOUT 0x7FFFFFFF
395 int vt8237_early_network_init(struct vt8237_network_rom *rom)
397 struct vt8237_network_rom n;
403 unsigned int checksum;
405 /* Network adapter */
406 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
407 PCI_DEVICE_ID_VIA_8233_7), 0);
408 if (dev == PCI_DEV_INVALID) {
409 print_err("Network is disabled, please enable\n");
413 tmp = pci_read_config32(dev, 0x5c);
414 tmp |= 0x08000000; /* Enable ERDBG. */
415 pci_write_config32(dev, 0x5c, tmp);
417 status = ((pci_read_config32(dev, 0x5c) >> 24) & 0x3);
419 /* Network controller OK, EEPROM loaded. */
424 print_err("No config data specified, using default MAC!\n");
425 n.mac_address[0] = 0x0;
426 n.mac_address[1] = 0x0;
427 n.mac_address[2] = 0xde;
428 n.mac_address[3] = 0xad;
429 n.mac_address[4] = 0xbe;
430 n.mac_address[5] = 0xef;
439 n.pmu_data_reg = 0x0;
454 rom_write = (u16 *) rom;
456 /* Write all data except checksum and second to last byte. */
457 tmp &= 0xff000000; /* Leave reserved bits in. */
458 for (i = 0; i < 15; i++) {
459 pci_write_config32(dev, 0x58, tmp | (i << 16) | rom_write[i]);
460 /* Lame code FIXME */
461 checksum += rom_write[i] & 0xff;
462 /* checksum %= 256; */
463 checksum += (rom_write[i] >> 8) & 0xff;
464 /* checksum %= 256; */
467 checksum += (rom_write[15] & 0xff);
468 checksum = ~(checksum & 0xff);
469 tmp |= (((checksum & 0xff) << 8) | rom_write[15]);
471 /* Write last byte and checksum. */
472 pci_write_config32(dev, 0x58, (15 << 16) | tmp);
474 tmp = pci_read_config32(dev, 0x5c);
475 pci_write_config32(dev, 0x5c, tmp | 0x01000000); /* Toggle SEEPR. */
477 /* Yes, this is a mess, but it's the easiest way to do it. */
478 while ((((pci_read_config32(dev, 0x5c) >> 25) & 1) == 0)
479 && (loops < LAN_TIMEOUT)) {
483 if (loops >= LAN_TIMEOUT) {
484 print_err("Timeout - LAN controller didn't accept config\n");
488 /* We are done, config will be used after PCIRST#. */