1 #include <console/console.h>
2 #include <device/device.h>
3 #include <device/pci.h>
4 #include <device/pci_ops.h>
5 #include <device/pci_ids.h>
7 #include <pc80/mc146818rtc.h>
14 void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);
15 static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
16 static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
17 static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
20 Our IDSEL mappings are as follows
21 PCI slot is AD31 (device 15) (00:14.0)
22 Southbridge is AD28 (device 12) (00:11.0)
24 static void pci_routing_fixup(struct device *dev)
27 printk_info("%s: dev is %p\n", __func__, dev);
29 /* initialize PCI interupts - these assignments depend
30 on the PCB routing of PINTA-D
37 pci_write_config8(dev, 0x55, 0xb0);
38 pci_write_config8(dev, 0x56, 0xa5);
39 pci_write_config8(dev, 0x57, 0xc0);
42 // Standard southbridge components
43 printk_info("setting southbridge\n");
44 pci_assign_irqs(0, 0x11, southbridgeIrqs);
46 // Ethernet built into southbridge
47 printk_info("setting ethernet\n");
48 pci_assign_irqs(0, 0x12, enetIrqs);
51 printk_info("setting pci slot\n");
52 pci_assign_irqs(0, 0x14, slotIrqs);
53 printk_info("%s: DONE\n", __func__);
56 static void vt8231_init(struct device *dev)
58 unsigned char enables;
59 struct southbridge_via_vt8231_config *conf = dev->chip_info;
61 printk_debug("vt8231 init\n");
63 // enable the internal I/O decode
64 enables = pci_read_config8(dev, 0x6C);
66 pci_write_config8(dev, 0x6C, enables);
68 // Map 4MB of FLASH into the address space
69 pci_write_config8(dev, 0x41, 0x7f);
71 // Set bit 6 of 0x40, because Award does it (IO recovery time)
72 // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
73 // interrupts can be properly marked as level triggered.
74 enables = pci_read_config8(dev, 0x40);
75 pci_write_config8(dev, 0x40, enables);
77 // Set 0x42 to 0xf0 to match Award bios
78 enables = pci_read_config8(dev, 0x42);
80 pci_write_config8(dev, 0x42, enables);
82 // Set bit 3 of 0x4a, to match award (dummy pci request)
83 enables = pci_read_config8(dev, 0x4a);
85 pci_write_config8(dev, 0x4a, enables);
87 // Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
88 enables = pci_read_config8(dev, 0x4f);
90 pci_write_config8(dev, 0x4f, enables);
92 // Set 0x58 to 0x03 to match Award
93 pci_write_config8(dev, 0x58, 0x03);
95 // enable the ethernet/RTC
97 enables = pci_read_config8(dev, 0x51);
99 pci_write_config8(dev, 0x51, enables);
102 // enable IDE, since Linux won't do it.
103 // First do some more things to devfn (17,0)
104 // note: this should already be cleared, according to the book.
105 enables = pci_read_config8(dev, 0x50);
106 printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
107 enables &= ~8; // need manifest constant here!
108 printk_debug("set IDE reg. 50 to 0x%x\n", enables);
109 pci_write_config8(dev, 0x50, enables);
111 // set default interrupt values (IDE)
112 enables = pci_read_config8(dev, 0x4c);
113 printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf);
114 // clear out whatever was there.
117 printk_debug("setting reg. 4c to 0x%x\n", enables);
118 pci_write_config8(dev, 0x4c, enables);
120 // set up the serial port interrupts.
121 // com2 to 3, com1 to 4
122 pci_write_config8(dev, 0x46, 0x04);
123 pci_write_config8(dev, 0x47, 0x03);
124 pci_write_config8(dev, 0x6e, 0x98);
126 /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
127 pci_write_config8(dev, 0x40, 0x54);
134 static void southbridge_init(struct device *dev)
137 pci_routing_fixup(dev);
140 static struct device_operations vt8231_lpc_ops = {
141 .read_resources = pci_dev_read_resources,
142 .set_resources = pci_dev_set_resources,
143 .enable_resources = pci_dev_enable_resources,
144 .init = &southbridge_init,
145 .scan_bus = scan_static_bus,
150 static const struct pci_driver lpc_driver __pci_driver = {
151 .ops = &vt8231_lpc_ops,
152 .vendor = PCI_VENDOR_ID_VIA,
153 .device = PCI_DEVICE_ID_VIA_8231,