src/southbridge/sis/sis966/sis966_lpc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2003 Linux Networx
   5  * Copyright (C) 2003 SuSE Linux AG
   6  * Copyright (C) 2004 Tyan Computer
   7  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   8  * Copyright (C) 2006,2007 AMD
   9  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
  10  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
  11  * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  26  */
  27
  28 #include <console/console.h>
  29 #include <device/device.h>
  30 #include <device/pci.h>
  31 #include <device/pnp.h>
  32 #include <device/pci_ids.h>
  33 #include <device/pci_ops.h>
  34 #include <pc80/mc146818rtc.h>
  35 #include <pc80/isa-dma.h>
  36 #include <bitops.h>
  37 #include <arch/io.h>
  38 #include <cpu/x86/lapic.h>
  39 #include <stdlib.h>
  40 #include "sis966.h"
  41 #include <pc80/keyboard.h>
  42
  43 #define NMI_OFF 0
  44
  45 struct ioapicreg {
  46         unsigned int reg;
  47         unsigned int value_low, value_high;
  48 };
  49
  50 static struct ioapicreg ioapicregvalues[] = {
  51 #define ALL             (0xff << 24)
  52 #define NONE            (0)
  53 #define DISABLED        (1 << 16)
  54 #define ENABLED         (0 << 16)
  55 #define TRIGGER_EDGE    (0 << 15)
  56 #define TRIGGER_LEVEL   (1 << 15)
  57 #define POLARITY_HIGH   (0 << 13)
  58 #define POLARITY_LOW    (1 << 13)
  59 #define PHYSICAL_DEST   (0 << 11)
  60 #define LOGICAL_DEST    (1 << 11)
  61 #define ExtINT          (7 << 8)
  62 #define NMI             (4 << 8)
  63 #define SMI             (2 << 8)
  64 #define INT             (1 << 8)
  65         /* IO-APIC virtual wire mode configuration */
  66         /* mask, trigger, polarity, destination, delivery, vector */
  67         {   0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE},
  68         {   1, DISABLED, NONE},
  69         {   2, DISABLED, NONE},
  70         {   3, DISABLED, NONE},
  71         {   4, DISABLED, NONE},
  72         {   5, DISABLED, NONE},
  73         {   6, DISABLED, NONE},
  74         {   7, DISABLED, NONE},
  75         {   8, DISABLED, NONE},
  76         {   9, DISABLED, NONE},
  77         {  10, DISABLED, NONE},
  78         {  11, DISABLED, NONE},
  79         {  12, DISABLED, NONE},
  80         {  13, DISABLED, NONE},
  81         {  14, DISABLED, NONE},
  82         {  15, DISABLED, NONE},
  83         {  16, DISABLED, NONE},
  84         {  17, DISABLED, NONE},
  85         {  18, DISABLED, NONE},
  86         {  19, DISABLED, NONE},
  87         {  20, DISABLED, NONE},
  88         {  21, DISABLED, NONE},
  89         {  22, DISABLED, NONE},
  90         {  23, DISABLED, NONE},
  91         /* Be careful and don't write past the end... */
  92 };
  93
  94 static void setup_ioapic(unsigned long ioapic_base)
  95 {
  96         int i;
  97         unsigned long value_low, value_high;
  98 //      unsigned long ioapic_base = 0xfec00000;
  99         volatile unsigned long *l;
 100         struct ioapicreg *a = ioapicregvalues;
 101
 102         ioapicregvalues[0].value_high = lapicid()<<(56-32);
 103
 104         l = (unsigned long *) ioapic_base;
 105
 106         for (i = 0; i < ARRAY_SIZE(ioapicregvalues);
 107              i++, a++) {
 108                 l[0] = (a->reg * 2) + 0x10;
 109                 l[4] = a->value_low;
 110                 value_low = l[4];
 111                 l[0] = (a->reg *2) + 0x11;
 112                 l[4] = a->value_high;
 113                 value_high = l[4];
 114                 if ((i==0) && (value_low == 0xffffffff)) {
 115                         printk_warning("IO APIC not responding.\n");
 116                         return;
 117                 }
 118                 printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
 119                             a->reg, a->value_low, a->value_high);
 120         }
 121 }
 122
 123 // 0x7a or e3
 124 #define PREVIOUS_POWER_STATE    0x7A
 125
 126 #define MAINBOARD_POWER_OFF     0
 127 #define MAINBOARD_POWER_ON      1
 128 #define SLOW_CPU_OFF    0
 129 #define SLOW_CPU__ON    1
 130
 131 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
 132 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL      MAINBOARD_POWER_ON
 133 #endif
 134
 135 static void lpc_common_init(device_t dev)
 136 {
 137         uint8_t byte;
 138         uint32_t dword;
 139
 140         /* IO APIC initialization */
 141         byte = pci_read_config8(dev, 0x74);
 142         byte |= (1<<0); // enable APIC
 143         pci_write_config8(dev, 0x74, byte);
 144         dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
 145
 146         setup_ioapic(dword);
 147
 148 }
 149
 150 static void lpc_slave_init(device_t dev)
 151 {
 152         lpc_common_init(dev);
 153 }
 154
 155
 156 static void lpc_usb_legacy_init(device_t dev)
 157 {
 158     uint16_t acpi_base;
 159
 160     acpi_base = (pci_read_config8(dev,0x75) << 8);
 161
 162     outb(inb(acpi_base + 0xbb) |0x80, acpi_base + 0xbb);
 163     outb(inb(acpi_base + 0xba) |0x80, acpi_base + 0xba);
 164 }
 165
 166 static void lpc_init(device_t dev)
 167 {
 168          uint8_t byte;
 169          uint8_t byte_old;
 170          int on;
 171          int nmi_option;
 172
 173         printk_debug("LPC_INIT -------->\n");
 174         init_pc_keyboard(0x60, 0x64, 0);
 175
 176         lpc_usb_legacy_init(dev);
 177          lpc_common_init(dev);
 178
 179         /* power after power fail */
 180
 181
 182         on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 183         get_option(&on, "power_on_after_fail");
 184         byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
 185         byte &= ~0x40;
 186         if (!on) {
 187                 byte |= 0x40;
 188         }
 189         pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
 190         printk_info("set power %s after power fail\n", on?"on":"off");
 191
 192         /* Throttle the CPU speed down for testing */
 193         on = SLOW_CPU_OFF;
 194         get_option(&on, "slow_cpu");
 195         if(on) {
 196                 uint16_t pm10_bar;
 197                 uint32_t dword;
 198                 pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
 199                 outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
 200                 dword = inl(pm10_bar + 0x10);
 201                 on = 8-on;
 202                 printk_debug("Throttling CPU %2d.%1.1d percent.\n",
 203                                 (on*12)+(on>>1),(on&1)*5);
 204         }
 205
 206         /* Enable Error reporting */
 207         /* Set up sync flood detected */
 208         byte = pci_read_config8(dev, 0x47);
 209         byte |= (1 << 1);
 210         pci_write_config8(dev, 0x47, byte);
 211
 212         /* Set up NMI on errors */
 213         byte = inb(0x70); // RTC70
 214         byte_old = byte;
 215         nmi_option = NMI_OFF;
 216         get_option(&nmi_option, "nmi");
 217         if (nmi_option) {
 218                 byte &= ~(1 << 7); /* set NMI */
 219         } else {
 220                 byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
 221         }
 222         if( byte != byte_old) {
 223                 outb(0x70, byte);
 224         }
 225
 226         /* Initialize the real time clock */
 227         rtc_init(0);
 228
 229         /* Initialize isa dma */
 230         isa_dma_init();
 231
 232         printk_debug("LPC_INIT <--------\n");
 233 }
 234
 235 static void sis966_lpc_read_resources(device_t dev)
 236 {
 237         struct resource *res;
 238
 239         /* Get the normal pci resources of this device */
 240         pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
 241
 242         /* Add an extra subtractive resource for both memory and I/O. */
 243         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 244         res->base = 0;
 245         res->size = 0x1000;
 246         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 247                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 248
 249         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 250         res->base = 0xff800000;
 251         res->size = 0x00800000; /* 8 MB for flash */
 252         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 253                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 254
 255         res = new_resource(dev, 3); /* IOAPIC */
 256         res->base = 0xfec00000;
 257         res->size = 0x00001000;
 258         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 259 }
 260
 261 /**
 262  * @brief Enable resources for children devices
 263  *
 264  * @param dev the device whos children's resources are to be enabled
 265  *
 266  * This function is call by the global enable_resources() indirectly via the
 267  * device_operation::enable_resources() method of devices.
 268  *
 269  * Indirect mutual recursion:
 270  *      enable_childrens_resources() -> enable_resources()
 271  *      enable_resources() -> device_operation::enable_resources()
 272  *      device_operation::enable_resources() -> enable_children_resources()
 273  */
 274 static void sis966_lpc_enable_childrens_resources(device_t dev)
 275 {
 276         unsigned link;
 277         uint32_t reg, reg_var[4];
 278         int i;
 279         int var_num = 0;
 280
 281         reg = pci_read_config32(dev, 0xa0);
 282
 283         for (link = 0; link < dev->links; link++) {
 284                 device_t child;
 285                 for (child = dev->link[link].children; child; child = child->sibling) {
 286                         enable_resources(child);
 287                         if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
 288                                 for(i=0;i<child->resources;i++) {
 289                                         struct resource *res;
 290                                         unsigned long base, end; // don't need long long
 291                                         res = &child->resource[i];
 292                                         if(!(res->flags & IORESOURCE_IO)) continue;
 293                                         base = res->base;
 294                                         end = resource_end(res);
 295                                         printk_debug("sis966 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end);
 296                                         switch(base) {
 297                                         case 0x3f8: // COM1
 298                                                 reg |= (1<<0);  break;
 299                                         case 0x2f8: // COM2
 300                                                 reg |= (1<<1);  break;
 301                                         case 0x378: // Parallal 1
 302                                                 reg |= (1<<24); break;
 303                                         case 0x3f0: // FD0
 304                                                 reg |= (1<<20); break;
 305                                         case 0x220:  // Aduio 0
 306                                                 reg |= (1<<8);  break;
 307                                         case 0x300:  // Midi 0
 308                                                 reg |= (1<<12); break;
 309                                         }
 310                                         if( (base == 0x290) || (base >= 0x400)) {
 311                                                 if(var_num>=4) continue; // only 4 var ; compact them ?
 312                                                 reg |= (1<<(28+var_num));
 313                                                 reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
 314                                         }
 315                                 }
 316                         }
 317                 }
 318         }
 319         pci_write_config32(dev, 0xa0, reg);
 320         for(i=0;i<var_num;i++) {
 321                 pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
 322         }
 323
 324
 325 }
 326
 327 static void sis966_lpc_enable_resources(device_t dev)
 328 {
 329         pci_dev_enable_resources(dev);
 330         sis966_lpc_enable_childrens_resources(dev);
 331 }
 332
 333 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 334 {
 335         pci_write_config32(dev, 0x40,
 336                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 337 }
 338
 339 static struct pci_operations lops_pci = {
 340         .set_subsystem  = lpci_set_subsystem,
 341 };
 342
 343 static struct device_operations lpc_ops  = {
 344         .read_resources = sis966_lpc_read_resources,
 345         .set_resources  = pci_dev_set_resources,
 346         .enable_resources       = sis966_lpc_enable_resources,
 347         .init           = lpc_init,
 348         .scan_bus       = scan_static_bus,
 349 //      .enable         = sis966_enable,
 350         .ops_pci        = &lops_pci,
 351 };
 352 static const struct pci_driver lpc_driver __pci_driver = {
 353         .ops    = &lpc_ops,
 354         .vendor = PCI_VENDOR_ID_SIS,
 355         .device = PCI_DEVICE_ID_SIS_SIS966_LPC,
 356 };
 357
 358 static struct device_operations lpc_slave_ops  = {
 359         .read_resources = sis966_lpc_read_resources,
 360         .set_resources  = pci_dev_set_resources,
 361         .enable_resources       = pci_dev_enable_resources,
 362         .init           = lpc_slave_init,
 363 //      .enable         = sis966_enable,
 364         .ops_pci        = &lops_pci,
 365 };