Move the v3 resource allocator to v2.
authorMyles Watson <mylesgw@gmail.com>
Thu, 2 Jul 2009 18:56:24 +0000 (18:56 +0000)
committerMyles Watson <mylesgw@gmail.com>
Thu, 2 Jul 2009 18:56:24 +0000 (18:56 +0000)
commit29cc9eda2021a87396ef31a6fc81daff6fd1be7a
treed3dfa07ca85547c77c5d07825fc8afcc19489076
parent2468331952bae0abdc4d76dbe6cf26f05b7825e5
Move the v3 resource allocator to v2.

Major changes:
1. Separate resource allocation into:
A. Read Resources
B. Avoid fixed resources (constrain limits)
C. Allocate resources
D. Set resources

Usage notes:
Resources which have IORESOURCE_FIXED set in the flags constrain the placement
of other resources.  All fixed resources will end up outside (above or below)
the allocated resources.

Domains usually start with base = 0 and limit = 2^address_bits - 1.

I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is
still there for resources.  Some platforms may want to change that, but I didn't
want to break anyone's board.

Resources are allocated in a single block for memory and another for I/O.
Currently the resource allocator doesn't support holes.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
62 files changed:
src/cpu/amd/sc520/sc520.c
src/cpu/emulation/qemu-x86/northbridge.c
src/cpu/ppc/ppc4xx/pci_domain.c
src/devices/cardbus_device.c
src/devices/device.c
src/devices/device_util.c
src/devices/pci_device.c
src/devices/root_device.c
src/include/device/device.h
src/include/device/resource.h
src/northbridge/amd/amdfam10/northbridge.c
src/northbridge/amd/amdk8/misc_control.c
src/northbridge/amd/amdk8/northbridge.c
src/northbridge/amd/gx1/northbridge.c
src/northbridge/amd/gx2/northbridge.c
src/northbridge/amd/lx/northbridge.c
src/northbridge/ibm/cpc710/cpc710_northbridge.c
src/northbridge/ibm/cpc925/cpc925_northbridge.c
src/northbridge/intel/e7501/northbridge.c
src/northbridge/intel/e7520/northbridge.c
src/northbridge/intel/e7525/northbridge.c
src/northbridge/intel/i3100/northbridge.c
src/northbridge/intel/i440bx/northbridge.c
src/northbridge/intel/i82810/northbridge.c
src/northbridge/intel/i82830/northbridge.c
src/northbridge/intel/i855gme/northbridge.c
src/northbridge/intel/i855pm/northbridge.c
src/northbridge/intel/i945/northbridge.c
src/northbridge/motorola/mpc107/mpc107_northbridge.c
src/northbridge/via/cn400/northbridge.c
src/northbridge/via/cn700/northbridge.c
src/northbridge/via/cx700/cx700_lpc.c
src/northbridge/via/cx700/northbridge.c
src/northbridge/via/vt8601/northbridge.c
src/northbridge/via/vt8623/northbridge.c
src/northbridge/via/vx800/northbridge.c
src/southbridge/amd/amd8111/amd8111_lpc.c
src/southbridge/amd/amd8131/amd8131_bridge.c
src/southbridge/amd/amd8132/amd8132_bridge.c
src/southbridge/amd/cs5530/cs5530_isa.c
src/southbridge/amd/cs5535/cs5535.c
src/southbridge/amd/cs5536/cs5536.c
src/southbridge/amd/sb600/sb600_lpc.c
src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
src/southbridge/intel/esb6300/esb6300_lpc.c
src/southbridge/intel/i3100/i3100_lpc.c
src/southbridge/intel/i82371eb/i82371eb_isa.c
src/southbridge/intel/i82801ca/i82801ca_lpc.c
src/southbridge/intel/i82801dbm/i82801dbm_lpc.c
src/southbridge/intel/i82801er/i82801er_lpc.c
src/southbridge/intel/i82801gx/i82801gx_lpc.c
src/southbridge/intel/i82801xx/i82801xx_lpc.c
src/southbridge/nvidia/ck804/ck804_lpc.c
src/southbridge/nvidia/ck804/ck804_pci.c
src/southbridge/nvidia/mcp55/mcp55_lpc.c
src/southbridge/nvidia/mcp55/mcp55_pci.c
src/southbridge/ricoh/rl5c476/rl5c476.c
src/southbridge/sis/sis966/sis966_lpc.c
src/southbridge/via/vt8231/vt8231_lpc.c
src/southbridge/via/vt8235/vt8235_lpc.c
src/southbridge/winbond/w83c553/w83c553f.c