2 * (C) 2003 Linux Networx, SuSE Linux AG
3 * Copyright 2004 Tyan Computer
5 * 2006.1 yhlu add dest apicid for IRQ0
8 #include <console/console.h>
9 #include <device/device.h>
10 #include <device/pci.h>
11 #include <device/pnp.h>
12 #include <device/pci_ids.h>
13 #include <device/pci_ops.h>
14 #include <pc80/mc146818rtc.h>
15 #include <pc80/isa-dma.h>
18 #include <arch/ioapic.h>
19 #include <cpu/x86/lapic.h>
23 #define CK804_CHIP_REV 2
28 #define PREVIOUS_POWER_STATE 0x7A
30 #define MAINBOARD_POWER_OFF 0
31 #define MAINBOARD_POWER_ON 1
32 #define SLOW_CPU_OFF 0
33 #define SLOW_CPU__ON 1
35 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
36 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
39 static void lpc_common_init(device_t dev)
44 /* I/O APIC initialization */
45 byte = pci_read_config8(dev, 0x74);
46 byte |= (1 << 0); /* Enable APIC. */
47 pci_write_config8(dev, 0x74, byte);
48 dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */
50 setup_ioapic(dword, 0); // Don't rename IOAPIC ID
53 dword = pci_read_config32(dev, 0xe4);
55 pci_write_config32(dev, 0xe4, dword);
59 static void lpc_slave_init(device_t dev)
64 static void rom_dummy_write(device_t dev)
69 old = pci_read_config8(dev, 0x88);
72 pci_write_config8(dev, 0x88, new);
74 old = pci_read_config8(dev, 0x6d);
77 pci_write_config8(dev, 0x6d, new);
80 p = (uint8_t *) 0xffffffe0;
86 old = pci_read_config8(dev, 0x6d);
89 pci_write_config8(dev, 0x6d, new);
92 static void enable_hpet(struct device *dev)
94 unsigned long hpet_address;
96 pci_write_config32(dev, 0x44, 0xfed00001);
97 hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe;
98 printk(BIOS_DEBUG, "Enabling HPET @0x%lx\n", hpet_address);
103 static void lpc_init(device_t dev)
105 uint8_t byte, byte_old;
108 lpc_common_init(dev);
110 pm_base = pci_read_config32(dev, 0x60) & 0xff00;
111 printk(BIOS_INFO, "%s: pm_base = %x \n", __func__, pm_base);
113 #if CK804_CHIP_REV==1
114 if (dev->bus->secondary != 1)
119 /* Posted memory write enable */
120 byte = pci_read_config8(dev, 0x46);
121 pci_write_config8(dev, 0x46, byte | (1 << 0));
124 /* power after power fail */
125 on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
126 get_option(&on, "power_on_after_fail");
127 byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
131 pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
132 printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off");
134 /* Throttle the CPU speed down for testing. */
136 get_option(&on, "slow_cpu");
140 pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00);
141 outl(((on << 1) + 0x10), (pm10_bar + 0x10));
142 dword = inl(pm10_bar + 0x10);
144 printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
145 (on * 12) + (on >> 1), (on & 1) * 5);
148 // default is enabled
149 /* Enable Port 92 fast reset. */
150 byte = pci_read_config8(dev, 0xe8);
152 pci_write_config8(dev, 0xe8, byte);
155 /* Enable Error reporting. */
156 /* Set up sync flood detected. */
157 byte = pci_read_config8(dev, 0x47);
159 pci_write_config8(dev, 0x47, byte);
161 /* Set up NMI on errors. */
162 byte = inb(0x70); /* RTC70 */
164 nmi_option = NMI_OFF;
165 get_option(&nmi_option, "nmi");
167 byte &= ~(1 << 7); /* Set NMI. */
169 byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */
171 if (byte != byte_old)
174 /* Initialize the real time clock (RTC). */
177 /* Initialize ISA DMA. */
180 /* Initialize the High Precision Event Timers (HPET). */
183 rom_dummy_write(dev);
186 static void ck804_lpc_read_resources(device_t dev)
188 struct resource *res;
191 /* Get the normal PCI resources of this device. */
192 /* We got one for APIC, or one more for TRAP. */
193 pci_dev_read_resources(dev);
195 /* Get resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL. */
196 for (index = 0x60; index <= 0x68; index += 4) /* We got another 3. */
197 pci_get_resource(dev, index);
198 compact_resources(dev);
200 /* Add an extra subtractive resource for both memory and I/O. */
201 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
204 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
205 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
207 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
208 res->base = 0xff800000;
209 res->size = 0x00800000; /* 8 MB for flash */
210 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
211 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
213 res = new_resource(dev, 3); /* IOAPIC */
214 res->base = IO_APIC_ADDR;
215 res->size = 0x00001000;
216 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
220 * Enable resources for children devices.
222 * This function is called by the global enable_resources() indirectly via the
223 * device_operation::enable_resources() method of devices.
226 static void ck804_lpc_enable_childrens_resources(device_t dev)
229 uint32_t reg, reg_var[4];
232 reg = pci_read_config32(dev, 0xa0);
234 for (link = dev->link_list; link; link = link->next) {
236 for (child = link->children; child; child = child->sibling) {
237 if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
238 struct resource *res;
239 for (res = child->resource_list; res; res = res->next) {
240 unsigned long base, end; // don't need long long
241 if (!(res->flags & IORESOURCE_IO))
244 end = resource_end(res);
245 printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\n", dev_path(child), base, end);
253 case 0x378: // Parallel 1
259 case 0x220: // Audio 0
262 case 0x300: // Midi 0
266 if (base == 0x290 || base >= 0x400) {
268 continue; // only 4 var ; compact them ?
269 reg |= (1 << (28 + var_num));
270 reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16);
276 pci_write_config32(dev, 0xa0, reg);
277 for (i = 0; i < var_num; i++)
278 pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]);
281 static void ck804_lpc_enable_resources(device_t dev)
283 pci_dev_enable_resources(dev);
284 ck804_lpc_enable_childrens_resources(dev);
287 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
289 pci_write_config32(dev, 0x40,
290 ((device & 0xffff) << 16) | (vendor & 0xffff));
293 static struct pci_operations lops_pci = {
294 .set_subsystem = lpci_set_subsystem,
297 static struct device_operations lpc_ops = {
298 .read_resources = ck804_lpc_read_resources,
299 .set_resources = pci_dev_set_resources,
300 .enable_resources = ck804_lpc_enable_resources,
302 .scan_bus = scan_static_bus,
303 // .enable = ck804_enable,
304 .ops_pci = &lops_pci,
307 static const struct pci_driver lpc_driver __pci_driver = {
309 .vendor = PCI_VENDOR_ID_NVIDIA,
310 .device = PCI_DEVICE_ID_NVIDIA_CK804_LPC,
313 static const struct pci_driver lpc_driver_pro __pci_driver = {
315 .vendor = PCI_VENDOR_ID_NVIDIA,
316 .device = PCI_DEVICE_ID_NVIDIA_CK804_PRO,
319 #if CK804_CHIP_REV == 1
320 static const struct pci_driver lpc_driver_slave __pci_driver = {
322 .vendor = PCI_VENDOR_ID_NVIDIA,
323 .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE,
326 static struct device_operations lpc_slave_ops = {
327 .read_resources = ck804_lpc_read_resources,
328 .set_resources = pci_dev_set_resources,
329 .enable_resources = pci_dev_enable_resources,
330 .init = lpc_slave_init,
331 // .enable = ck804_enable,
332 .ops_pci = &lops_pci,
335 static const struct pci_driver lpc_driver_slave __pci_driver = {
336 .ops = &lpc_slave_ops,
337 .vendor = PCI_VENDOR_ID_NVIDIA,
338 .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE,