src/southbridge/intel/i82801gx/i82801gx_pci.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <console/console.h>
  22 #include <device/device.h>
  23 #include <device/pci.h>
  24 #include <device/pci_ids.h>
  25
  26 static void pci_init(struct device *dev)
  27 {
  28         u16 reg16;
  29         u8 reg8;
  30
  31         /* Enable Bus Master */
  32         reg16 = pci_read_config16(dev, PCI_COMMAND);
  33         reg16 |= PCI_COMMAND_MASTER;
  34         pci_write_config16(dev, PCI_COMMAND, reg16);
  35
  36         /* This device has no interrupt */
  37         pci_write_config8(dev, 0x3c, 0xff);
  38
  39         /* disable parity error response and SERR */
  40         reg16 = pci_read_config16(dev, 0x3e);
  41         reg16 &= ~(1 << 0);
  42         reg16 &= ~(1 << 1);
  43         pci_write_config16(dev, 0x3e, reg16);
  44
  45         /* Master Latency Count must be set to 0x04! */
  46         reg8 = pci_read_config8(dev, 0x1b);
  47         reg8 &= 0x07;
  48         reg8 |= (0x04 << 3);
  49         pci_write_config8(dev, 0x1b, reg8);
  50
  51         /* Will this improve throughput of bus masters? */
  52         pci_write_config8(dev, PCI_MIN_GNT, 0x06);
  53
  54         /* Clear errors in status registers */
  55         reg16 = pci_read_config16(dev, 0x06);
  56         //reg16 |= 0xf900;
  57         pci_write_config16(dev, 0x06, reg16);
  58
  59         reg16 = pci_read_config16(dev, 0x1e);
  60         // reg16 |= 0xf900;
  61         pci_write_config16(dev, 0x1e, reg16);
  62 }
  63
  64 #undef PCI_BRIDGE_UPDATE_COMMAND
  65 static void ich_pci_dev_enable_resources(struct device *dev)
  66 {
  67         const struct pci_operations *ops;
  68         uint16_t command;
  69
  70         /* Set the subsystem vendor and device id for mainboard devices */
  71         ops = ops_pci(dev);
  72         if (dev->on_mainboard && ops && ops->set_subsystem) {
  73                 printk_debug("%s subsystem <- %02x/%02x\n",
  74                         dev_path(dev),
  75                         CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
  76                         CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
  77                 ops->set_subsystem(dev,
  78                         CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
  79                         CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
  80         }
  81
  82         command = pci_read_config16(dev, PCI_COMMAND);
  83         command |= dev->command;
  84 #if PCI_BRIDGE_UPDATE_COMMAND
  85         /* If we write to PCI_COMMAND, on some systems
  86          * this will cause the ROM and APICs not being visible
  87          * anymore.
  88          */
  89         printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
  90         pci_write_config16(dev, PCI_COMMAND, command);
  91 #else
  92         printk_debug("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
  93 #endif
  94 }
  95
  96 static void ich_pci_bus_enable_resources(struct device *dev)
  97 {
  98         uint16_t ctrl;
  99         /* enable IO in command register if there is VGA card
 100          * connected with (even it does not claim IO resource)
 101          */
 102         if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA)
 103                 dev->command |= PCI_COMMAND_IO;
 104         ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
 105         ctrl |= dev->link[0].bridge_ctrl;
 106         ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
 107         printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
 108         pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
 109
 110         /* This is the reason we need our own pci_bus_enable_resources */
 111         ich_pci_dev_enable_resources(dev);
 112
 113         enable_childrens_resources(dev);
 114 }
 115
 116 static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
 117 {
 118         /* NOTE: This is not the default position! */
 119         if (!vendor || !device) {
 120                 pci_write_config32(dev, 0x54,
 121                                 pci_read_config32(dev, PCI_VENDOR_ID));
 122         } else {
 123                 pci_write_config32(dev, 0x54,
 124                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 125         }
 126 }
 127
 128 static struct pci_operations pci_ops = {
 129         .set_subsystem = set_subsystem,
 130 };
 131
 132 static struct device_operations device_ops = {
 133         .read_resources         = pci_bus_read_resources,
 134         .set_resources          = pci_dev_set_resources,
 135         .enable_resources       = ich_pci_bus_enable_resources,
 136         .init                   = pci_init,
 137         .scan_bus               = pci_scan_bridge,
 138         .ops_pci                = &pci_ops,
 139 };
 140
 141 /* Desktop */
 142 /* 82801BA/CA/DB/EB/ER/FB/FR/FW/FRW/GB/GR/GDH/HB/IB/6300ESB/i3100 */
 143 static const struct pci_driver i82801g_pci __pci_driver = {
 144         .ops    = &device_ops,
 145         .vendor = PCI_VENDOR_ID_INTEL,
 146         .device = 0x244e,
 147 };
 148
 149 /* Mobile / Ultra Mobile */
 150 /* 82801BAM/CAM/DBL/DBM/FBM/GBM/GHM/GU/HBM/HEM */
 151 static const struct pci_driver i82801gmu_pci __pci_driver = {
 152         .ops    = &device_ops,
 153         .vendor = PCI_VENDOR_ID_INTEL,
 154         .device = 0x2448,
 155 };