src/southbridge/intel/i82801gx/i82801gx_lpc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <console/console.h>
  22 #include <device/device.h>
  23 #include <device/pci.h>
  24 #include <device/pci_ids.h>
  25 #include <pc80/mc146818rtc.h>
  26 #include <pc80/isa-dma.h>
  27 #include <pc80/i8259.h>
  28 #include <arch/io.h>
  29 #include "i82801gx.h"
  30
  31 #include "../../../northbridge/intel/i945/ich7.h"
  32
  33 #define MAINBOARD_POWER_OFF 0
  34 #define MAINBOARD_POWER_ON  1
  35
  36 #ifndef MAINBOARD_POWER_ON_AFTER_FAIL
  37 #define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON
  38 #endif
  39
  40 #define NMI_OFF 0
  41
  42 typedef struct southbridge_intel_i82801gx_config config_t;
  43
  44 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
  45  * 0x00 - 0000 = Reserved
  46  * 0x01 - 0001 = Reserved
  47  * 0x02 - 0010 = Reserved
  48  * 0x03 - 0011 = IRQ3
  49  * 0x04 - 0100 = IRQ4
  50  * 0x05 - 0101 = IRQ5
  51  * 0x06 - 0110 = IRQ6
  52  * 0x07 - 0111 = IRQ7
  53  * 0x08 - 1000 = Reserved
  54  * 0x09 - 1001 = IRQ9
  55  * 0x0A - 1010 = IRQ10
  56  * 0x0B - 1011 = IRQ11
  57  * 0x0C - 1100 = IRQ12
  58  * 0x0D - 1101 = Reserved
  59  * 0x0E - 1110 = IRQ14
  60  * 0x0F - 1111 = IRQ15
  61  * PIRQ[n]_ROUT[7] - PIRQ Routing Control
  62  * 0x80 - The PIRQ is not routed.
  63  */
  64
  65 #define PIRQA 0x03
  66 #define PIRQB 0x05
  67 #define PIRQC 0x06
  68 #define PIRQD 0x07
  69 #define PIRQE 0x09
  70 #define PIRQF 0x0A
  71 #define PIRQG 0x0B
  72 #define PIRQH 0x0C
  73
  74 static void i82801gx_enable_apic(struct device *dev)
  75 {
  76         int i;
  77         u32 reg32;
  78         volatile u32 *ioapic_index = (volatile u32 *)0xfec00000;
  79         volatile u32 *ioapic_data = (volatile u32 *)0xfec00010;
  80
  81         /* Enable ACPI I/O and power management. */
  82         pci_write_config8(dev, ACPI_CNTL, 0x80);
  83
  84         *ioapic_index = 0;
  85         *ioapic_data = (1 << 25);
  86
  87         *ioapic_index = 0;
  88         reg32 = *ioapic_data;
  89         printk_debug("Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
  90         if (reg32 != (1 << 25))
  91                 die("APIC Error\n");
  92
  93         printk_spew("Dumping IOAPIC registers\n");
  94         for (i=0; i<3; i++) {
  95                 *ioapic_index = i;
  96                 printk_spew("  reg 0x%04x:", i);
  97                 reg32 = *ioapic_data;
  98                 printk_spew(" 0x%08x\n", reg32);
  99         }
 100
 101         *ioapic_index = 3; /* Select Boot Configuration register. */
 102         *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
 103 }
 104
 105 static void i82801gx_enable_serial_irqs(struct device *dev)
 106 {
 107         /* Set packet length and toggle silent mode bit for one frame. */
 108         pci_write_config8(dev, SERIRQ_CNTL,
 109                           (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
 110 }
 111
 112 static void i82801gx_pirq_init(device_t dev)
 113 {
 114         device_t irq_dev;
 115         /* Get the chip configuration */
 116         config_t *config = dev->chip_info;
 117
 118         pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
 119         pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
 120         pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
 121         pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
 122
 123         pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
 124         pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
 125         pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
 126         pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
 127
 128         /* Eric Biederman once said we should let the OS do this.
 129          * I am not so sure anymore he was right.
 130          */
 131
 132         for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 133                 u8 int_pin=0, int_line=0;
 134
 135                 if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
 136                         continue;
 137
 138                 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
 139
 140                 switch (int_pin) {
 141                 case 1: /* INTA# */ int_line = config->pirqa_routing; break;
 142                 case 2: /* INTB# */ int_line = config->pirqb_routing; break;
 143                 case 3: /* INTC# */ int_line = config->pirqc_routing; break;
 144                 case 4: /* INTD# */ int_line = config->pirqd_routing; break;
 145                 }
 146
 147                 if (!int_line)
 148                         continue;
 149
 150                 pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
 151         }
 152 }
 153
 154 static void i82801gx_gpi_routing(device_t dev)
 155 {
 156         /* Get the chip configuration */
 157         config_t *config = dev->chip_info;
 158         u32 reg32 = 0;
 159
 160         /* An array would be much nicer here, or some
 161          * other method of doing this.
 162          */
 163         reg32 |= (config->gpi0_routing & 0x03) << 0;
 164         reg32 |= (config->gpi1_routing & 0x03) << 2;
 165         reg32 |= (config->gpi2_routing & 0x03) << 4;
 166         reg32 |= (config->gpi3_routing & 0x03) << 6;
 167         reg32 |= (config->gpi4_routing & 0x03) << 8;
 168         reg32 |= (config->gpi5_routing & 0x03) << 10;
 169         reg32 |= (config->gpi6_routing & 0x03) << 12;
 170         reg32 |= (config->gpi7_routing & 0x03) << 14;
 171         reg32 |= (config->gpi8_routing & 0x03) << 16;
 172         reg32 |= (config->gpi9_routing & 0x03) << 18;
 173         reg32 |= (config->gpi10_routing & 0x03) << 20;
 174         reg32 |= (config->gpi11_routing & 0x03) << 22;
 175         reg32 |= (config->gpi12_routing & 0x03) << 24;
 176         reg32 |= (config->gpi13_routing & 0x03) << 26;
 177         reg32 |= (config->gpi14_routing & 0x03) << 28;
 178         reg32 |= (config->gpi15_routing & 0x03) << 30;
 179
 180         pci_write_config32(dev, 0xb8, reg32);
 181 }
 182
 183 static void i82801gx_power_options(device_t dev)
 184 {
 185         u8 reg8;
 186         u16 reg16;
 187
 188         int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 189         int nmi_option;
 190
 191         /* Which state do we want to goto after g3 (power restored)?
 192          * 0 == S0 Full On
 193          * 1 == S5 Soft Off
 194          */
 195         get_option(&pwr_on, "power_on_after_fail");
 196         reg8 = pci_read_config8(dev, GEN_PMCON_3);
 197         reg8 &= 0xfe;
 198         if (pwr_on) {
 199                 reg8 &= ~1;
 200         } else {
 201                 reg8 |= 1;
 202         }
 203         reg8 |= (3 << 4);       /* avoid #S4 assertions */
 204         reg8 &= ~(1 << 3);      /* minimum asssertion is 1 to 2 RTCCLK */
 205
 206         pci_write_config8(dev, GEN_PMCON_3, reg8);
 207         printk_info("Set power %s after power failure.\n", pwr_on ? "on" : "off");
 208
 209         /* Set up NMI on errors. */
 210         reg8 = inb(0x61);
 211         reg8 &= 0x0f;           /* Higher Nibble must be 0 */
 212         reg8 &= ~(1 << 3);      /* IOCHK# NMI Enable */
 213         // reg8 &= ~(1 << 2);   /* PCI SERR# Enable */
 214         reg8 |= (1 << 2); /* PCI SERR# Disable for now */
 215         outb(reg8, 0x61);
 216
 217         reg8 = inb(0x70);
 218         nmi_option = NMI_OFF;
 219         get_option(&nmi_option, "nmi");
 220         if (nmi_option) {
 221                 printk_info ("NMI sources enabled.\n");
 222                 reg8 &= ~(1 << 7);      /* Set NMI. */
 223         } else {
 224                 printk_info ("NMI sources disabled.\n");
 225                 reg8 |= ( 1 << 7);      /* Can't mask NMI from PCI-E and NMI_NOW */
 226         }
 227         outb(reg8, 0x70);
 228
 229         // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down
 230         reg16 = pci_read_config16(dev, GEN_PMCON_1);
 231         reg16 &= ~((3 << 0) | (1 << 10));
 232         reg16 |= (1 << 3) | (1 << 5);
 233         reg16 |= (1 << 2); // CLKRUN_EN
 234         pci_write_config16(dev, GEN_PMCON_1, reg16);
 235
 236         // Set the board's GPI routing.
 237         i82801gx_gpi_routing(dev);
 238 }
 239
 240 static void i82801gx_configure_cstates(device_t dev)
 241 {
 242         u8 reg8;
 243
 244         reg8 = pci_read_config8(dev, 0xa9); // Cx state configuration
 245         reg8 |= (1 << 4) | (1 << 3) | (1 << 2); // Enable Popup & Popdown
 246         pci_write_config8(dev, 0xa9, reg8);
 247
 248         // Set Deeper Sleep configuration to recommended values
 249         reg8 = pci_read_config8(dev, 0xaa);
 250         reg8 &= 0xf0;
 251         reg8 |= (2 << 2);       // Deeper Sleep to Stop CPU: 34-40us
 252         reg8 |= (2 << 0);       // Deeper Sleep to Sleep: 15us
 253         pci_write_config8(dev, 0xaa, reg8);
 254 }
 255
 256 static void i82801gx_rtc_init(struct device *dev)
 257 {
 258         u8 reg8;
 259         int rtc_failed;
 260
 261         reg8 = pci_read_config8(dev, GEN_PMCON_3);
 262         rtc_failed = reg8 & RTC_BATTERY_DEAD;
 263         if (rtc_failed) {
 264                 reg8 &= ~RTC_BATTERY_DEAD;
 265                 pci_write_config8(dev, GEN_PMCON_3, reg8);
 266         }
 267         printk_debug("rtc_failed = 0x%x\n", rtc_failed);
 268
 269         rtc_init(rtc_failed);
 270 }
 271
 272 static void enable_hpet(void)
 273 {
 274         u32 reg32;
 275
 276         /* Leave HPET at default address, but enable it */
 277         reg32 = RCBA32(0x3404);
 278         reg32 |= (1 << 7); // HPET Address Enable
 279         RCBA32(0x3404) = reg32;
 280 }
 281
 282 static void enable_clock_gating(void)
 283 {
 284         u32 reg32;
 285
 286         /* Enable Clock Gating for most devices */
 287         reg32 = RCBA32(0x341c);
 288         reg32 |= (1 << 31);     // LPC clock gating
 289         reg32 |= (1 << 30);     // PATA clock gating
 290         // SATA clock gating
 291         reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
 292         reg32 |= (1 << 23);     // AC97 clock gating
 293         reg32 |= (1 << 20) | (1 << 19); // USB EHCI clock gating
 294         reg32 |= (1 << 3) | (1 << 1);   // DMI clock gating
 295         reg32 |= (1 << 2);      // PCIe clock gating;
 296         RCBA32(0x341c) = reg32;
 297 }
 298
 299 #if CONFIG_HAVE_SMI_HANDLER
 300 static void i82801gx_lock_smm(struct device *dev)
 301 {
 302         void smm_lock(void);
 303 #if TEST_SMM_FLASH_LOCKDOWN
 304         u8 reg8;
 305 #endif
 306
 307 #if ENABLE_ACPI_MODE_IN_COREBOOT
 308         printk_debug("Enabling ACPI via APMC:\n");
 309         outb(0xe1, 0xb2); // Enable ACPI mode
 310         printk_debug("done.\n");
 311 #else
 312         printk_debug("Disabling ACPI via APMC:\n");
 313         outb(0x1e, 0xb2); // Disable ACPI mode
 314         printk_debug("done.\n");
 315 #endif
 316         /* Don't allow evil boot loaders, kernels, or
 317          * userspace applications to deceive us:
 318          */
 319         smm_lock();
 320
 321 #if TEST_SMM_FLASH_LOCKDOWN
 322         /* Now try this: */
 323         printk_debug("Locking BIOS to RO... ");
 324         reg8 = pci_read_config8(dev, 0xdc);     /* BIOS_CNTL */
 325         printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
 326                         (reg8&1)?"rw":"ro");
 327         reg8 &= ~(1 << 0);                      /* clear BIOSWE */
 328         pci_write_config8(dev, 0xdc, reg8);
 329         reg8 |= (1 << 1);                       /* set BLE */
 330         pci_write_config8(dev, 0xdc, reg8);
 331         printk_debug("ok.\n");
 332         reg8 = pci_read_config8(dev, 0xdc);     /* BIOS_CNTL */
 333         printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
 334                         (reg8&1)?"rw":"ro");
 335
 336         printk_debug("Writing:\n");
 337         *(volatile u8 *)0xfff00000 = 0x00;
 338         printk_debug("Testing:\n");
 339         reg8 |= (1 << 0);                       /* set BIOSWE */
 340         pci_write_config8(dev, 0xdc, reg8);
 341
 342         reg8 = pci_read_config8(dev, 0xdc);     /* BIOS_CNTL */
 343         printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
 344                         (reg8&1)?"rw":"ro");
 345         printk_debug("Done.\n");
 346 #endif
 347 }
 348 #endif
 349
 350 #define SPIBASE 0x3020
 351 static void i82801gx_spi_init(void)
 352 {
 353         u16 spicontrol;
 354
 355         spicontrol = RCBA16(SPIBASE + 2);
 356         spicontrol &= ~(1 << 0); // SPI Access Request
 357         RCBA16(SPIBASE + 2) = spicontrol;
 358 }
 359
 360 static void i82801gx_fixups(void)
 361 {
 362         /* This needs to happen after PCI enumeration */
 363         RCBA32(0x1d40) |= 1;
 364 }
 365
 366 static void lpc_init(struct device *dev)
 367 {
 368         printk_debug("i82801gx: lpc_init\n");
 369
 370         /* Set the value for PCI command register. */
 371         pci_write_config16(dev, PCI_COMMAND, 0x000f);
 372
 373         /* IO APIC initialization. */
 374         i82801gx_enable_apic(dev);
 375
 376         i82801gx_enable_serial_irqs(dev);
 377
 378         /* Setup the PIRQ. */
 379         i82801gx_pirq_init(dev);
 380
 381         /* Setup power options. */
 382         i82801gx_power_options(dev);
 383
 384         /* Configure Cx state registers */
 385         i82801gx_configure_cstates(dev);
 386
 387         /* Set the state of the GPIO lines. */
 388         //gpio_init(dev);
 389
 390         /* Initialize the real time clock. */
 391         i82801gx_rtc_init(dev);
 392
 393         /* Initialize ISA DMA. */
 394         isa_dma_init();
 395
 396         /* Initialize the High Precision Event Timers, if present. */
 397         enable_hpet();
 398
 399         /* Initialize Clock Gating */
 400         enable_clock_gating();
 401
 402         setup_i8259();
 403
 404 #if CONFIG_HAVE_SMI_HANDLER
 405         i82801gx_lock_smm(dev);
 406 #endif
 407
 408         i82801gx_spi_init();
 409
 410         i82801gx_fixups();
 411 }
 412
 413 static void i82801gx_lpc_read_resources(device_t dev)
 414 {
 415         struct resource *res;
 416
 417         /* Get the normal PCI resources of this device. */
 418         pci_dev_read_resources(dev);
 419
 420         /* Add an extra subtractive resource for both memory and I/O. */
 421         res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
 422         res->flags =
 423             IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 424
 425         res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
 426         res->flags =
 427             IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 428 }
 429
 430 static void i82801gx_lpc_enable_resources(device_t dev)
 431 {
 432         pci_dev_enable_resources(dev);
 433         enable_childrens_resources(dev);
 434 }
 435
 436 static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
 437 {
 438         if (!vendor || !device) {
 439                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 440                                 pci_read_config32(dev, PCI_VENDOR_ID));
 441         } else {
 442                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 443                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 444         }
 445 }
 446
 447 static struct pci_operations pci_ops = {
 448         .set_subsystem = set_subsystem,
 449 };
 450
 451 static struct device_operations device_ops = {
 452         .read_resources         = i82801gx_lpc_read_resources,
 453         .set_resources          = pci_dev_set_resources,
 454         .enable_resources       = i82801gx_lpc_enable_resources,
 455         .init                   = lpc_init,
 456         .scan_bus               = scan_static_bus,
 457         .enable                 = i82801gx_enable,
 458         .ops_pci                = &pci_ops,
 459 };
 460
 461 /* 82801GB/GR (ICH7/ICH7R) */
 462 static const struct pci_driver ich7_ich7r_lpc __pci_driver = {
 463         .ops    = &device_ops,
 464         .vendor = PCI_VENDOR_ID_INTEL,
 465         .device = 0x27b8,
 466 };
 467
 468 /* 82801GBM/GU (ICH7-M/ICH7-U) */
 469 static const struct pci_driver ich7m_ich7u_lpc __pci_driver = {
 470         .ops    = &device_ops,
 471         .vendor = PCI_VENDOR_ID_INTEL,
 472         .device = 0x27b9,
 473 };
 474
 475 /* 82801GHM (ICH7-M DH) */
 476 static const struct pci_driver ich7m_dh_lpc __pci_driver = {
 477         .ops    = &device_ops,
 478         .vendor = PCI_VENDOR_ID_INTEL,
 479         .device = 0x27bd,
 480 };