1 #include "i82801ex_smbus.h"
3 #define SMBUS_IO_BASE 0x0f00
5 static void enable_smbus(void)
7 device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
9 print_spew("SMBus controller enabled\n");
11 pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
12 print_debug_hex32(pci_read_config32(dev, 0x20));
13 /* Set smbus enable */
14 pci_write_config8(dev, 0x40, 1);
15 /* Set smbus iospace enable */
16 pci_write_config8(dev, 0x4, 1);
18 pci_write_config8(dev, 0x11, 4);
20 /* Disable interrupt generation */
21 outb(0, SMBUS_IO_BASE + SMBHSTCTL);
23 /* clear any lingering errors, so the transaction will run */
24 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
27 static int smbus_read_byte(unsigned device, unsigned address)
29 return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
32 static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
34 if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
38 print_debug("Unimplemented smbus_write_byte() called.\n");
41 /* setup transaction */
42 /* disable interrupts */
43 outw(inw(SMBUS_IO_BASE + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)),
44 SMBUS_IO_BASE + SMBGCTL);
45 /* set the device I'm talking too */
46 outw(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADDR);
47 outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
48 /* set up for a byte data write */ /* FIXME */
49 outw((inw(SMBUS_IO_BASE + SMBGCTL) & ~7) | (0x1), SMBUS_IO_BASE + SMBGCTL);
50 /* clear any lingering errors, so the transaction will run */
51 /* Do I need to write the bits to a 1 to clear an error? */
52 outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
54 /* clear the data word...*/
55 outw(val, SMBUS_IO_BASE + SMBHSTDAT);
57 /* start the command */
58 outw((inw(SMBUS_IO_BASE + SMBGCTL) | (1 << 3)), SMBUS_IO_BASE + SMBGCTL);
60 /* poll for transaction completion */
61 smbus_wait_until_done(SMBUS_IO_BASE);
66 static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
67 unsigned data1, unsigned data2)
73 /* chear the PM timeout flags, SECOND_TO_STS */
74 outw(inw(0x0400 + 0x66), 0x0400 + 0x66);
76 if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
80 /* setup transaction */
81 /* Obtain ownership */
82 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
83 for(stat=0;(stat&0x40)==0;) {
84 stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
86 /* clear the done bit */
87 outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT);
88 /* disable interrupts */
89 outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
91 /* set the device I'm talking too */
92 outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD);
94 /* set the command address */
95 outb(cmd & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
97 /* set the block length */
98 outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0);
100 /* try sending out the first byte of data here */
101 byte=(data1>>(0))&0x0ff;
102 outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
103 /* issue a block write command */
104 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40,
105 SMBUS_IO_BASE + SMBHSTCTL);
107 for(i=0;i<length;i++) {
109 /* poll for transaction completion */
110 if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
114 /* load the next byte */
116 byte=(data2>>(i%4))&0x0ff;
118 byte=(data1>>(i))&0x0ff;
119 outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
121 /* clear the done bit */
122 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
123 SMBUS_IO_BASE + SMBHSTSTAT);
126 print_debug("SMBUS Block complete\n");