1 #include <device/pci_ids.h>
4 static void enable_smbus(void)
7 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_SMB), 0);
8 if (dev == PCI_DEV_INVALID) {
9 die("SMBUS controller not found\r\n");
12 print_debug("SMBus controller enabled\r\n");
13 /* set smbus iobase */
14 pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
15 /* Set smbus enable */
16 pci_write_config8(dev, HOSTC, HST_EN);
17 /* Set smbus iospace enable */
18 pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
19 /* Disable interrupt generation */
20 outb(0, SMBUS_IO_BASE + SMBHSTCTL);
21 /* clear any lingering errors, so the transaction will run */
22 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
26 static inline void smbus_delay(void)
31 // See http://www.coreboot.org/pipermail/linuxbios/2004-September/009077.html
32 // for a description of this function.
33 static int smbus_wait_until_active(void)
36 loops = SMBUS_TIMEOUT;
40 val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
45 return loops ? 0 : -4;
48 static int smbus_wait_until_ready(void)
51 loops = SMBUS_TIMEOUT;
55 val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
60 if(loops == (SMBUS_TIMEOUT / 2)) {
62 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT),
63 SMBUS_IO_BASE + SMBHSTSTAT);
69 static int smbus_wait_until_done(void)
72 loops = SMBUS_TIMEOUT;
77 val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
79 if ( (val & 1) == 0) {
82 // BYTE_DONE or SUCCESS or error?
83 if ((val & ~((1<<6)|(1<<0)) ) != 0 ) {
90 static int smbus_read_byte(unsigned device, unsigned address)
92 unsigned char global_control_register;
93 unsigned char global_status_register;
96 if (smbus_wait_until_ready() < 0) {
100 /* setup transaction */
101 /* disable interrupts */
102 outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL);
103 /* set to read from the specified device */
104 outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
105 /* set the command/address... */
106 outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
107 /* set up for a byte data read */
108 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2<<2), SMBUS_IO_BASE + SMBHSTCTL);
110 /* clear any lingering errors, so the transaction will run */
111 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
113 /* clear the data byte...*/
114 outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
116 /* start a byte read, with interrupts disabled */
117 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
118 /* poll for it to start */
119 if (smbus_wait_until_active() < 0) {
123 /* poll for transaction completion */
124 if (smbus_wait_until_done() < 0) {
128 global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~(1<<6); /* Ignore the In Use Status... */
130 /* read results of transaction */
131 byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
134 if (global_status_register != 2) {