2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Arastra, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <device/device.h>
23 #include <device/pci.h>
26 void i3100_enable(device_t dev)
30 volatile u32 *disable;
36 * To disable an integrated southbridge device, set the corresponding
37 * flag in the Function Disable register.
40 /* Temporarily enable the root complex register block at 0xa0000000. */
41 lpc_dev = dev_find_slot(0x0, PCI_DEVFN(0x1f, 0x0));
42 pci_write_config32(lpc_dev, 0xf0, 0xa0000000 | (1 << 0));
43 disable = (volatile u32 *) 0xa0003418;
44 func = PCI_FUNC(dev->path.pci.devfn);
45 switch (PCI_SLOT(dev->path.pci.devfn)) {
46 case 0x1f: /* LPC (fn0), SATA (fn2), SMBus (fn3) */
47 *disable |= (1 << (func == 0x0 ? 14 : func));
49 case 0x1d: /* UHCI (fn0, fn1), EHCI (fn7) */
50 *disable |= (1 << (func + 8));
52 case 0x1c: /* PCIe ports B0-B3 (fn0-fn3) */
53 *disable |= (1 << (func + 16));
56 /* Disable the root complex register block. */
57 pci_write_config32(lpc_dev, 0xf0, 0);
60 struct chip_operations southbridge_intel_i3100_ops = {
61 CHIP_NAME("Intel 3100 Southbridge")