2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 * for rs780 internal graphics device
22 * device id of internal grphics:
28 * RS785G: 0x9710 - just works, not much tested
30 #include <console/console.h>
31 #include <device/device.h>
32 #include <device/pci.h>
33 #include <device/pci_ids.h>
34 #include <device/pci_ops.h>
36 #include <cpu/x86/msr.h>
38 extern int is_dev3_present(void);
39 void set_pcie_reset(void);
40 void set_pcie_dereset(void);
42 extern uint64_t uma_memory_base, uma_memory_size;
44 /* Trust the original resource allocation. Don't do it again. */
45 #undef DONT_TRUST_RESOURCE_ALLOCATION
46 //#define DONT_TRUST_RESOURCE_ALLOCATION
48 #define CLK_CNTL_INDEX 0x8
49 #define CLK_CNTL_DATA 0xC
51 /* The Integrated Info Table. */
52 ATOM_INTEGRATED_SYSTEM_INFO_V2 vgainfo;
55 static u32 clkind_read(device_t dev, u32 index)
57 u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
59 *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index & 0x7F;
60 return *(u32*)(gfx_bar2+CLK_CNTL_DATA);
64 static void clkind_write(device_t dev, u32 index, u32 data)
66 u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
67 /* printk(BIOS_DEBUG, "gfx bar 2 %02x\n", gfx_bar2); */
69 *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7;
70 *(u32*)(gfx_bar2+CLK_CNTL_DATA) = data;
74 * pci_dev_read_resources thinks it is a IO type.
75 * We have to force it to mem type.
77 static void rs780_gfx_read_resources(device_t dev)
79 printk(BIOS_DEBUG, "rs780_gfx_read_resources.\n");
81 /* The initial value of 0x24 is 0xFFFFFFFF, which is confusing.
82 Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000,
83 which tells us it is a memory address base.
85 pci_write_config32(dev, 0x24, 0x00000000);
87 /* Get the normal pci resources of this device */
88 pci_dev_read_resources(dev);
89 compact_resources(dev);
92 typedef struct _MMIORANGE
99 MMIORANGE MMIO[8], CreativeMMIO[8];
101 #define CIM_STATUS u32
102 #define CIM_SUCCESS 0x00000000
103 #define CIM_ERROR 0x80000000
104 #define CIM_UNSUPPORTED 0x80000001
105 #define CIM_DISABLEPORT 0x80000002
107 #define MMIO_ATTRIB_NP_ONLY 1
108 #define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1
109 #define MMIO_ATTRIB_SKIP_ZERO 1<<2
111 #ifdef DONT_TRUST_RESOURCE_ALLOCATION
112 static MMIORANGE* AllocMMIO(MMIORANGE* pMMIO)
115 for (i=0; i<8; i++) {
116 if (pMMIO[i].Limit == 0)
122 static void FreeMMIO(MMIORANGE* pMMIO)
128 static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
131 MMIORANGE * TempRange;
134 if(pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit)
136 TempRange = AllocMMIO(pMMIO);
137 if(TempRange == 0) return 0x80000000;
138 TempRange->Base = Limit;
139 TempRange->Limit = pMMIO[i].Limit;
140 TempRange->Attribute = pMMIO[i].Attribute;
141 pMMIO[i].Limit = Base;
144 TempRange = AllocMMIO(pMMIO);
145 if(TempRange == 0) return 0x80000000;
146 TempRange->Base = Base;
147 TempRange->Limit = Limit;
148 TempRange->Attribute = Attribute;
152 static u8 FinalizeMMIO(MMIORANGE *pMMIO)
157 if (pMMIO[i].Base == pMMIO[i].Limit)
164 if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute)
166 if (pMMIO[i].Base == pMMIO[j].Limit)
168 pMMIO[j].Limit = pMMIO[i].Limit;
171 if (pMMIO[i].Limit == pMMIO[j].Base)
173 pMMIO[j].Base = pMMIO[i].Base;
181 if (pMMIO[i].Limit != 0) n++;
186 static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
188 CIM_STATUS Status = CIM_UNSUPPORTED;
189 u8 Bus, Dev, Reg, BusStart, BusEnd;
191 device_t dev0x14 = dev_find_slot(0, PCI_DEVFN(0x14, 4));
193 Value = pci_read_config32(dev0x14, 0x18);
194 BusStart = (Value >> 8) & 0xFF;
195 BusEnd = (Value >> 16) & 0xFF;
196 for(Bus = BusStart; Bus <= BusEnd; Bus++)
198 for(Dev = 0; Dev <= 0x1f; Dev++)
200 tempdev = dev_find_slot(Bus, Dev << 3);
201 Value = pci_read_config32(tempdev, 0);
202 printk(BIOS_DEBUG, "Dev ID %x \n", Value);
203 if((Value & 0xffff) == 0x1102)
206 u32 MMIOStart = 0xffffffff;
208 for(Reg = 0x10; Reg < 0x20; Reg+=4)
211 BaseA = pci_read_config32(tempdev, Reg);
215 Value = Value & 0xffffff00;
218 if(MMIOStart > Value)
221 //WritePCI(PciAddress,AccWidthUint32,&LimitA);
222 pci_write_config32(tempdev, Reg, LimitA);
223 //ReadPCI(PciAddress,AccWidthUint32,&LimitA);
224 LimitA = pci_read_config32(tempdev, Reg);
225 LimitA = Value + (~LimitA + 1);
226 //WritePCI(PciAddress,AccWidthUint32,&BaseA);
227 pci_write_config32(tempdev, Reg, BaseA);
228 if (LimitA > MMIOLimit)
233 printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit);
234 if (MMIOStart < MMIOLimit)
236 Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO);
237 if(Status == CIM_ERROR) return Status;
242 if(Status == CIM_SUCCESS)
245 if(FinalizeMMIO(pMMIO) > 4)
254 static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
259 k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
261 for(i = 0; i < 8; i++)
266 for(j = 0; j < 8; j++)
268 if (Base < pMMIO[j].Base)
270 Base = pMMIO[j].Base;
274 if(pMMIO[k].Limit != 0)
276 if(Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 )
282 Base = pMMIO[k].Base | 0x3;
283 Limit= ((pMMIO[k].Limit - 1) & 0xffffff00) | pMMIO[k].Attribute | (LinkID << 4);
287 if (Attribute & MMIO_ATTRIB_SKIP_ZERO && Base == 0 && Limit == 0) continue;
288 MmioReg = (Attribute & MMIO_ATTRIB_BOTTOM_TO_TOP)?n:(7-n);
290 //RWPCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x80+MmioReg*8),AccWidthUint32 |S3_SAVE,0x0,0x0);
291 pci_write_config32(k8_f1, 0x80+MmioReg*8, 0);
293 //WritePCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x84+MmioReg*8),AccWidthUint32 |S3_SAVE,&Limit);
294 pci_write_config32(k8_f1, 0x84+MmioReg*8, Limit);
296 //WritePCI(PCI_ADDRESS(0,CPU_DEV,CPU_F1,0x80+MmioReg*8),AccWidthUint32 |S3_SAVE,&Base);
297 pci_write_config32(k8_f1, 0x80+MmioReg*8, Base);
302 static void internal_gfx_pci_dev_init(struct device *dev)
304 unsigned char * bpointer;
305 volatile u32 * GpuF0MMReg;
306 volatile u32 * pointer;
310 u16 deviceid, vendorid;
311 device_t nb_dev = dev_find_slot(0, 0);
312 device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
313 device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
314 static const u8 ht_freq_lookup [] = {2, 0, 4, 0, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 0, 0, 28, 30, 32};
315 static const u8 ht_width_lookup [] = {8, 16, 0, 0, 2, 4, 0, 0};
316 static const u16 memclk_lookup_fam0F [] = {100, 0, 133, 0, 0, 166, 0, 200};
317 static const u16 memclk_lookup_fam10 [] = {200, 266, 333, 400, 533, 667, 800, 800};
319 /* We definetely will use this in future. Just leave it here. */
320 /*struct southbridge_amd_rs780_config *cfg =
321 (struct southbridge_amd_rs780_config *)dev->chip_info;*/
323 deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
324 vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
325 printk(BIOS_DEBUG, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
328 command = pci_read_config16(dev, 0x04);
330 pci_write_config16(dev, 0x04, command);
333 bpointer = (unsigned char *) &vgainfo;
334 for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++)
340 GpuF0MMReg = (u32 *)pci_read_config32(dev, 0x18);
342 /* GFX_InitFBAccess. */
343 value = nbmc_read_index(nb_dev, 0x10);
344 *(GpuF0MMReg + 0x2000/4) = 0x11;
345 *(GpuF0MMReg + 0x2180/4) = ((value&0xff00)>>8)|((value&0xff000000)>>8);
346 *(GpuF0MMReg + 0x2c04/4) = ((value&0xff00)<<8);
347 *(GpuF0MMReg + 0x5428/4) = ((value&0xffff0000)+0x10000)-((value&0xffff)<<16);
348 *(GpuF0MMReg + 0xF774/4) = 0xffffffff;
349 *(GpuF0MMReg + 0xF770/4) = 0x00000001;
350 *(GpuF0MMReg + 0x2000/4) = 0x00000011;
351 *(GpuF0MMReg + 0x200c/4) = 0x00000020;
352 *(GpuF0MMReg + 0x2010/4) = 0x10204810;
353 *(GpuF0MMReg + 0x2010/4) = 0x00204810;
354 *(GpuF0MMReg + 0x2014/4) = 0x10408810;
355 *(GpuF0MMReg + 0x2014/4) = 0x00408810;
356 *(GpuF0MMReg + 0x2414/4) = 0x00000080;
357 *(GpuF0MMReg + 0x2418/4) = 0x84422415;
358 *(GpuF0MMReg + 0x2418/4) = 0x04422415;
359 *(GpuF0MMReg + 0x5490/4) = 0x00000001;
360 *(GpuF0MMReg + 0x7de4/4) |= (1<<3) | (1<<4);
361 /* Force allow LDT_STOP Cool'n'Quiet workaround. */
362 *(GpuF0MMReg + 0x655c/4) |= 1<<4;
364 // disable write combining, needed for stability
365 // reference bios does this only for RS780 rev A11
366 // need to figure out why we need it for all revs
367 *(GpuF0MMReg + 0x2000/4) = 0x00000010;
368 *(GpuF0MMReg + 0x2408/4) = 1 << 9;
369 *(GpuF0MMReg + 0x2000/4) = 0x00000011;
371 /* GFX_InitFBAccess finished. */
373 #if (CONFIG_GFXUMA == 1) /* for UMA mode. */
375 set_nbmc_enable_bits(nb_dev, 0x02, 0x00000000, 0x80000000);
376 set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000001);
377 set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000004);
378 set_nbmc_enable_bits(nb_dev, 0x01, 0x00040000, 0x00000000);
379 set_nbmc_enable_bits(nb_dev, 0xB1, 0xFFFF0000, 0x00000040);
380 set_nbmc_enable_bits(nb_dev, 0xC3, 0x00000000, 0x00000001);
381 set_nbmc_enable_bits(nb_dev, 0x07, 0xFFFFFFFF, 0x00000018);
382 set_nbmc_enable_bits(nb_dev, 0x06, 0xFFFFFFFF, 0x00000102);
383 set_nbmc_enable_bits(nb_dev, 0x09, 0xFFFFFFFF, 0x40000008);
384 set_nbmc_enable_bits(nb_dev, 0x06, 0x00000000, 0x80000000);
385 /* GFX_StartMC finished. */
388 set_nbmc_enable_bits(nb_dev, 0xaa, 0xf0, 0x30);
389 set_nbmc_enable_bits(nb_dev, 0xce, 0xf0, 0x30);
390 set_nbmc_enable_bits(nb_dev, 0xca, 0xff000000, 0x47000000);
391 set_nbmc_enable_bits(nb_dev, 0xcb, 0x3f000000, 0x01000000);
392 set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<0);
393 set_nbmc_enable_bits(nb_dev, 0x04, 0, 1<<31);
394 set_nbmc_enable_bits(nb_dev, 0xb4, 0x3f, 0x3f);
395 set_nbmc_enable_bits(nb_dev, 0xb4, 0, 1<<6);
396 set_nbmc_enable_bits(nb_dev, 0xc3, 1<<11, 0);
397 set_nbmc_enable_bits(nb_dev, 0xa0, 1<<29, 0);
398 nbmc_write_index(nb_dev, 0xa4, 0x3484576f);
399 nbmc_write_index(nb_dev, 0xa5, 0x222222df);
400 nbmc_write_index(nb_dev, 0xa6, 0x00000000);
401 nbmc_write_index(nb_dev, 0xa7, 0x00000000);
402 set_nbmc_enable_bits(nb_dev, 0xc3, 1<<8, 0);
404 set_nbmc_enable_bits(nb_dev, 0xc3, 1<<9, 0);
406 set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<2);
408 set_nbmc_enable_bits(nb_dev, 0x01, 0, 1<<3);
409 set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<31);
411 set_nbmc_enable_bits(nb_dev, 0x02, 0, 1<<31);
412 set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<30);
413 set_nbmc_enable_bits(nb_dev, 0xa0, 1<<31, 0);
414 set_nbmc_enable_bits(nb_dev, 0xa0, 0, 1<<29);
415 nbmc_write_index(nb_dev, 0xa4, 0x23484576);
416 nbmc_write_index(nb_dev, 0xa5, 0x00000000);
417 nbmc_write_index(nb_dev, 0xa6, 0x00000000);
418 nbmc_write_index(nb_dev, 0xa7, 0x00000000);
419 /* GFX_StartMC finished. */
421 /* GFX_SPPowerManagment, don't care for new. */
422 /* Post MC Init table programming. */
423 set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b);
425 /* Do we need Write and Read Calibration? */
426 /* GFX_Init finished. */
429 /* GFX_InitIntegratedInfo. */
430 /* fill the Integrated Info Table. */
431 vgainfo.sHeader.usStructureSize = sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2);
432 vgainfo.sHeader.ucTableFormatRevision = 1;
433 vgainfo.sHeader.ucTableContentRevision = 2;
435 #if (CONFIG_GFXUMA == 0) /* SP mode. */
436 // Side port support is incomplete, do not use it
437 // These parameters must match the motherboard
438 vgainfo.ulBootUpSidePortClock = 667*100;
439 vgainfo.ucMemoryType = 3; // 3=ddr3 sp mem, 2=ddr2 sp mem
440 vgainfo.ulMinSidePortClock = 333*100;
443 vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default
445 // find the DDR memory frequency
446 if (is_family10h()) {
447 value = pci_read_config32(k8_f2, 0x94); // read channel 0 DRAM Configuration High Register
448 if (extractbit(value, 14)) // if channel 0 disabled, channel 1 must have memory
449 value = pci_read_config32(k8_f2, 0x194);// read channel 1 DRAM Configuration High Register
450 vgainfo.ulBootUpUMAClock = memclk_lookup_fam10 [extractbits (value, 0, 2)] * 100;
452 if (is_family0Fh()) {
453 value = pci_read_config32(k8_f2, 0x94);
454 vgainfo.ulBootUpUMAClock = memclk_lookup_fam0F [extractbits (value, 20, 22)] * 100;
457 /* UMA Channel Number: 1 or 2. */
458 vgainfo.ucUMAChannelNumber = 1;
459 if (is_family0Fh()) {
460 value = pci_read_config32(k8_f2, 0x90);
461 if (extractbit(value, 11)) // 128-bit mode
462 vgainfo.ucUMAChannelNumber = 2;
464 if (is_family10h()) {
465 u32 dch0 = pci_read_config32(k8_f2, 0x94);
466 u32 dch1 = pci_read_config32(k8_f2, 0x194);
467 if (extractbit(dch0, 14) == 0 && extractbit(dch1, 14) == 0) { // both channels enabled
468 value = pci_read_config32(k8_f2, 0x110);
469 if (extractbit(value, 4)) // ganged mode
470 vgainfo.ucUMAChannelNumber = 2;
476 vgainfo.ulCPUCapInfo = 3;
478 vgainfo.ulCPUCapInfo = 2;
481 value = pci_read_config8(nb_dev, 0xd1);
482 value = ht_freq_lookup [value] * 100; // HT link frequency in MHz
483 vgainfo.ulHTLinkFreq = value * 100; // HT frequency in units of 100 MHz
484 vgainfo.ulHighVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
485 vgainfo.ulLowVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
488 vgainfo.ulLowVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
490 int sblink, cpuLnkFreqCap, nbLnkFreqCap;
491 value = pci_read_config32(k8_f0, 0x64);
492 sblink = extractbits(value, 8, 10);
493 cpuLnkFreqCap = pci_read_config16(k8_f0, 0x8a + sblink * 0x20);
494 nbLnkFreqCap = pci_read_config16(nb_dev, 0xd2);
495 if (cpuLnkFreqCap & nbLnkFreqCap & (1 << 10)) // if both 1800 MHz capable
496 vgainfo.ulLowVoltageHTLinkFreq = 1800*100;
500 value = pci_read_config8(nb_dev, 0xcb);
501 vgainfo.usMinDownStreamHTLinkWidth =
502 vgainfo.usMaxDownStreamHTLinkWidth =
503 vgainfo.usMinUpStreamHTLinkWidth =
504 vgainfo.usMaxUpStreamHTLinkWidth =
505 vgainfo.usMinHTLinkWidth =
506 vgainfo.usMaxHTLinkWidth = ht_width_lookup [extractbits(value, 0, 2)];
508 if (is_family0Fh()) {
509 vgainfo.usUMASyncStartDelay = 322;
510 vgainfo.usUMADataReturnTime = 286;
513 if (is_family10h()) {
514 static u16 t0mult_lookup [] = {10, 50, 200, 2000};
516 value = pci_read_config32(k8_f0, 0x16c);
517 t0time = extractbits(value, 0, 3);
518 t0scale = extractbits(value, 4, 5);
519 vgainfo.usLinkStatusZeroTime = t0mult_lookup [t0scale] * t0time;
520 vgainfo.usUMASyncStartDelay = 100;
521 if (vgainfo.ulHTLinkFreq < 1000 * 100) { // less than 1000 MHz
522 vgainfo.usUMADataReturnTime = 300;
523 vgainfo.usLinkStatusZeroTime = 6 * 100; // 6us for GH in HT1 mode
527 value = pci_read_config32(nb_dev, 0xac);
528 lssel = extractbits (value, 7, 8);
529 vgainfo.usUMADataReturnTime = 1300;
530 if (lssel == 0) vgainfo.usUMADataReturnTime = 150;
534 /* Transfer the Table to VBIOS. */
535 pointer = (u32 *)&vgainfo;
536 for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4)
538 #if (CONFIG_GFXUMA == 1)
539 *GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i;
541 *GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i;
543 *(GpuF0MMReg+1) = *pointer++;
549 temp = pci_read_config8(dev, 0x4);
550 //temp &= ~1; /* CIM clears this bit. Strangely, I can'd. */
552 pci_write_config8(dev, 0x4, temp);
554 // if the GFX debug bar is writable, then it has
555 // been programmed and can be safely enabled now
556 temp = pci_read_config32(nb_dev, 0x8c);
558 // if bits 1 (intgfx_enable) and 9 (gfx_debug_bar_enable)
559 // then enable gfx debug bar (set gxf_debug_decode_enable)
562 pci_write_config32(nb_dev, 0x8c, temp);
566 #ifdef DONT_TRUST_RESOURCE_ALLOCATION
567 /* NB_SetupMGMMIO. */
569 /* clear MMIO and CreativeMMIO. */
570 bpointer = (unsigned char *)MMIO;
571 for(i=0; i<sizeof(MMIO); i++)
576 bpointer = (unsigned char *)CreativeMMIO;
577 for(i=0; i<sizeof(CreativeMMIO); i++)
583 /* Set MMIO ranges in K8. */
584 /* Set MMIO TOM - 4G. */
585 SetMMIO(0x400<<12, 0x1000000, 0x80, &MMIO[0]);
586 /* Set MMIO for VGA Legacy FB. */
587 SetMMIO(0xa00, 0xc00, 0x80, &MMIO[0]);
589 /* Set MMIO for non prefetchable P2P. */
590 temp = pci_read_config32(dev0x14, 0x20);
591 Base32 = (temp & 0x0fff0) << 8;
592 Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
595 Status = GetCreativeMMIO(&CreativeMMIO[0]);
596 if(Status != CIM_ERROR)
597 SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
599 /* Set MMIO for prefetchable P2P. */
600 if(Status != CIM_ERROR)
602 temp = pci_read_config32(dev0x14, 0x24);
604 Base32 = (temp & 0x0fff0) <<8;
605 Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
607 SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
610 FinalizeMMIO(&MMIO[0]);
612 ProgramMMIO(&CreativeMMIO[0], 0, MMIO_ATTRIB_NP_ONLY);
613 ProgramMMIO(&MMIO[0], 0, MMIO_ATTRIB_NP_ONLY | MMIO_ATTRIB_BOTTOM_TO_TOP | MMIO_ATTRIB_SKIP_ZERO);
619 clkind_write(dev, 0x08, 0x01);
620 clkind_write(dev, 0x0C, 0x22);
621 clkind_write(dev, 0x0F, 0x0);
622 clkind_write(dev, 0x11, 0x0);
623 clkind_write(dev, 0x12, 0x0);
624 clkind_write(dev, 0x14, 0x0);
625 clkind_write(dev, 0x15, 0x0);
626 clkind_write(dev, 0x16, 0x0);
627 clkind_write(dev, 0x17, 0x0);
628 clkind_write(dev, 0x18, 0x0);
629 clkind_write(dev, 0x19, 0x0);
630 clkind_write(dev, 0x1A, 0x0);
631 clkind_write(dev, 0x1B, 0x0);
632 clkind_write(dev, 0x1C, 0x0);
633 clkind_write(dev, 0x1D, 0x0);
634 clkind_write(dev, 0x1E, 0x0);
635 clkind_write(dev, 0x26, 0x0);
636 clkind_write(dev, 0x27, 0x0);
637 clkind_write(dev, 0x28, 0x0);
638 clkind_write(dev, 0x5C, 0x0);
643 * Set registers in RS780 and CPU to enable the internal GFX.
644 * Please refer to CIM source code and BKDG.
647 static void rs780_internal_gfx_enable(device_t dev)
651 device_t nb_dev = dev_find_slot(0, 0);
654 #if (CONFIG_GFXUMA == 0)
655 u32 FB_Start, FB_End;
658 printk(BIOS_DEBUG, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev);
660 sysmem = rdmsr(0xc001001a);
661 printk(BIOS_DEBUG, "sysmem = %x_%x\n", sysmem.hi, sysmem.lo);
663 /* The system top memory in 780. */
664 pci_write_config32(nb_dev, 0x90, sysmem.lo);
665 htiu_write_index(nb_dev, 0x30, 0);
666 htiu_write_index(nb_dev, 0x31, 0);
668 /* Disable external GFX and enable internal GFX. */
669 l_dword = pci_read_config32(nb_dev, 0x8c);
672 pci_write_config32(nb_dev, 0x8c, l_dword);
674 /* NB_SetDefaultIndexes */
675 pci_write_config32(nb_dev, 0x94, 0x7f);
676 pci_write_config32(nb_dev, 0x60, 0x7f);
677 pci_write_config32(nb_dev, 0xe0, 0);
679 /* NB_InitEarlyNB finished. */
681 /* LPC DMA Deadlock workaround? */
683 device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
684 l_dword = pci_read_config32(k8_f0, 0x68);
685 l_dword &= ~(3 << 21);
686 l_dword |= (1 << 21);
687 pci_write_config32(k8_f0, 0x68, l_dword);
689 /* GFX_InitCommon. */
690 nbmc_write_index(nb_dev, 0x23, 0x00c00010);
691 set_nbmc_enable_bits(nb_dev, 0x16, 1<<15, 1<<15);
692 set_nbmc_enable_bits(nb_dev, 0x25, 0xffffffff, 0x111f111f);
693 set_htiu_enable_bits(nb_dev, 0x37, 1<<24, 1<<24);
695 #if (CONFIG_GFXUMA == 1)
697 /* Copy CPU DDR Controller to NB MC. */
698 device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
699 device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
700 device_t k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4));
701 for (i = 0; i < 12; i++)
703 l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
704 nbmc_write_index(nb_dev, 0x30 + i, l_dword);
707 l_dword = pci_read_config32(k8_f2, 0x80);
708 nbmc_write_index(nb_dev, 0x3c, l_dword);
709 l_dword = pci_read_config32(k8_f2, 0x94);
710 set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<22))<<16);
711 set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<< 8))<<17);
712 l_dword = pci_read_config32(k8_f2, 0x90);
713 set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<10))<<18);
716 for (i = 0; i < 12; i++)
718 l_dword = pci_read_config32(k8_f2, 0x140 + i * 4);
719 nbmc_write_index(nb_dev, 0x3d + i, l_dword);
722 l_dword = pci_read_config32(k8_f2, 0x180);
723 nbmc_write_index(nb_dev, 0x49, l_dword);
724 l_dword = pci_read_config32(k8_f2, 0x194);
725 set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<<22))<<16);
726 set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<< 8))<<17);
727 l_dword = pci_read_config32(k8_f2, 0x190);
728 set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<<10))<<18);
730 l_dword = pci_read_config32(k8_f2, 0x110);
731 nbmc_write_index(nb_dev, 0x4a, l_dword);
732 l_dword = pci_read_config32(k8_f2, 0x114);
733 nbmc_write_index(nb_dev, 0x4b, l_dword);
734 l_dword = pci_read_config32(k8_f4, 0x44);
735 set_nbmc_enable_bits(nb_dev, 0x4a, 0, !!(l_dword & (1<<22))<<24);
736 l_dword = pci_read_config32(k8_f1, 0x40);
737 nbmc_write_index(nb_dev, 0x4c, l_dword);
738 l_dword = pci_read_config32(k8_f1, 0xf0);
739 nbmc_write_index(nb_dev, 0x4d, l_dword);
743 /* Set UMA in the 780 side. */
744 /* UMA start address, size. */
745 /* The UMA starts at 0xC0000000 of internal RS780 address space
746 [31:16] addr of last byte | [31:16] addr of first byte
748 nbmc_write_index(nb_dev, 0x10, ((uma_memory_size - 1 + 0xC0000000) & (~0xffff)) | 0xc000);
749 nbmc_write_index(nb_dev, 0x11, uma_memory_base);
750 nbmc_write_index(nb_dev, 0x12, 0);
751 nbmc_write_index(nb_dev, 0xf0, uma_memory_size >> 20);
752 /* GFX_InitUMA finished. */
755 /* SP memory:Hynix HY5TQ1G631ZNFP. 128MB = 64M * 16. 667MHz. DDR3. */
757 /* Enable Async mode. */
758 set_nbmc_enable_bits(nb_dev, 0x06, 7<<8, 1<<8);
759 set_nbmc_enable_bits(nb_dev, 0x08, 1<<10, 0);
760 /* The last item in AsynchMclkTaskFileIndex. Why? */
761 /* MC_MPLL_CONTROL2. */
762 nbmc_write_index(nb_dev, 0x07, 0x40100028);
763 /* MC_MPLL_DIV_CONTROL. */
764 nbmc_write_index(nb_dev, 0x0b, 0x00000028);
765 /* MC_MPLL_FREQ_CONTROL. */
766 set_nbmc_enable_bits(nb_dev, 0x09, 3<<12|15<<16|15<<8, 1<<12|4<<16|0<<8);
767 /* MC_MPLL_CONTROL3. For PM. */
768 set_nbmc_enable_bits(nb_dev, 0x08, 0xff<<13, 1<<13|1<<18);
769 /* MPLL_CAL_TRIGGER. */
770 set_nbmc_enable_bits(nb_dev, 0x06, 0, 1<<0);
771 udelay(200); /* time is long enough? */
772 set_nbmc_enable_bits(nb_dev, 0x06, 0, 1<<1);
773 set_nbmc_enable_bits(nb_dev, 0x06, 1<<0, 0);
774 /* MCLK_SRC_USE_MPLL. */
775 set_nbmc_enable_bits(nb_dev, 0x02, 0, 1<<20);
778 nbmc_write_index(nb_dev, 0x01, 0x88108280);
779 set_nbmc_enable_bits(nb_dev, 0x02, ~(1<<20), 0x00030200);
780 nbmc_write_index(nb_dev, 0x04, 0x08881018);
781 nbmc_write_index(nb_dev, 0x05, 0x000000bb);
782 nbmc_write_index(nb_dev, 0x0c, 0x0f00001f);
783 nbmc_write_index(nb_dev, 0xa1, 0x01f10000);
784 /* MCA_INIT_DLL_PM. */
785 set_nbmc_enable_bits(nb_dev, 0xc9, 1<<24, 1<<24);
786 nbmc_write_index(nb_dev, 0xa2, 0x74f20000);
787 nbmc_write_index(nb_dev, 0xa3, 0x8af30000);
788 nbmc_write_index(nb_dev, 0xaf, 0x47d0a41c);
789 nbmc_write_index(nb_dev, 0xb0, 0x88800130);
790 nbmc_write_index(nb_dev, 0xb1, 0x00000040);
791 nbmc_write_index(nb_dev, 0xb4, 0x41247000);
792 nbmc_write_index(nb_dev, 0xb5, 0x00066664);
793 nbmc_write_index(nb_dev, 0xb6, 0x00000022);
794 nbmc_write_index(nb_dev, 0xb7, 0x00000044);
795 nbmc_write_index(nb_dev, 0xb8, 0xbbbbbbbb);
796 nbmc_write_index(nb_dev, 0xb9, 0xbbbbbbbb);
797 nbmc_write_index(nb_dev, 0xba, 0x55555555);
798 nbmc_write_index(nb_dev, 0xc1, 0x00000000);
799 nbmc_write_index(nb_dev, 0xc2, 0x00000000);
800 nbmc_write_index(nb_dev, 0xc3, 0x80006b00);
801 nbmc_write_index(nb_dev, 0xc4, 0x00066664);
802 nbmc_write_index(nb_dev, 0xc5, 0x00000000);
803 nbmc_write_index(nb_dev, 0xd2, 0x00000022);
804 nbmc_write_index(nb_dev, 0xd3, 0x00000044);
805 nbmc_write_index(nb_dev, 0xd6, 0x00050005);
806 nbmc_write_index(nb_dev, 0xd7, 0x00000000);
807 nbmc_write_index(nb_dev, 0xd8, 0x00700070);
808 nbmc_write_index(nb_dev, 0xd9, 0x00700070);
809 nbmc_write_index(nb_dev, 0xe0, 0x00200020);
810 nbmc_write_index(nb_dev, 0xe1, 0x00200020);
811 nbmc_write_index(nb_dev, 0xe8, 0x00200020);
812 nbmc_write_index(nb_dev, 0xe9, 0x00200020);
813 nbmc_write_index(nb_dev, 0xe0, 0x00180018);
814 nbmc_write_index(nb_dev, 0xe1, 0x00180018);
815 nbmc_write_index(nb_dev, 0xe8, 0x00180018);
816 nbmc_write_index(nb_dev, 0xe9, 0x00180018);
819 /* Memory Termination. */
820 set_nbmc_enable_bits(nb_dev, 0xa1, 0x0ff, 0x044);
821 set_nbmc_enable_bits(nb_dev, 0xb4, 0xf00, 0xb00);
823 /* Controller Termation. */
824 set_nbmc_enable_bits(nb_dev, 0xb1, 0x77770000, 0x77770000);
827 /* OEM Init MC. 667MHz. */
828 nbmc_write_index(nb_dev, 0xa8, 0x7a5aaa78);
829 nbmc_write_index(nb_dev, 0xa9, 0x514a2319);
830 nbmc_write_index(nb_dev, 0xaa, 0x54400520);
831 nbmc_write_index(nb_dev, 0xab, 0x441460ff);
832 nbmc_write_index(nb_dev, 0xa0, 0x20f00a48);
833 set_nbmc_enable_bits(nb_dev, 0xa2, ~(0xffffffc7), 0x10);
834 nbmc_write_index(nb_dev, 0xb2, 0x00000303);
835 set_nbmc_enable_bits(nb_dev, 0xb1, ~(0xffffff70), 0x45);
837 /* set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b); */
839 /* Init PM timing. */
842 l_dword = nbmc_read_index(nb_dev, 0xa0+i);
843 nbmc_write_index(nb_dev, 0xc8+i, l_dword);
847 l_dword = nbmc_read_index(nb_dev, 0xa8+i);
848 nbmc_write_index(nb_dev, 0xcc+i, l_dword);
850 l_dword = nbmc_read_index(nb_dev, 0xb1);
851 set_nbmc_enable_bits(nb_dev, 0xc8, 0xff<<24, ((l_dword&0x0f)<<24)|((l_dword&0xf00)<<20));
854 /* FB_Start = ; FB_End = ; iSpSize = 0x0080, 128MB. */
855 nbmc_write_index(nb_dev, 0x11, 0x40000000);
856 FB_Start = 0xc00 + 0x080;
857 FB_End = 0xc00 + 0x080;
858 nbmc_write_index(nb_dev, 0x10, (((FB_End&0xfff)<<20)-0x10000)|(((FB_Start&0xfff)-0x080)<<4));
859 set_nbmc_enable_bits(nb_dev, 0x0d, ~0x000ffff0, (FB_Start&0xfff)<<20);
860 nbmc_write_index(nb_dev, 0x0f, 0);
861 nbmc_write_index(nb_dev, 0x0e, (FB_Start&0xfff)|(0xaaaa<<12));
864 /* GFX_InitSP finished. */
867 static struct pci_operations lops_pci = {
868 .set_subsystem = pci_dev_set_subsystem,
871 static struct device_operations pcie_ops = {
872 .read_resources = rs780_gfx_read_resources,
873 .set_resources = pci_dev_set_resources,
874 .enable_resources = pci_dev_enable_resources,
875 .init = internal_gfx_pci_dev_init, /* The option ROM initializes the device. rs780_gfx_init, */
877 .enable = rs780_internal_gfx_enable,
878 .ops_pci = &lops_pci,
882 * We should list all of them here.
884 static const struct pci_driver pcie_driver_780 __pci_driver = {
886 .vendor = PCI_VENDOR_ID_ATI,
887 .device = PCI_DEVICE_ID_ATI_RS780_INT_GFX,
890 static const struct pci_driver pcie_driver_780c __pci_driver = {
892 .vendor = PCI_VENDOR_ID_ATI,
893 .device = PCI_DEVICE_ID_ATI_RS780C_INT_GFX,
895 static const struct pci_driver pcie_driver_780m __pci_driver = {
897 .vendor = PCI_VENDOR_ID_ATI,
898 .device = PCI_DEVICE_ID_ATI_RS780M_INT_GFX,
900 static const struct pci_driver pcie_driver_780mc __pci_driver = {
902 .vendor = PCI_VENDOR_ID_ATI,
903 .device = PCI_DEVICE_ID_ATI_RS780MC_INT_GFX,
905 static const struct pci_driver pcie_driver_780e __pci_driver = {
907 .vendor = PCI_VENDOR_ID_ATI,
908 .device = PCI_DEVICE_ID_ATI_RS780E_INT_GFX,
910 static const struct pci_driver pcie_driver_785g __pci_driver = {
912 .vendor = PCI_VENDOR_ID_ATI,
913 .device = PCI_DEVICE_ID_ATI_RS785G_INT_GFX,
916 /* step 12 ~ step 14 from rpr */
917 static void single_port_configuration(device_t nb_dev, device_t dev)
921 struct southbridge_amd_rs780_config *cfg =
922 (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
924 printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration.\n");
926 /* step 12 training, releases hold training for GFX port 0 (device 2) */
927 PcieReleasePortTraining(nb_dev, dev, 2);
928 result = PcieTrainPort(nb_dev, dev, 2);
929 printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step12.\n");
931 /* step 13 Power Down Control */
932 /* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */
933 set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0);
935 /* step 13.a Link Training was NOT successful */
937 set_nbmisc_enable_bits(nb_dev, 0x8, 0, 0x3 << 4); /* prevent from training. */
938 set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x3 << 2); /* hide the GFX bridge. */
940 nbpcie_ind_write_index(nb_dev, 0x65, 0xccf0f0);
942 nbpcie_ind_write_index(nb_dev, 0x65, 0xffffffff);
943 set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 3, 1 << 3);
945 } else { /* step 13.b Link Training was successful */
946 set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1);
947 reg32 = nbpcie_p_read_index(dev, 0x29);
948 width = reg32 & 0xFF;
949 printk(BIOS_DEBUG, "GFX Inactive Lanes = 0x%x.\n", width);
953 nbpcie_ind_write_index(nb_dev, 0x65,
954 cfg->gfx_lane_reversal ? 0x7f7f : 0xccfefe);
957 nbpcie_ind_write_index(nb_dev, 0x65,
958 cfg->gfx_lane_reversal ? 0x3f3f : 0xccfcfc);
961 nbpcie_ind_write_index(nb_dev, 0x65,
962 cfg->gfx_lane_reversal ? 0x0f0f : 0xccf0f0);
966 printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step13.\n");
968 /* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */
969 set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19);
970 printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step14.\n");
973 static void dual_port_configuration(device_t nb_dev, device_t dev)
976 u32 reg32, dev_ind = dev->path.pci.devfn >> 3;
977 struct southbridge_amd_rs780_config *cfg =
978 (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
980 /* 5.4.1.2 Dual Port Configuration */
981 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
982 set_nbmisc_enable_bits(nb_dev, 0x08, 0xF << 8, 0x5 << 8);
983 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
985 /* 5.7. Training for Device 2 */
986 /* 5.7.1. Releases hold training for GFX port 0 (device 2) */
987 PcieReleasePortTraining(nb_dev, dev, dev_ind);
988 /* 5.7.2- 5.7.9. PCIE Link Training Sequence */
989 result = PcieTrainPort(nb_dev, dev, dev_ind);
991 /* Power Down Control for Device 2 */
992 /* Link Training was NOT successful */
994 /* Powers down all lanes for port A */
995 /* nbpcie_ind_write_index(nb_dev, 0x65, 0x0f0f); */
996 /* Note: I have to disable the slot where there isnt a device,
997 * otherwise the system will hang. I dont know why. */
998 set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, 1 << dev_ind);
1000 } else { /* step 16.b Link Training was successful */
1001 reg32 = nbpcie_p_read_index(dev, 0xa2);
1002 width = (reg32 >> 4) & 0x7;
1003 printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width);
1007 nbpcie_ind_write_index(nb_dev, 0x65,
1008 cfg->gfx_lane_reversal ? 0x0707 : 0x0e0e);
1011 nbpcie_ind_write_index(nb_dev, 0x65,
1012 cfg->gfx_lane_reversal ? 0x0303 : 0x0c0c);
1018 /* For single port GFX configuration Only
1025 * 101 = x12 (not supported)
1028 static void dynamic_link_width_control(device_t nb_dev, device_t dev, u8 width)
1032 struct southbridge_amd_rs780_config *cfg =
1033 (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
1036 reg32 = nbpcie_p_read_index(dev, 0xa2);
1039 set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 1 << 0);
1041 set_pcie_enable_bits(dev, 0xa2, 3 << 0, width << 0);
1043 set_pcie_enable_bits(dev, 0xa2, 1 << 8, 1 << 8);
1045 if (0 == cfg->gfx_reconfiguration)
1046 set_pcie_enable_bits(dev, 0xa2, 1 << 11, 1 << 11);
1050 reg32 = nbpcie_p_read_index(dev, 0xa2);
1052 while (reg32 & 0x100);
1055 sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0));
1057 reg32 = pci_ext_read_config32(nb_dev, sb_dev,
1058 PCIE_VC0_RESOURCE_STATUS);
1059 } while (reg32 & VC_NEGOTIATION_PENDING);
1062 reg32 = nbpcie_p_read_index(dev, 0xa2);
1063 if (((reg32 & 0x70) >> 4) != 0x6) {
1064 /* the unused lanes should be powered off. */
1068 set_pcie_enable_bits(nb_dev, 0x40, 1 << 0, 0 << 0);
1072 * GFX Core initialization, dev2, dev3
1074 void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
1077 struct southbridge_amd_rs780_config *cfg =
1078 (struct southbridge_amd_rs780_config *)nb_dev->chip_info;
1080 printk(BIOS_DEBUG, "rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
1083 /* GFX Core Initialization */
1084 //if (port == 2) return;
1086 /* step 2, TMDS, (only need if CMOS option is enabled) */
1087 if (cfg->gfx_tmds) {
1090 #if 1 /* external clock mode */
1091 /* table 5-22, 5.9.1. REFCLK */
1092 /* 5.9.1.1. Disables the GFX REFCLK transmitter so that the GFX
1093 * REFCLK PAD can be driven by an external source. */
1094 /* 5.9.1.2. Enables GFX REFCLK receiver to receive the REFCLK from an external source. */
1095 set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28 | 1 << 26, 1 << 28);
1097 /* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */
1098 /* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */
1099 /* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */
1100 set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
1101 1 << 6 | 1 << 8 | 1 << 10);
1102 reg32 = nbmisc_read_index(nb_dev, 0x28);
1103 printk(BIOS_DEBUG, "misc 28 = %x\n", reg32);
1105 /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */
1106 set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 1 << 31);
1107 #else /* internal clock mode */
1108 /* table 5-23, 5.9.1. REFCLK */
1109 /* 5.9.1.1. Enables the GFX REFCLK transmitter so that the GFX
1110 * REFCLK PAD can be driven by the SB REFCLK. */
1111 /* 5.9.1.2. Disables GFX REFCLK receiver from receiving the
1112 * REFCLK from an external source.*/
1113 set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28, 1 << 29 | 0 << 28);
1115 /* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */
1116 /* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */
1117 /* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */
1118 set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10,
1120 reg32 = nbmisc_read_index(nb_dev, 0x28);
1121 printk(BIOS_DEBUG, "misc 28 = %x\n", reg32);
1123 /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */
1124 set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 0 << 31);
1127 /* step 5.9.3, GFX overclocking, (only need if CMOS option is enabled) */
1128 /* 5.9.3.1. Increases PLL BW for 6G operation.*/
1129 /* set_nbmisc_enable_bits(nb_dev, 0x36, 0x3FF << 4, 0xB5 << 4); */
1132 /* step 5.9.4, reset the GFX link */
1133 /* step 5.9.4.1 asserts both calibration reset and global reset */
1134 set_nbmisc_enable_bits(nb_dev, 0x8, 0x3 << 14, 0x3 << 14);
1136 /* step 5.9.4.2 de-asserts calibration reset */
1137 set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 14, 0 << 14);
1139 /* step 5.9.4.3 wait for at least 200us */
1142 /* step 5.9.4.4 de-asserts global reset */
1143 set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 15, 0 << 15);
1145 /* 5.9.5 Reset PCIE_GFX Slot */
1146 /* It is done in mainboard.c */
1151 /* step 5.9.8 program PCIE memory mapped configuration space */
1152 /* done by enable_pci_bar3() before */
1154 /* step 7 compliance state, (only need if CMOS option is enabled) */
1155 /* the compliance stete is just for test. refer to 4.2.5.2 of PCIe specification */
1156 if (cfg->gfx_compliance) {
1157 /* force compliance */
1158 set_nbmisc_enable_bits(nb_dev, 0x32, 1 << 6, 1 << 6);
1159 /* release hold training for device 2. GFX initialization is done. */
1160 set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4);
1161 dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width);
1162 printk(BIOS_DEBUG, "rs780_gfx_init step7.\n");
1166 /* 5.9.12 Core Initialization. */
1167 /* 5.9.12.1 sets RCB timeout to be 25ms */
1168 /* 5.9.12.2. RCB Cpl timeout on link down. */
1169 set_pcie_enable_bits(dev, 0x70, 7 << 16 | 1 << 19, 4 << 16 | 1 << 19);
1170 printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.1.\n");
1172 /* step 5.9.12.3 disables slave ordering logic */
1173 set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8);
1174 printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.3.\n");
1176 /* step 5.9.12.4 sets DMA payload size to 64 bytes */
1177 set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10);
1178 /* 5.9.12.5. Blocks DMA traffic during C3 state. */
1179 set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
1181 /* 5.9.12.6. Disables RC ordering logic */
1182 set_pcie_enable_bits(nb_dev, 0x20, 1 << 9, 1 << 9);
1184 /* Enabels TLP flushing. */
1185 /* Note: It is got from RS690. The system will hang without this action. */
1186 set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
1188 /* 5.9.12.7. Ignores DLLPs during L1 so that txclk can be turned off */
1189 set_pcie_enable_bits(nb_dev, 0x2, 1 << 0, 1 << 0);
1191 /* 5.9.12.8 Prevents LC to go from L0 to Rcv_L0s if L1 is armed. */
1192 set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
1194 /* 5.9.12.9 CMGOOD_OVERRIDE for end point initiated lane degradation. */
1195 set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17);
1196 printk(BIOS_DEBUG, "rs780_gfx_init step5.9.12.9.\n");
1198 /* 5.9.12.10 Sets the timer in Config state from 20us to */
1199 /* 5.9.12.11 De-asserts RX_EN in L0s. */
1200 /* 5.9.12.12 Enables de-assertion of PG2RX_CR_EN to lock clock
1201 * recovery parameter when lane is in electrical idle in L0s.*/
1202 set_pcie_enable_bits(dev, 0xB1, 1 << 23 | 1 << 19 | 1 << 28, 1 << 23 | 1 << 19 | 1 << 28);
1204 /* 5.9.12.13. Turns off offset calibration. */
1205 /* 5.9.12.14. Enables Rx Clock gating in CDR */
1206 set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 10/* | 1 << 22 */, 1 << 10/* | 1 << 22 */);
1208 /* 5.9.12.15. Sets number of TX Clocks to drain TX Pipe to 3. */
1209 set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 3 << 4);
1211 /* 5.9.12.16. Lets PI use Electrical Idle from PHY when
1212 * turning off PLL in L1 at Gen2 speed instead Inferred Electrical Idle. */
1213 set_pcie_enable_bits(nb_dev, 0x40, 3 << 14, 2 << 14);
1215 /* 5.9.12.17. Prevents the Electrical Idle from causing a transition from Rcv_L0 to Rcv_L0s. */
1216 set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20);
1218 /* 5.9.12.18. Prevents the LTSSM from going to Rcv_L0s if it has already
1219 * acknowledged a request to go to L1. */
1220 set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
1222 /* 5.9.12.19. LDSK only taking deskew on deskewing error detect */
1223 set_pcie_enable_bits(nb_dev, 0x40, 1 << 28, 0 << 28);
1225 /* 5.9.12.20. Bypasses lane de-skew logic if in x1 */
1226 set_pcie_enable_bits(nb_dev, 0xC2, 1 << 14, 1 << 14);
1228 /* 5.9.12.21. Sets Electrical Idle Threshold. */
1229 set_nbmisc_enable_bits(nb_dev, 0x35, 3 << 21, 2 << 21);
1231 /* 5.9.12.22. Advertises -6 dB de-emphasis value in TS1 Data Rate Identifier
1232 * Only if CMOS Option in section. skip */
1234 /* 5.9.12.23. Disables GEN2 capability of the device. */
1235 set_pcie_enable_bits(dev, 0xA4, 1 << 0, 0 << 0);
1237 /* 5.9.12.24.Disables advertising Upconfigure Support. */
1238 set_pcie_enable_bits(dev, 0xA2, 1 << 13, 1 << 13);
1240 /* 5.9.12.25. No comment in RPR. */
1241 set_nbmisc_enable_bits(nb_dev, 0x39, 1 << 10, 0 << 10);
1243 /* 5.9.12.26. This capacity is required since links wider than x1 and/or multiple link
1244 * speed are supported */
1245 set_pcie_enable_bits(nb_dev, 0xC1, 1 << 0, 1 << 0);
1247 /* 5.9.12.27. Enables NVG86 ECO. A13 above only. */
1248 if (get_nb_rev(nb_dev) == REV_RS780_A12) /* A12 */
1249 set_pcie_enable_bits(dev, 0x02, 1 << 11, 1 << 11);
1251 /* 5.9.12.28 Hides and disables the completion timeout method. */
1252 set_pcie_enable_bits(nb_dev, 0xC1, 1 << 2, 0 << 2);
1254 /* 5.9.12.29. Use the bif_core de-emphasis strength by default. */
1255 /* set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 28, 1 << 28); */
1257 /* 5.9.12.30. Set TX arbitration algorithm to round robin */
1258 set_pcie_enable_bits(nb_dev, 0x1C,
1259 1 << 0 | 0x1F << 1 | 0x1F << 6,
1260 1 << 0 | 0x04 << 1 | 0x04 << 6);
1262 /* Single-port/Dual-port configureation. */
1263 switch (cfg->gfx_dual_slot) {
1265 /* step 1, lane reversal (only need if build config option is enabled) */
1266 if (cfg->gfx_lane_reversal) {
1267 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
1268 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
1269 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
1271 printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
1273 printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
1274 if((dev->path.pci.devfn >> 3) == 2) {
1275 single_port_configuration(nb_dev, dev);
1277 set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
1278 printk(BIOS_INFO, "Single port. Do nothing.\n"); // If dev3
1283 /* step 1, lane reversal (only need if build config option is enabled) */
1284 if (cfg->gfx_lane_reversal) {
1285 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
1286 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
1287 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
1288 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
1290 printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
1291 /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
1292 /* AMD calls the configuration CrossFire */
1293 set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
1294 printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
1296 printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
1297 dual_port_configuration(nb_dev, dev);
1302 if(is_dev3_present()){
1303 /* step 1, lane reversal (only need if CMOS option is enabled) */
1304 if (cfg->gfx_lane_reversal) {
1305 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
1306 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
1307 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
1308 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
1310 printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
1311 /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
1312 /* AMD calls the configuration CrossFire */
1313 set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8);
1314 printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
1317 printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
1318 dual_port_configuration(nb_dev, dev);
1321 if (cfg->gfx_lane_reversal) {
1322 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
1323 set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
1324 set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
1326 printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
1328 if((dev->path.pci.devfn >> 3) == 2)
1329 single_port_configuration(nb_dev, dev);
1331 set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
1332 printk(BIOS_DEBUG, "If dev3.., single port. Do nothing.\n");
1337 printk(BIOS_INFO, "Incorrect configuration of external GFX slot.\n");