2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #ifndef _CIMX_SB800_CHIP_H_
21 #define _CIMX_SB800_CHIP_H_
23 extern struct chip_operations southbridge_amd_cimx_sb800_ops;
26 * configuration set in mainboard/devicetree.cb
27 * boot_switch_sata_ide:
28 * 0 -set SATA as primary, PATA(IDE) as secondary.
29 * 1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE,
30 * gpp_configuration - The configuration of General Purpose Port A/B/C/D
31 * 0(GPP_CFGMODE_X4000) -PortA Lanes[3:0]
32 * 2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2]
33 * 3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3
34 * 4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
36 struct southbridge_amd_cimx_sb800_config
38 u32 boot_switch_sata_ide : 1;
42 #endif /* _CIMX_SB800_CHIP_H_ */