2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <arch/romcc_io.h>
23 static void enable_rom(void)
29 dev = PCI_DEV(0, 0x14, 0x03);
30 /* SB800 LPC Bridge 0:20:3:44h.
31 * BIT6: Port Enable for serial port 0x3f8-0x3ff
32 * BIT29: Port Enable for KBC port 0x60 and 0x64
33 * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
35 dword = pci_io_read_config32(dev, 0x44);
36 //dword |= (1<<6) | (1<<29) | (1<<30) ;
37 /* Turn on all of LPC IO Port decode enable */
39 pci_io_write_config32(dev, 0x44, dword);
41 /* SB800 LPC Bridge 0:20:3:48h.
42 * BIT0: Port Enable for SuperIO 0x2E-0x2F
43 * BIT1: Port Enable for SuperIO 0x4E-0x4F
44 * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
45 * BIT6: Port Enable for RTC IO 0x70-0x73
46 * BIT21: Port Enable for Port 0x80
48 dword = pci_io_read_config32(dev, 0x48);
49 dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21);
50 pci_io_write_config32(dev, 0x48, dword);
52 /* Enable rom access */
53 word = pci_io_read_config16(dev, 0x6c);
54 word = 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6);
55 pci_io_write_config16(dev, 0x6c, word);
58 static void enable_prefetch(void)
61 device_t dev = PCI_DEV(0, 0x14, 0x03);
63 /* Enable PrefetchEnSPIFromHost */
64 dword = pci_io_read_config32(dev, 0xb8);
65 pci_io_write_config32(dev, 0xb8, dword | (1 << 24));
68 static void enable_spi_fast_mode(void)
72 device_t dev = PCI_DEV(0, 0x14, 0x03);
75 volatile u32 *spi_base = (void *)0xa0000000;
76 u32 save = pci_io_read_config32(dev, 0xa0);
77 pci_io_write_config32(dev, 0xa0, (u32) spi_base | 2);
79 // early enable of SPI 33 MHz fast mode read
81 spi_base[3] = (byte & ~(3 << 14)) | (1 << 14);
82 spi_base[0] = spi_base[0] | (1 << 18); // fast read enable
84 pci_io_write_config32(dev, 0xa0, save);
87 static void enable_clocks(void)
91 volatile u32 *acpi_mmio = (void *) (0xFED80000 + 0xE00 + 0x40);
93 // Program AcpiMmioEn to enable MMIO access to MiscCntrl register
100 // Program SB800 MiscCntrl Device_CLK1_sel for 48 MHz (default is 14 MHz)
102 reg32 &= ~((1 << 0) | (1 << 2));
107 static void bootblock_southbridge_init(void)
109 /* Setup the rom access for 2M */
112 enable_spi_fast_mode();