1 // Initialize PCI devices (on emulators)
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU GPLv3 license.
8 #include "util.h" // dprintf
9 #include "pci.h" // PCIDevice
10 #include "biosvar.h" // GET_EBDA
12 #define PCI_ADDRESS_SPACE_MEM 0x00
13 #define PCI_ADDRESS_SPACE_IO 0x01
14 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
16 #define PCI_ROM_SLOT 6
17 #define PCI_NUM_REGIONS 7
19 static u32 pci_bios_io_addr;
20 static u32 pci_bios_mem_addr;
21 static u32 pci_bios_bigmem_addr;
22 /* host irqs corresponding to PCI irqs A-D */
23 static u8 pci_irqs[4] = { 11, 9, 11, 9 };
25 static void pci_set_io_region_addr(PCIDevice d, int region_num, u32 addr)
30 if ( region_num == PCI_ROM_SLOT ) {
33 ofs = 0x10 + region_num * 4;
36 old_addr = pci_config_readl(d, ofs);
38 pci_config_writel(d, ofs, addr);
39 dprintf(1, "region %d: 0x%08x\n", region_num, addr);
41 /* enable memory mappings */
42 cmd = pci_config_readw(d, PCI_COMMAND);
43 if ( region_num == PCI_ROM_SLOT )
45 else if (old_addr & PCI_ADDRESS_SPACE_IO)
49 pci_config_writew(d, PCI_COMMAND, cmd);
52 /* return the global irq number corresponding to a given device irq
53 pin. We could also use the bus number to have a more precise
55 static int pci_slot_get_pirq(PCIDevice pci_dev, int irq_num)
58 slot_addend = (pci_dev.devfn >> 3) - 1;
59 return (irq_num + slot_addend) & 3;
62 static void pci_bios_init_bridges(PCIDevice d)
64 u16 vendor_id, device_id;
66 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
67 device_id = pci_config_readw(d, PCI_DEVICE_ID);
69 if (vendor_id == PCI_VENDOR_ID_INTEL
70 && device_id == PCI_DEVICE_ID_INTEL_82371SB_0) {
78 for(i = 0; i < 4; i++) {
80 /* set to trigger level */
81 elcr[irq >> 3] |= (1 << (irq & 7));
82 /* activate irq remapping in PIIX */
83 pci_config_writeb(d, 0x60 + i, irq);
87 dprintf(1, "PIIX3 init: elcr=%02x %02x\n",
92 static void pci_bios_init_device(PCIDevice d)
96 int i, pin, pic_irq, vendor_id, device_id;
98 class = pci_config_readw(d, PCI_CLASS_DEVICE);
99 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
100 device_id = pci_config_readw(d, PCI_DEVICE_ID);
101 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n",
102 d.bus, d.devfn, vendor_id, device_id);
105 if (vendor_id == PCI_VENDOR_ID_INTEL
106 && device_id == PCI_DEVICE_ID_INTEL_82371SB_1) {
108 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
109 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
112 /* IDE: we map it as in ISA mode */
113 pci_set_io_region_addr(d, 0, 0x1f0);
114 pci_set_io_region_addr(d, 1, 0x3f4);
115 pci_set_io_region_addr(d, 2, 0x170);
116 pci_set_io_region_addr(d, 3, 0x374);
120 if (vendor_id != 0x1234)
122 /* VGA: map frame buffer to default Bochs VBE address */
123 pci_set_io_region_addr(d, 0, 0xE0000000);
127 if (vendor_id == PCI_VENDOR_ID_IBM) {
129 if (device_id == 0x0046 || device_id == 0xFFFF) {
131 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
136 if (vendor_id == PCI_VENDOR_ID_APPLE &&
137 (device_id == 0x0017 || device_id == 0x0022)) {
139 pci_set_io_region_addr(d, 0, 0x80800000);
144 /* default memory mappings */
145 for(i = 0; i < PCI_NUM_REGIONS; i++) {
149 if (i == PCI_ROM_SLOT)
153 pci_config_writel(d, ofs, 0xffffffff);
154 val = pci_config_readl(d, ofs);
156 size = (~(val & ~0xf)) + 1;
157 if (val & PCI_ADDRESS_SPACE_IO)
158 paddr = &pci_bios_io_addr;
159 else if (size >= 0x04000000)
160 paddr = &pci_bios_bigmem_addr;
162 paddr = &pci_bios_mem_addr;
163 *paddr = ALIGN(*paddr, size);
164 pci_set_io_region_addr(d, i, *paddr);
171 /* map the interrupt */
172 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
174 pin = pci_slot_get_pirq(d, pin - 1);
175 pic_irq = pci_irqs[pin];
176 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
179 if (vendor_id == PCI_VENDOR_ID_INTEL
180 && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
181 /* PIIX4 Power Management device (for ACPI) */
182 u32 pm_io_base = BUILD_PM_IO_BASE;
183 pci_config_writel(d, 0x40, pm_io_base | 1);
184 pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
185 u32 smb_io_base = BUILD_SMB_IO_BASE;
186 pci_config_writel(d, 0x90, smb_io_base | 1);
187 pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
191 static void pci_for_each_device(void (*init_func)(PCIDevice d))
194 u16 vendor_id, device_id;
196 for(bus = 0; bus < 1; bus++) {
197 for(devfn = 0; devfn < 256; devfn++) {
198 PCIDevice d = pci_bd(bus, devfn);
199 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
200 device_id = pci_config_readw(d, PCI_DEVICE_ID);
201 if (vendor_id != 0xffff || device_id != 0xffff) {
212 // Already done by coreboot.
215 pci_bios_io_addr = 0xc000;
216 pci_bios_mem_addr = 0xf0000000;
217 pci_bios_bigmem_addr = GET_EBDA(ram_size);
218 if (pci_bios_bigmem_addr < 0x90000000)
219 pci_bios_bigmem_addr = 0x90000000;
221 pci_for_each_device(pci_bios_init_bridges);
223 pci_for_each_device(pci_bios_init_device);