4 #include "types.h" // u32
6 typedef struct PCIDevice {
11 static inline PCIDevice pci_bd(u8 bus, u8 devfn) {
12 struct PCIDevice d = {bus, devfn};
15 static inline u16 pci_to_bdf(PCIDevice d) {
16 return (d.bus << 8) | d.devfn;
18 static inline u8 pci_bdf_to_bus(u16 bdf) {
21 static inline u8 pci_bdf_to_dev(u16 bdf) {
22 return (bdf >> 3) & 0x1f;
24 static inline u8 pci_bdf_to_fn(u16 bdf) {
28 void pci_config_writel(PCIDevice d, u32 addr, u32 val);
29 void pci_config_writew(PCIDevice d, u32 addr, u16 val);
30 void pci_config_writeb(PCIDevice d, u32 addr, u8 val);
31 u32 pci_config_readl(PCIDevice d, u32 addr);
32 u16 pci_config_readw(PCIDevice d, u32 addr);
33 u8 pci_config_readb(PCIDevice d, u32 addr);
35 int pci_find_device(u16 vendid, u16 devid, int index, PCIDevice *dev);
36 int pci_find_classprog(u32 classprog, int index, PCIDevice *dev);
37 int pci_find_class(u16 classid, int index, PCIDevice *dev);
40 void create_pirtable();
43 /****************************************************************
45 ****************************************************************/
47 #define PCI_VENDOR_ID 0x00 /* 16 bits */
48 #define PCI_DEVICE_ID 0x02 /* 16 bits */
49 #define PCI_COMMAND 0x04 /* 16 bits */
50 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
51 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
52 #define PCI_CLASS_PROG 0x09
53 #define PCI_CLASS_DEVICE 0x0a /* Device class */
54 #define PCI_BASE_ADDR_0 0x10
55 #define PCI_BASE_ADDR_1 0x14
56 #define PCI_BASE_ADDR_2 0x18
57 #define PCI_BASE_ADDR_3 0x1c
58 #define PCI_BASE_ADDR_4 0x20
59 #define PCI_BASE_ADDR_5 0x24
60 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
61 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
62 #define PCI_MIN_GNT 0x3e /* 8 bits */
63 #define PCI_MAX_LAT 0x3f /* 8 bits */
65 #define PCI_VENDOR_ID_INTEL 0x8086
66 #define PCI_VENDOR_ID_IBM 0x1014
67 #define PCI_VENDOR_ID_APPLE 0x106b
69 #define PCI_DEVICE_ID_INTEL_82441 0x1237
70 #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
71 #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
72 #define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110
73 #define PCI_DEVICE_ID_INTEL_82371AB 0x7111
74 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
77 /****************************************************************
79 ****************************************************************/
89 struct link_info links[4];
101 u32 compatible_devid;
105 struct pir_slot slots[0];
108 #define PIR_SIGNATURE 0x52495024 // $PIR