2 * This file is part of the coreboot project.
4 * Copyright (C) 2009 One Laptop per Child, Association, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <device/pci_ids.h>
22 #define SMBUS_IO_BASE 0x0500 //from award bios
23 #define PMIO_BASE VX800_ACPI_IO_BASE //might as well set this while we're here
25 #define SMBHSTSTAT SMBUS_IO_BASE + 0x0
26 #define SMBSLVSTAT SMBUS_IO_BASE + 0x1
27 #define SMBHSTCTL SMBUS_IO_BASE + 0x2
28 #define SMBHSTCMD SMBUS_IO_BASE + 0x3
29 #define SMBXMITADD SMBUS_IO_BASE + 0x4
30 #define SMBHSTDAT0 SMBUS_IO_BASE + 0x5
31 #define SMBHSTDAT1 SMBUS_IO_BASE + 0x6
32 /* Rest of these aren't currently used... */
33 #define SMBBLKDAT SMBUS_IO_BASE + 0x7
34 #define SMBSLVCTL SMBUS_IO_BASE + 0x8
35 #define SMBTRNSADD SMBUS_IO_BASE + 0x9
36 #define SMBSLVDATA SMBUS_IO_BASE + 0xa
37 #define SMLINK_PIN_CTL SMBUS_IO_BASE + 0xe
38 #define SMBUS_PIN_CTL SMBUS_IO_BASE + 0xf
40 /* Define register settings */
41 #define HOST_RESET 0xff
42 #define DIMM_BASE 0xa0 // 1010000 is base for DIMM in SMBus
43 #define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ
45 #define SMBUS_TIMEOUT (100*1000*10)
47 #define I2C_TRANS_CMD 0x40
48 #define CLOCK_SLAVE_ADDRESS 0x69
50 #define SMBUS_DELAY() outb(0x80, 0x80)
52 /* Debugging macros. Only necessary if something isn't working right */
57 #define PRINT_DEBUG(x) print_debug(x)
58 #define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
60 #define PRINT_DEBUG(x)
61 #define PRINT_DEBUG_HEX16(x)
64 /* Internal functions */
65 static void smbus_print_error(unsigned char host_status_register, int loops)
67 // print_err("some i2c error\r\n");
68 /* Check if there actually was an error */
69 if ( host_status_register == 0x00 || host_status_register == 0x40 ||
70 host_status_register == 0x42) return;
71 print_err("smbus_error: ");
72 print_err_hex8(host_status_register);
74 if (loops >= SMBUS_TIMEOUT) {
75 print_err("SMBus Timout\r\n");
77 if (host_status_register & (1 << 4)) {
78 print_err("Interrup/SMI# was Failed Bus Transaction\r\n");
80 if (host_status_register & (1 << 3)) {
81 print_err("Bus Error\r\n");
83 if (host_status_register & (1 << 2)) {
84 print_err("Device Error\r\n");
86 if (host_status_register & (1 << 1)) {
87 /* This isn't a real error... */
88 print_debug("Interrupt/SMI# was Successful Completion\r\n");
90 if (host_status_register & (1 << 0)) {
91 print_err("Host Busy\r\n");
95 static void smbus_wait_until_ready(void)
100 /* Yes, this is a mess, but it's the easiest way to do it */
101 while(((inb(SMBHSTSTAT) & 1) == 1) && (loops <= SMBUS_TIMEOUT)) {
105 smbus_print_error(inb(SMBHSTSTAT), loops);
108 static void smbus_reset(void)
110 outb(HOST_RESET, SMBHSTSTAT);
113 /* Public functions */
114 static unsigned int set_ics_data(unsigned char dev, int data, char len)
118 /* clear host data port */
119 outb(0x00, SMBHSTDAT0);
121 smbus_wait_until_ready();
123 /* read to reset block transfer counter */
126 /* fill blocktransfer array */
128 //char d2_data[] = {0x0d,0x00,0x3f,0xcd,0x7f,0xbf,0x1a,0x2a,0x01,0x0f,0x0b,0x00,0x8d,0x9b};
129 outb(0x0d,SMBBLKDAT);
130 outb(0x00,SMBBLKDAT);
131 outb(0x3f,SMBBLKDAT);
132 outb(0xcd,SMBBLKDAT);
133 outb(0x7f,SMBBLKDAT);
134 outb(0xbf,SMBBLKDAT);
135 outb(0x1a,SMBBLKDAT);
136 outb(0x2a,SMBBLKDAT);
137 outb(0x01,SMBBLKDAT);
138 outb(0x0f,SMBBLKDAT);
139 outb(0x0b,SMBBLKDAT);
140 outb(0x80,SMBBLKDAT);
141 outb(0x8d,SMBBLKDAT);
142 outb(0x9b,SMBBLKDAT);
144 //char d4_data[] = {0x08,0xff,0x3f,0x00,0x00,0xff,0xff,0xff,0xff};
145 outb(0x08,SMBBLKDAT);
146 outb(0xff,SMBBLKDAT);
147 outb(0x3f,SMBBLKDAT);
148 outb(0x00,SMBBLKDAT);
149 outb(0x00,SMBBLKDAT);
150 outb(0xff,SMBBLKDAT);
151 outb(0xff,SMBBLKDAT);
152 outb(0xff,SMBBLKDAT);
153 outb(0xff,SMBBLKDAT);
156 //for (i=0; i < len; i++)
157 // outb(data[i],SMBBLKDAT);
159 outb(dev, SMBXMITADD);
161 outb(len, SMBHSTDAT0);
162 outb(0x74, SMBHSTCTL);
166 smbus_wait_until_ready();
172 static unsigned int get_spd_data(unsigned int dimm, unsigned int offset)
177 /* clear host data port */
178 outb(0x00, SMBHSTDAT0);
180 smbus_wait_until_ready();
182 /* Do some mathmatic magic */
187 outb(dimm|0x1, SMBXMITADD);
188 outb(offset, SMBHSTCMD);
189 outb(0x48, SMBHSTCTL);
193 smbus_wait_until_ready();
195 val = inb(SMBHSTDAT0);
200 static void enable_smbus(void)
204 dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_LPC), 0);
206 if (dev == PCI_DEV_INVALID) {
207 /* This won't display text if enable_smbus() is before serial init */
208 die("Power Managment Controller not found\r\n");
211 /* Set clock source */
212 pci_write_config8(dev, 0x94, 0x20);
214 /* Write SMBus IO base to 0xd0, and enable SMBus */
215 pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
217 /* Set to Award value */
218 pci_write_config8(dev, 0xd2, 0x05);
220 /* Make it work for I/O ...*/
221 pci_write_config16(dev, 0x04, 0x0003);
224 coreboot hangs at this two lines after os reboot(this even happen after I change os
225 reboot to cold reboot, this also interfere S3 wakeup)*/
226 /* Setup clock chips */
227 //set_ics_data(0xd2, 0, 14);
228 //set_ics_data(0xd4, 0, 9);
231 /* clear host data port */
232 outb(0x00, SMBHSTDAT0);
234 smbus_wait_until_ready();
238 * A fixup for some systems that need time for the SMBus to "warm up". This is
239 * needed on some VT823x based systems, where the SMBus spurts out bad data for
240 * a short time after power on. This has been seen on the VIA Epia series and
241 * Jetway J7F2-series. It reads the ID byte from SMBus, looking for
242 * known-good data from a slot/address. Exits on either good data or a timeout.
244 * TODO: This should probably go into some global file, but one would need to
245 * be created just for it. If some other chip needs/wants it, we can
246 * worry about it then.
248 * @param ctrl The memory controller and SMBus addresses.
250 void smbus_fixup(const struct mem_controller *ctrl)
252 int i, ram_slots, current_slot = 0;
255 ram_slots = ARRAY_SIZE(ctrl->channel0);
257 print_err("smbus_fixup() thinks there are no RAM slots!\r\n");
261 PRINT_DEBUG("Waiting for SMBus to warm up");
264 * Bad SPD data should be either 0 or 0xff, but YMMV. So we look for
265 * the ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between).
266 * VT8237R has only been seen on DDR and DDR2 based systems, so far.
268 for (i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) ||
269 (result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++) {
271 if (current_slot > ram_slots)
274 result = get_spd_data(ctrl->channel0[current_slot],
280 if (i >= SMBUS_TIMEOUT)
281 print_err("SMBus timed out while warming up\r\n");
283 PRINT_DEBUG("Done\r\n");
286 /* Debugging Function */
288 static void dump_spd_data(void)
290 int dimm, offset, regs;
293 for(dimm = 0; dimm < 8; dimm++)
295 print_debug("SPD Data for DIMM ");
296 print_debug_hex8(dimm);
299 val = get_spd_data(dimm, 0);
303 } else if(val == 0x80) {
306 print_debug("No DIMM present\r\n");
309 for(offset = 0; offset < regs; offset++)
311 print_debug(" Offset ");
312 print_debug_hex8(offset);
313 print_debug(" = 0x");
314 print_debug_hex8(get_spd_data(dimm, offset));
320 #define dump_spd_data()