projects / coreboot.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: e6e899d) | patch
Here's the VIA vx800 patch from OLPC.
authorBari Ari <bari@onelabs.com>
Wed, 27 May 2009 13:12:42 +0000 (13:12 +0000)
committerUwe Hermann <uwe@hermann-uwe.de>
Wed, 27 May 2009 13:12:42 +0000 (13:12 +0000)
commit612163e3833e807caeed8889dae41d24026241e7
treee0a711474dd3f82eaf43954dc6074ce6857d9be7tree | snapshot
parente6e899dde951823ebc9abf997a6af06debac82a3commit | diff
Here's the VIA vx800 patch from OLPC.

It's untested, but a good starting point for everyone.

Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
36 files changed:
src/northbridge/via/vx800/Config.lb [new file with mode: 0644] blob
src/northbridge/via/vx800/DrivingClkPhaseData.h [new file with mode: 0644] blob
src/northbridge/via/vx800/chip.h [new file with mode: 0644] blob
src/northbridge/via/vx800/ddr2init/DramInit.c [new file with mode: 0644] blob
src/northbridge/via/vx800/ddr2init/DramInit.h [new file with mode: 0644] blob
src/northbridge/via/vx800/ddr2init/DramUtil.c [new file with mode: 0644] blob
src/northbridge/via/vx800/ddr2init/DramUtil.h [new file with mode: 0644] blob
src/northbridge/via/vx800/ddr2init/Translatorddr2init.c [new file with mode: 0644] blob
src/northbridge/via/vx800/ddr2init/vx800/ClkCtrl.c [new file with mode: 0644] blob
src/northbridge/via/vx800/ddr2init/vx800/DQSSearch.c [new file with mode: 0644] blob
src/northbridge/via/vx800/ddr2init/vx800/DRDY_BL.c [new file with mode: 0644] blob
src/northbridge/via/vx800/ddr2init/vx800/Detection.c [new file with mode: 0644] blob
src/northbridge/via/vx800/ddr2init/vx800/DevInit.c [new file with mode: 0644] blob
src/northbridge/via/vx800/ddr2init/vx800/DrivingSetting.c [new file with mode: 0644] blob
src/northbridge/via/vx800/ddr2init/vx800/FinalSetting.c [new file with mode: 0644] blob
src/northbridge/via/vx800/ddr2init/vx800/FreqSetting.c [new file with mode: 0644] blob
src/northbridge/via/vx800/ddr2init/vx800/RankMap.c [new file with mode: 0644] blob
src/northbridge/via/vx800/ddr2init/vx800/TimingSetting.c [new file with mode: 0644] blob
src/northbridge/via/vx800/ddr2init/vx800/UMARamSetting.c [new file with mode: 0644] blob
src/northbridge/via/vx800/examples/DrivingClkPhaseData.c [new file with mode: 0644] blob
src/northbridge/via/vx800/examples/cache_as_ram_auto.c [new file with mode: 0644] blob
src/northbridge/via/vx800/examples/chipset_init.c [new file with mode: 0644] blob
src/northbridge/via/vx800/northbridge.c [new file with mode: 0644] blob
src/northbridge/via/vx800/northbridge.h [new file with mode: 0644] blob
src/northbridge/via/vx800/raminit.c [new file with mode: 0644] blob
src/northbridge/via/vx800/raminit.h [new file with mode: 0644] blob
src/northbridge/via/vx800/romstrap.inc [new file with mode: 0644] blob
src/northbridge/via/vx800/romstrap.lds [new file with mode: 0644] blob
src/northbridge/via/vx800/vga.c [new file with mode: 0644] blob
src/northbridge/via/vx800/vgabios.c [new file with mode: 0644] blob
src/northbridge/via/vx800/vgachip.h [new file with mode: 0644] blob
src/northbridge/via/vx800/vx800.h [new file with mode: 0644] blob
src/northbridge/via/vx800/vx800_early_serial.c [new file with mode: 0644] blob
src/northbridge/via/vx800/vx800_early_smbus.c [new file with mode: 0644] blob
src/northbridge/via/vx800/vx800_ide.c [new file with mode: 0644] blob
src/northbridge/via/vx800/vx800_lpc.c [new file with mode: 0644] blob
my coreboot WIP stuff (asus m5a99x-evo board)