2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <cpu/x86/mtrr.h>
22 #include <cpu/x86/cache.h>
23 #include <pc80/mc146818rtc.h>
26 #include <arch/romcc_io.h>
31 struct cbmem_entry *get_cbmem_toc(void)
33 return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
36 /* Debugging macros. */
37 #if CONFIG_DEBUG_RAM_SETUP
38 #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x)
40 #define PRINTK_DEBUG(x...)
43 #define RAM_INITIALIZATION_COMPLETE (1 << 19)
45 #define RAM_COMMAND_SELF_REFRESH (0x0 << 16)
46 #define RAM_COMMAND_NOP (0x1 << 16)
47 #define RAM_COMMAND_PRECHARGE (0x2 << 16)
48 #define RAM_COMMAND_MRS (0x3 << 16)
49 #define RAM_COMMAND_EMRS (0x4 << 16)
50 #define RAM_COMMAND_CBR (0x6 << 16)
51 #define RAM_COMMAND_NORMAL (0x7 << 16)
53 #define RAM_EMRS_1 (0x0 << 21)
54 #define RAM_EMRS_2 (0x1 << 21)
55 #define RAM_EMRS_3 (0x2 << 21)
57 static int get_dimm_spd_address(struct sys_info *sysinfo, int device)
59 if (sysinfo->spd_addresses)
60 return sysinfo->spd_addresses[device];
62 return DIMM0 + device;
66 static inline int spd_read_byte(unsigned device, unsigned address)
68 return smbus_read_byte(device, address);
71 static __attribute__((noinline)) void do_ram_command(u32 command)
75 reg32 = MCHBAR32(DCC);
76 reg32 &= ~( (3<<21) | (1<<20) | (1<<19) | (7 << 16) );
79 /* Also set Init Complete */
80 if (command == RAM_COMMAND_NORMAL)
81 reg32 |= RAM_INITIALIZATION_COMPLETE;
83 PRINTK_DEBUG(" Sending RAM command 0x%08x", reg32);
85 MCHBAR32(DCC) = reg32; /* This is the actual magic */
87 PRINTK_DEBUG("...done\n");
92 static void ram_read32(u32 offset)
94 PRINTK_DEBUG(" ram read: %08x\n", offset);
99 #if CONFIG_DEBUG_RAM_SETUP
100 void sdram_dump_mchbar_registers(void)
103 printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n");
105 for (i=0; i<0xfff; i+=4) {
106 if (MCHBAR32(i) == 0)
108 printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i));
113 static int memclk(void)
116 #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
119 switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
123 default: printk(BIOS_DEBUG, "memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
128 #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
129 static u16 fsbclk(void)
131 switch (MCHBAR32(CLKCFG) & 7) {
135 default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
139 #elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
140 static u16 fsbclk(void)
142 switch (MCHBAR32(CLKCFG) & 7) {
146 default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
152 static int sdram_capabilities_max_supported_memory_frequency(void)
156 #if CONFIG_MAXIMUM_SUPPORTED_FREQUENCY
157 return CONFIG_MAXIMUM_SUPPORTED_FREQUENCY;
160 reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */
168 /* Newer revisions of this chipset rather support faster memory clocks,
169 * so if it's a reserved value, return the fastest memory clock that we
170 * know of and can handle
176 * @brief determine whether chipset is capable of dual channel interleaved mode
178 * @return 1 if interleaving is supported, 0 otherwise
180 static int sdram_capabilities_interleave(void)
184 reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
192 * @brief determine whether chipset is capable of two memory channels
194 * @return 1 if dual channel operation is supported, 0 otherwise
196 static int sdram_capabilities_dual_channel(void)
200 reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
207 static int sdram_capabilities_enhanced_addressing_xor(void)
211 reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
217 static int sdram_capabilities_two_dimms_per_channel(void)
221 reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe8); /* CAPID0 + 8 */
227 // TODO check if we ever need this function
229 static int sdram_capabilities_MEM4G_disable(void)
233 reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
240 #define GFX_FREQUENCY_CAP_166MHZ 0x04
241 #define GFX_FREQUENCY_CAP_200MHZ 0x03
242 #define GFX_FREQUENCY_CAP_250MHZ 0x02
243 #define GFX_FREQUENCY_CAP_ALL 0x00
245 static int sdram_capabilities_core_frequencies(void)
249 reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
250 reg8 &= (1 << 3) | (1 << 2) | (1 << 1);
256 static void sdram_detect_errors(struct sys_info *sysinfo)
261 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
263 if (reg8 & ((1<<7)|(1<<2))) {
265 printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n");
266 /* Write back clears bit 2 */
267 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
273 printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n");
275 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
279 /* Set SLP_S3# Assertion Stretch Enable */
280 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */
282 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
285 printk(BIOS_DEBUG, "Reset required.\n");
288 for (;;) asm("hlt"); /* Wait for reset! */
292 /* Set DRAM initialization bit in ICH7 */
293 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
295 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
297 /* clear self refresh status if check is disabled or not a resume */
298 if (!CONFIG_CHECK_SLFRCS_ON_RESUME || sysinfo->boot_path != 2) {
301 /* Validate self refresh config */
302 if (((sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) ||
303 (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) &&
304 !(MCHBAR8(0xf14) & (1<<0))) {
307 if (((sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) ||
308 (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) &&
309 !(MCHBAR8(0xf14) & (1<<1))) {
315 printk(BIOS_DEBUG, "Reset required.\n");
318 for (;;) asm("hlt"); /* Wait for reset! */
323 * @brief Get generic DIMM parameters.
324 * @param sysinfo Central memory controller information structure
326 * This function gathers several pieces of information for each system DIMM:
327 * o DIMM width (x8 / x16)
328 * o DIMM sides (single sided / dual sided)
330 * Also, some non-supported scenarios are detected.
333 static void sdram_get_dram_configuration(struct sys_info *sysinfo)
339 * i945 supports two DIMMs, in two configurations:
341 * - single channel with two DIMMs
342 * - dual channel with one DIMM per channel
344 * In practice dual channel mainboards have their SPD at 0x50/0x52
345 * whereas single channel configurations have their SPD at 0x50/0x51.
347 * The capability register knows a lot about the channel configuration
348 * but for now we stick with the information we gather via SPD.
351 if (sdram_capabilities_dual_channel()) {
352 sysinfo->dual_channel = 1;
353 printk(BIOS_DEBUG, "This mainboard supports Dual Channel Operation.\n");
355 sysinfo->dual_channel = 0;
356 printk(BIOS_DEBUG, "This mainboard supports only Single Channel Operation.\n");
360 * Since we only support two DIMMs in total, there is a limited number
361 * of combinations. This function returns the type of DIMMs.
363 * [0:7] lower DIMM population
364 * [8-15] higher DIMM population
367 * There are 5 different possible populations for a DIMM socket:
368 * 1. x16 double sided (X16DS)
369 * 2. x8 double sided (X8DS)
370 * 3. x16 single sided (X16SS)
371 * 4. x8 double stacked (X8DDS)
372 * 5. not populated (NC)
374 * For the return value we start counting at zero.
378 for (i=0; i<(2 * DIMM_SOCKETS); i++) {
379 int device = get_dimm_spd_address(sysinfo, i);
382 /* Initialize the socket information with a sane value */
383 sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
385 /* Dual Channel not supported, but Channel 1? Bail out */
386 if (!sdram_capabilities_dual_channel() && (i >> 1))
389 /* Two DIMMs per channel not supported, but odd DIMM number? */
390 if (!sdram_capabilities_two_dimms_per_channel() && (i& 1))
393 printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
395 if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) {
396 printk(BIOS_DEBUG, "N/A\n");
400 reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE);
401 if (reg8 == ERROR_SCHEME_ECC)
402 die("Error: ECC memory not supported by this chipset\n");
404 reg8 = spd_read_byte(device, SPD_MODULE_ATTRIBUTES);
405 if (reg8 & MODULE_BUFFERED)
406 die("Error: Buffered memory not supported by this chipset\n");
407 if (reg8 & MODULE_REGISTERED)
408 die("Error: Registered memory not supported by this chipset\n");
410 switch (spd_read_byte(device, SPD_PRIMARY_SDRAM_WIDTH)) {
412 switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
414 printk(BIOS_DEBUG, "x8DDS\n");
415 sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS;
418 printk(BIOS_DEBUG, "x8DS\n");
419 sysinfo->dimm[i] = SYSINFO_DIMM_X8DS;
422 printk(BIOS_DEBUG, "Unsupported.\n");
426 switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
428 printk(BIOS_DEBUG, "x16DS\n");
429 sysinfo->dimm[i] = SYSINFO_DIMM_X16DS;
432 printk(BIOS_DEBUG, "x16SS\n");
433 sysinfo->dimm[i] = SYSINFO_DIMM_X16SS;
436 printk(BIOS_DEBUG, "Unsupported.\n");
440 die("Unsupported DDR-II memory width.\n");
443 dimm_mask |= (1 << i);
447 die("No memory installed.\n");
450 if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
451 printk(BIOS_INFO, "Channel 0 has no memory populated.\n");
456 * @brief determine if any DIMMs are stacked
458 * @param sysinfo central sysinfo data structure.
460 static void sdram_verify_package_type(struct sys_info * sysinfo)
464 /* Assume no stacked DIMMs are available until we find one */
465 sysinfo->package = 0;
466 for (i=0; i<2*DIMM_SOCKETS; i++) {
467 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
470 /* Is the current DIMM a stacked DIMM? */
471 if (spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_NUM_DIMM_BANKS) & (1 << 4))
472 sysinfo->package = 1;
476 static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo)
481 /* Setup CAS mask with all supported CAS Latencies */
482 cas_mask = SPD_CAS_LATENCY_DDR2_3 |
483 SPD_CAS_LATENCY_DDR2_4 |
484 SPD_CAS_LATENCY_DDR2_5;
486 for (i=0; i<2*DIMM_SOCKETS; i++) {
487 if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED)
488 cas_mask &= spd_read_byte(get_dimm_spd_address(sysinfo, i),
489 SPD_ACCEPTABLE_CAS_LATENCIES);
493 die("No DDR-II modules with accepted CAS latencies found.\n");
499 static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 cas_mask)
502 int lowest_common_cas = 0;
503 int max_ram_speed = 0;
505 const u8 ddr2_speeds_table[] = {
506 0x50, 0x60, /* DDR2 400: tCLK = 5.0ns tAC = 0.6ns */
507 0x3d, 0x50, /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns */
508 0x30, 0x45, /* DDR2 667: tCLK = 3.0ns tAC = 0.45ns */
511 const u8 spd_lookup_table[] = {
512 SPD_MIN_CYCLE_TIME_AT_CAS_MAX, SPD_ACCESS_TIME_FROM_CLOCK,
513 SPD_SDRAM_CYCLE_TIME_2ND, SPD_ACCESS_TIME_FROM_CLOCK_2ND,
514 SPD_SDRAM_CYCLE_TIME_3RD, SPD_ACCESS_TIME_FROM_CLOCK_3RD
517 switch (sdram_capabilities_max_supported_memory_frequency()) {
518 case 400: max_ram_speed = 0; break;
519 case 533: max_ram_speed = 1; break;
520 case 667: max_ram_speed = 2; break;
526 sysinfo->memory_frequency = 0;
529 if (cas_mask & SPD_CAS_LATENCY_DDR2_3) {
530 lowest_common_cas = 3;
531 } else if (cas_mask & SPD_CAS_LATENCY_DDR2_4) {
532 lowest_common_cas = 4;
533 } else if (cas_mask & SPD_CAS_LATENCY_DDR2_5) {
534 lowest_common_cas = 5;
536 PRINTK_DEBUG("lowest common cas = %d\n", lowest_common_cas);
538 for (j = max_ram_speed; j>=0; j--) {
539 int freq_cas_mask = cas_mask;
541 PRINTK_DEBUG("Probing Speed %d\n", j);
542 for (i=0; i<2*DIMM_SOCKETS; i++) {
543 int device = get_dimm_spd_address(sysinfo, i);
544 int current_cas_mask;
546 PRINTK_DEBUG(" DIMM: %d\n", i);
547 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
551 current_cas_mask = spd_read_byte(device, SPD_ACCEPTABLE_CAS_LATENCIES);
553 while (current_cas_mask) {
554 int highest_supported_cas = 0, current_cas = 0;
555 PRINTK_DEBUG(" Current CAS mask: %04x; ", current_cas_mask);
556 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
557 highest_supported_cas = 5;
558 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
559 highest_supported_cas = 4;
560 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
561 highest_supported_cas = 3;
563 die("Invalid max. CAS.\n");
565 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
567 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
569 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
572 die("Invalid CAS.\n");
575 idx = highest_supported_cas - current_cas;
576 PRINTK_DEBUG("idx=%d, ", idx);
577 PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(device, spd_lookup_table[2*idx]));
578 PRINTK_DEBUG("tAC=%x", spd_read_byte(device, spd_lookup_table[(2*idx)+1]));
580 if (spd_read_byte(device, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
581 spd_read_byte(device, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
582 PRINTK_DEBUG(": OK\n");
586 PRINTK_DEBUG(": Not fast enough!\n");
588 current_cas_mask &= ~(1 << (current_cas));
591 freq_cas_mask &= current_cas_mask;
592 if (!current_cas_mask) {
593 PRINTK_DEBUG(" No valid CAS for this speed on DIMM %d\n", i);
597 PRINTK_DEBUG(" freq_cas_mask for speed %d: %04x\n", j, freq_cas_mask);
600 case 0: sysinfo->memory_frequency = 400; break;
601 case 1: sysinfo->memory_frequency = 533; break;
602 case 2: sysinfo->memory_frequency = 667; break;
604 if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
606 } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
608 } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
615 if (sysinfo->memory_frequency && sysinfo->cas) {
616 printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n",
617 sysinfo->memory_frequency, sysinfo->cas);
619 die("Could not find common memory frequency and CAS\n");
623 static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo)
628 int freq_multiplier = 0;
630 switch (sysinfo->memory_frequency) {
631 case 400: freq_multiplier = 0x14; break; /* 5ns */
632 case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
633 case 667: freq_multiplier = 0x0c; break; /* 3ns */
636 tRAS_cycles = 4; /* 4 clocks minimum */
637 tRAS_time = tRAS_cycles * freq_multiplier;
639 for (i=0; i<2*DIMM_SOCKETS; i++) {
642 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
645 reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
647 die("Invalid tRAS value.\n");
650 while ((tRAS_time >> 2) < reg8) {
651 tRAS_time += freq_multiplier;
655 if(tRAS_cycles > 0x18) {
656 die("DDR-II Module does not support this frequency (tRAS error)\n");
659 printk(BIOS_DEBUG, "tRAS = %d cycles\n", tRAS_cycles);
660 sysinfo->tras = tRAS_cycles;
663 static void sdram_detect_smallest_tRP(struct sys_info * sysinfo)
668 int freq_multiplier = 0;
670 switch (sysinfo->memory_frequency) {
671 case 400: freq_multiplier = 0x14; break; /* 5ns */
672 case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
673 case 667: freq_multiplier = 0x0c; break; /* 3ns */
676 tRP_cycles = 2; /* 2 clocks minimum */
677 tRP_time = tRP_cycles * freq_multiplier;
679 for (i=0; i<2*DIMM_SOCKETS; i++) {
682 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
685 reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ROW_PRECHARGE_TIME);
687 die("Invalid tRP value.\n");
690 while (tRP_time < reg8) {
691 tRP_time += freq_multiplier;
697 die("DDR-II Module does not support this frequency (tRP error)\n");
700 printk(BIOS_DEBUG, "tRP = %d cycles\n", tRP_cycles);
701 sysinfo->trp = tRP_cycles;
704 static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
709 int freq_multiplier = 0;
711 switch (sysinfo->memory_frequency) {
712 case 400: freq_multiplier = 0x14; break; /* 5ns */
713 case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
714 case 667: freq_multiplier = 0x0c; break; /* 3ns */
717 tRCD_cycles = 2; /* 2 clocks minimum */
718 tRCD_time = tRCD_cycles * freq_multiplier;
720 for (i=0; i<2*DIMM_SOCKETS; i++) {
723 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
726 reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_RAS_TO_CAS_DELAY);
728 die("Invalid tRCD value.\n");
731 while (tRCD_time < reg8) {
732 tRCD_time += freq_multiplier;
736 if(tRCD_cycles > 6) {
737 die("DDR-II Module does not support this frequency (tRCD error)\n");
740 printk(BIOS_DEBUG, "tRCD = %d cycles\n", tRCD_cycles);
741 sysinfo->trcd = tRCD_cycles;
744 static void sdram_detect_smallest_tWR(struct sys_info * sysinfo)
749 int freq_multiplier = 0;
751 switch (sysinfo->memory_frequency) {
752 case 400: freq_multiplier = 0x14; break; /* 5ns */
753 case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
754 case 667: freq_multiplier = 0x0c; break; /* 3ns */
757 tWR_cycles = 2; /* 2 clocks minimum */
758 tWR_time = tWR_cycles * freq_multiplier;
760 for (i=0; i<2*DIMM_SOCKETS; i++) {
763 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
766 reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_WRITE_RECOVERY_TIME);
768 die("Invalid tWR value.\n");
771 while (tWR_time < reg8) {
772 tWR_time += freq_multiplier;
777 die("DDR-II Module does not support this frequency (tWR error)\n");
780 printk(BIOS_DEBUG, "tWR = %d cycles\n", tWR_cycles);
781 sysinfo->twr = tWR_cycles;
784 static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
788 const u8 tRFC_cycles[] = {
790 15, 21, 26, /* DDR2-400 */
791 20, 28, 34, /* DDR2-533 */
792 25, 35, 43 /* DDR2-667 */
795 for (i=0; i<2*DIMM_SOCKETS; i++) {
798 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
801 reg8 = sysinfo->banksize[i*2];
803 case 0x04: reg8 = 0; break;
804 case 0x08: reg8 = 1; break;
805 case 0x10: reg8 = 2; break;
806 case 0x20: reg8 = 3; break;
809 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS || sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
813 /* Can this happen? Go back to 127.5ns just to be sure
814 * we don't run out of the array. This may be wrong
816 printk(BIOS_DEBUG, "DIMM %d is 1Gb x16.. Please report.\n", i);
825 switch (sysinfo->memory_frequency) {
826 case 667: index += 3; /* Fallthrough */
827 case 533: index += 3; /* Fallthrough */
831 sysinfo->trfc = tRFC_cycles[index];
832 printk(BIOS_DEBUG, "tRFC = %d cycles\n", tRFC_cycles[index]);
835 static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
839 sysinfo->refresh = 0;
841 for (i=0; i<2*DIMM_SOCKETS; i++) {
844 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
847 refresh = spd_read_byte(get_dimm_spd_address(sysinfo, i),
848 SPD_REFRESH) & ~(1 << 7);
854 /* Refresh is slower than 15.6us, use 15.6us */
859 sysinfo->refresh = 1;
863 die("DDR-II module has unsupported refresh value\n");
865 printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
868 static void sdram_verify_burst_length(struct sys_info * sysinfo)
872 for (i=0; i<2*DIMM_SOCKETS; i++) {
873 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
876 if (!(spd_read_byte(get_dimm_spd_address(sysinfo, i),
877 SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
878 die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n");
882 static void sdram_program_dram_width(struct sys_info * sysinfo)
884 u16 c0dramw=0, c1dramw=0;
887 if (sysinfo->dual_channel)
892 switch (sysinfo->dimm[0]) {
893 case 0: c0dramw = 0x0000; break; /* x16DS */
894 case 1: c0dramw = 0x0001; break; /* x8DS */
895 case 2: c0dramw = 0x0000; break; /* x16SS */
896 case 3: c0dramw = 0x0005; break; /* x8DDS */
897 case 4: c0dramw = 0x0000; break; /* NC */
900 switch (sysinfo->dimm[idx]) {
901 case 0: c1dramw = 0x0000; break; /* x16DS */
902 case 1: c1dramw = 0x0010; break; /* x8DS */
903 case 2: c1dramw = 0x0000; break; /* x16SS */
904 case 3: c1dramw = 0x0050; break; /* x8DDS */
905 case 4: c1dramw = 0x0000; break; /* NC */
908 if ( !sdram_capabilities_dual_channel() ) {
914 MCHBAR16(C0DRAMW) = c0dramw;
915 MCHBAR16(C1DRAMW) = c1dramw;
918 static void sdram_write_slew_rates(u32 offset, const u32 *slew_rate_table)
923 MCHBAR32(offset+(i*4)) = slew_rate_table[i];
926 static const u32 dq2030[] = {
927 0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
928 0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
929 0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
930 0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
933 static const u32 dq2330[] = {
934 0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
935 0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
936 0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
937 0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
940 static const u32 cmd2710[] = {
941 0x07060605, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
942 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
943 0x1110100f, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
944 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
947 static const u32 cmd3210[] = {
948 0x0f0d0b0a, 0x17151311, 0x1f1d1b19, 0x1f1f1f1f,
949 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
950 0x18171615, 0x1f1f1c1a, 0x1f1f1f1f, 0x1f1f1f1f,
951 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
954 static const u32 clk2030[] = {
955 0x0e0d0d0c, 0x100f0f0e, 0x100f0e0d, 0x15131211,
956 0x1d1b1917, 0x2523211f, 0x2a282927, 0x32302e2c,
957 0x17161514, 0x1b1a1918, 0x1f1e1d1c, 0x23222120,
958 0x27262524, 0x2d2b2928, 0x3533312f, 0x3d3b3937
961 static const u32 ctl3215[] = {
962 0x01010000, 0x03020101, 0x07060504, 0x0b0a0908,
963 0x100f0e0d, 0x14131211, 0x18171615, 0x1c1b1a19,
964 0x05040403, 0x07060605, 0x0a090807, 0x0f0d0c0b,
965 0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d
968 static const u32 ctl3220[] = {
969 0x05040403, 0x07060505, 0x0e0c0a08, 0x1a171411,
970 0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e,
971 0x09080807, 0x0b0a0a09, 0x0f0d0c0b, 0x1b171311,
972 0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e
975 static const u32 nc[] = {
976 0x00000000, 0x00000000, 0x00000000, 0x00000000,
977 0x00000000, 0x00000000, 0x00000000, 0x00000000,
978 0x00000000, 0x00000000, 0x00000000, 0x00000000,
979 0x00000000, 0x00000000, 0x00000000, 0x00000000
993 static const u8 dual_channel_slew_group_lookup[] = {
994 DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
995 DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
996 DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210,
997 DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710,
998 DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC,
1000 DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
1001 DQ2030, CMD3210, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210,
1002 DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
1003 DQ2030, CMD3210, CTL3215, NC, CLK2030, NC, DQ2030, CMD2710,
1004 DQ2030, CMD3210, CTL3215, NC, CLK2030, NC, NC, NC,
1006 DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210,
1007 DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
1008 DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210,
1009 DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710,
1010 DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC,
1012 DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
1013 DQ2030, CMD2710, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210,
1014 DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
1015 DQ2030, CMD2710, CTL3215, NC, CLK2030, NC, DQ2030, CMD2710,
1016 DQ2030, CMD2710, CTL3215, NC, CLK2030, NC, NC, NC,
1018 NC, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210,
1019 NC, NC, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210,
1020 NC, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210,
1021 NC, NC, CTL3215, NC, CLK2030, CLK2030, DQ2030, CMD2710
1024 static const u8 single_channel_slew_group_lookup[] = {
1025 DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1026 DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1027 DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, DQ2330, CMD3210,
1028 DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1029 DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC,
1031 DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1032 DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210,
1033 DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1034 DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210,
1035 DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, NC, NC,
1037 DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, DQ2330, CMD3210,
1038 DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1039 DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, DQ2330, CMD3210,
1040 DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1041 DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC,
1043 DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1044 DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210,
1045 DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1046 DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210,
1047 DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, NC, NC,
1049 DQ2330, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210,
1050 DQ2330, NC, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210,
1051 DQ2330, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210,
1052 DQ2330, NC, CTL3215, NC, CLK2030, CLK2030, DQ2030, CMD3210
1055 static const u32 *slew_group_lookup(int dual_channel, int index)
1057 const u8 *slew_group;
1058 /* Dual Channel needs different tables. */
1060 slew_group = dual_channel_slew_group_lookup;
1062 slew_group = single_channel_slew_group_lookup;
1064 switch (slew_group[index]) {
1065 case DQ2030: return dq2030;
1066 case DQ2330: return dq2330;
1067 case CMD2710: return cmd2710;
1068 case CMD3210: return cmd3210;
1069 case CLK2030: return clk2030;
1070 case CTL3215: return ctl3215;
1071 case CTL3220: return ctl3220;
1078 #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
1079 /* Strength multiplier tables */
1080 static const u8 dual_channel_strength_multiplier[] = {
1081 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1082 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1083 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1084 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
1085 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1086 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1087 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1088 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1089 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
1090 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1091 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1092 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1093 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1094 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
1095 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1096 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1097 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1098 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1099 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
1100 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1101 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1102 0x00, 0x00, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1103 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1104 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x44, 0x22
1107 static const u8 single_channel_strength_multiplier[] = {
1108 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1109 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1110 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1111 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1112 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1113 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1114 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1115 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1116 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1117 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1118 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1119 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1120 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1121 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1122 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1123 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1124 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1125 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1126 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1127 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1128 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1129 0x33, 0x00, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1130 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1131 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
1133 #elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
1134 static const u8 dual_channel_strength_multiplier[] = {
1135 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1136 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1137 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1138 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1139 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1140 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1141 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1142 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1143 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1144 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1145 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1146 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1147 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1148 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1149 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1150 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1151 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1152 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1153 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1154 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1155 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1156 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1157 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1158 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33
1161 static const u8 single_channel_strength_multiplier[] = {
1162 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1163 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1164 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1165 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1166 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1167 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1168 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1169 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1170 0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1171 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1172 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1173 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1174 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1175 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1176 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1177 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1178 0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1179 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1180 0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1181 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1182 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1183 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1184 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1185 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00
1189 static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
1191 const u8 * strength_multiplier;
1192 int idx, dual_channel;
1194 /* Set Strength Multipliers */
1196 /* Dual Channel needs different tables. */
1197 if (sdram_capabilities_dual_channel()) {
1198 printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n");
1199 strength_multiplier = dual_channel_strength_multiplier;
1201 idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[2];
1203 printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n");
1204 strength_multiplier = single_channel_strength_multiplier;
1206 idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1];
1209 printk(BIOS_DEBUG, "Table Index: %d\n", idx);
1211 MCHBAR8(G1SC) = strength_multiplier[idx * 8 + 0];
1212 MCHBAR8(G2SC) = strength_multiplier[idx * 8 + 1];
1213 MCHBAR8(G3SC) = strength_multiplier[idx * 8 + 2];
1214 MCHBAR8(G4SC) = strength_multiplier[idx * 8 + 3];
1215 MCHBAR8(G5SC) = strength_multiplier[idx * 8 + 4];
1216 MCHBAR8(G6SC) = strength_multiplier[idx * 8 + 5];
1217 MCHBAR8(G7SC) = strength_multiplier[idx * 8 + 6];
1218 MCHBAR8(G8SC) = strength_multiplier[idx * 8 + 7];
1221 sdram_write_slew_rates(G1SRPUT, slew_group_lookup(dual_channel, idx * 8 + 0));
1222 sdram_write_slew_rates(G2SRPUT, slew_group_lookup(dual_channel, idx * 8 + 1));
1223 if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED)) {
1225 sdram_write_slew_rates(G3SRPUT, ctl3220);
1227 sdram_write_slew_rates(G3SRPUT, slew_group_lookup(dual_channel, idx * 8 + 2));
1229 sdram_write_slew_rates(G4SRPUT, slew_group_lookup(dual_channel, idx * 8 + 3));
1230 sdram_write_slew_rates(G5SRPUT, slew_group_lookup(dual_channel, idx * 8 + 4));
1231 sdram_write_slew_rates(G6SRPUT, slew_group_lookup(dual_channel, idx * 8 + 5));
1234 if (sysinfo->dual_channel) {
1235 sdram_write_slew_rates(G7SRPUT, slew_group_lookup(dual_channel, idx * 8 + 6));
1236 sdram_write_slew_rates(G8SRPUT, slew_group_lookup(dual_channel, idx * 8 + 7));
1238 sdram_write_slew_rates(G7SRPUT, nc);
1239 sdram_write_slew_rates(G8SRPUT, nc);
1243 static void sdram_enable_rcomp(void)
1246 /* Enable Global Periodic RCOMP */
1248 reg32 = MCHBAR32(GBRCOMPCTL);
1249 reg32 &= ~(1 << 23);
1250 MCHBAR32(GBRCOMPCTL) = reg32;
1253 static void sdram_program_dll_timings(struct sys_info *sysinfo)
1255 u32 chan0dll = 0, chan1dll = 0;
1258 printk(BIOS_DEBUG, "Programming DLL Timings... \n");
1260 MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) );
1261 MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
1263 /* We drive both channels with the same speed */
1264 switch (sysinfo->memory_frequency) {
1265 case 400: chan0dll = 0x26262626; chan1dll=0x26262626; break; /* 400MHz */
1266 case 533: chan0dll = 0x22222222; chan1dll=0x22222222; break; /* 533MHz */
1267 case 667: chan0dll = 0x11111111; chan1dll=0x11111111; break; /* 667MHz */
1270 for (i=0; i < 4; i++) {
1271 MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = chan0dll;
1272 MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = chan0dll;
1273 MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = chan1dll;
1274 MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = chan1dll;
1278 static void sdram_force_rcomp(void)
1283 reg32 = MCHBAR32(ODTC);
1285 MCHBAR32(ODTC) = reg32;
1287 reg32 = MCHBAR32(SMSRCTL);
1289 MCHBAR32(SMSRCTL) = reg32;
1291 /* Start initial RCOMP */
1292 reg32 = MCHBAR32(GBRCOMPCTL);
1294 MCHBAR32(GBRCOMPCTL) = reg32;
1296 reg8 = i945_silicon_revision();
1297 if ((reg8 == 0 && (MCHBAR32(DCC) & (3 << 0)) == 0) || (reg8 == 1)) {
1299 reg32 = MCHBAR32(GBRCOMPCTL);
1301 MCHBAR32(GBRCOMPCTL) = reg32;
1305 static void sdram_initialize_system_memory_io(struct sys_info *sysinfo)
1310 printk(BIOS_DEBUG, "Initializing System Memory IO... \n");
1311 /* Enable Data Half Clock Pushout */
1312 reg8 = MCHBAR8(C0HCTC);
1315 MCHBAR8(C0HCTC) = reg8;
1317 reg8 = MCHBAR8(C1HCTC);
1320 MCHBAR8(C1HCTC) = reg8;
1322 MCHBAR16(WDLLBYPMODE) &= ~( (1 << 9) | (1 << 6) | (1 << 4) | (1 << 3) | (1 << 1) );
1323 MCHBAR16(WDLLBYPMODE) |= (1 << 8) | (1 << 7) | (1 << 5) | (1 << 2) | (1 << 0);
1325 MCHBAR8(C0WDLLCMC) = 0;
1326 MCHBAR8(C1WDLLCMC) = 0;
1328 /* Program RCOMP Settings */
1329 sdram_program_dram_width(sysinfo);
1331 sdram_rcomp_buffer_strength_and_slew(sysinfo);
1333 /* Indicate that RCOMP programming is done */
1334 reg32 = MCHBAR32(GBRCOMPCTL);
1335 reg32 &= ~( (1 << 29) | (1 << 26) | (3 << 21) | (3 << 2) );
1336 reg32 |= (3 << 27) | (3 << 0);
1337 MCHBAR32(GBRCOMPCTL) = reg32;
1339 MCHBAR32(GBRCOMPCTL) |= (1 << 10);
1341 /* Program DLL Timings */
1342 sdram_program_dll_timings(sysinfo);
1344 /* Force RCOMP cycle */
1345 sdram_force_rcomp();
1348 static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
1352 printk(BIOS_DEBUG, "Enabling System Memory IO... \n");
1354 reg32 = MCHBAR32(RCVENMT);
1355 reg32 &= ~(0x3f << 6);
1356 MCHBAR32(RCVENMT) = reg32; /* [11:6] = 0 */
1358 reg32 |= (1 << 11) | (1 << 9);
1359 MCHBAR32(RCVENMT) = reg32;
1361 reg32 = MCHBAR32(DRTST);
1362 reg32 |= (1 << 3) | (1 << 2);
1363 MCHBAR32(DRTST) = reg32;
1365 reg32 = MCHBAR32(DRTST);
1366 reg32 |= (1 << 6) | (1 << 4);
1367 MCHBAR32(DRTST) = reg32;
1369 asm volatile ("nop; nop;" ::: "memory");
1371 reg32 = MCHBAR32(DRTST);
1373 /* Is channel 0 populated? */
1374 if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1375 sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
1376 reg32 |= (1 << 7) | (1 << 5);
1380 /* Is channel 1 populated? */
1381 if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1382 sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
1383 reg32 |= (1 << 9) | (1 << 8);
1387 MCHBAR32(DRTST) = reg32;
1389 /* Activate DRAM Channel IO Buffers */
1390 if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1391 sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) {
1392 reg32 = MCHBAR32(C0DRC1);
1394 MCHBAR32(C0DRC1) = reg32;
1396 if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1397 sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) {
1398 reg32 = MCHBAR32(C1DRC1);
1400 MCHBAR32(C1DRC1) = reg32;
1405 unsigned long side1;
1406 unsigned long side2;
1409 static struct dimm_size sdram_get_dimm_size(struct sys_info *sysinfo, u16 dimmno)
1411 /* Calculate the log base 2 size of a DIMM in bits */
1412 struct dimm_size sz;
1413 int value, low, rows, columns, device;
1415 device = get_dimm_spd_address(sysinfo, dimmno);
1419 rows = spd_read_byte(device, SPD_NUM_ROWS); /* rows */
1420 if (rows < 0) goto hw_err;
1421 if ((rows & 0xf) == 0) goto val_err;
1422 sz.side1 += rows & 0xf;
1424 columns = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */
1425 if (columns < 0) goto hw_err;
1426 if ((columns & 0xf) == 0) goto val_err;
1427 sz.side1 += columns & 0xf;
1429 value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); /* banks */
1430 if (value < 0) goto hw_err;
1431 if ((value & 0xff) == 0) goto val_err;
1432 sz.side1 += log2(value & 0xff);
1434 /* Get the module data width and convert it to a power of two */
1435 value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB); /* (high byte) */
1436 if (value < 0) goto hw_err;
1440 low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* (low byte) */
1441 if (low < 0) goto hw_err;
1442 value = value | (low & 0xff);
1443 if ((value != 72) && (value != 64)) goto val_err;
1444 sz.side1 += log2(value);
1447 value = spd_read_byte(device, SPD_NUM_DIMM_BANKS); /* number of physical banks */
1449 if (value < 0) goto hw_err;
1452 if (value == 1) goto out;
1453 if (value != 2) goto val_err;
1455 /* Start with the symmetrical case */
1456 sz.side2 = sz.side1;
1458 if ((rows & 0xf0) == 0) goto out; /* If symmetrical we are done */
1460 /* Don't die here, I have not come across any of these to test what
1463 printk(BIOS_ERR, "Assymetric DIMMs are not supported by this chipset\n");
1465 sz.side2 -= (rows & 0x0f); /* Subtract out rows on side 1 */
1466 sz.side2 += ((rows >> 4) & 0x0f); /* Add in rows on side 2 */
1468 sz.side2 -= (columns & 0x0f); /* Subtract out columns on side 1 */
1469 sz.side2 += ((columns >> 4) & 0x0f); /* Add in columns on side 2 */
1474 die("Bad SPD value\n");
1476 /* If a hardware error occurs the spd rom probably does not exist.
1477 * In this case report that there is no memory
1485 static void sdram_detect_dimm_size(struct sys_info * sysinfo)
1489 for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1490 struct dimm_size sz;
1492 sysinfo->banksize[i * 2] = 0;
1493 sysinfo->banksize[(i * 2) + 1] = 0;
1495 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1498 sz = sdram_get_dimm_size(sysinfo, i);
1500 sysinfo->banks[i] = spd_read_byte(get_dimm_spd_address(sysinfo, i),
1501 SPD_NUM_BANKS_PER_SDRAM); /* banks */
1504 die("DDR-II rank size smaller than 128MB is not supported.\n");
1506 sysinfo->banksize[i * 2] = 1 << (sz.side1 - 28);
1508 printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
1513 /* If there is a second side, it has to have at least 128M, too */
1515 die("DDR-II rank size smaller than 128MB is not supported.\n");
1517 sysinfo->banksize[(i * 2) + 1] = 1 << (sz.side2 - 28);
1519 printk(BIOS_DEBUG, "DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
1523 static int sdram_program_row_boundaries(struct sys_info *sysinfo)
1526 int cum0, cum1, tolud, tom;
1528 printk(BIOS_DEBUG, "Setting RAM size... \n");
1531 for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1532 cum0 += sysinfo->banksize[i];
1533 MCHBAR8(C0DRB0+i) = cum0;
1536 /* Assume we continue in Channel 1 where we stopped in Channel 0 */
1539 /* Exception: Interleaved starts from the beginning */
1540 if (sysinfo->interleaved)
1544 /* Exception: Channel 1 is not populated. C1DRB stays zero */
1545 if (sysinfo->dimm[2] == SYSINFO_DIMM_NOT_POPULATED &&
1546 sysinfo->dimm[3] == SYSINFO_DIMM_NOT_POPULATED)
1550 for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1551 cum1 += sysinfo->banksize[i + 4];
1552 MCHBAR8(C1DRB0+i) = cum1;
1555 /* Set TOLUD Top Of Low Usable DRAM */
1556 if (sysinfo->interleaved)
1557 tolud = (cum0 + cum1) << 1;
1559 tolud = (cum1 ? cum1 : cum0) << 1;
1561 /* The TOM register has a different format */
1564 /* Limit the value of TOLUD to leave some space for PCI memory. */
1566 tolud = 0xd0; /* 3.25GB : 0.75GB */
1568 pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);
1570 printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
1571 printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
1572 printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
1574 pci_write_config16(PCI_DEV(0,0,0), TOM, tom);
1579 static int sdram_set_row_attributes(struct sys_info *sysinfo)
1582 u16 dra0=0, dra1=0, dra = 0;
1584 printk(BIOS_DEBUG, "Setting row attributes... \n");
1585 for(i=0; i < 2 * DIMM_SOCKETS; i++) {
1589 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
1593 device = get_dimm_spd_address(sysinfo, i);
1595 value = spd_read_byte(device, SPD_NUM_ROWS); /* rows */
1596 columnsrows = (value & 0x0f);
1598 value = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */
1599 columnsrows |= (value & 0xf) << 4;
1601 switch (columnsrows) {
1602 case 0x9d: dra = 2; break;
1603 case 0xad: dra = 3; break;
1604 case 0xbd: dra = 4; break;
1605 case 0xae: dra = 3; break;
1606 case 0xbe: dra = 4; break;
1607 default: die("Unsupported Rows/Columns. (DRA)");
1610 /* Double Sided DIMMs? */
1611 if (sysinfo->banksize[(2 * i) + 1] != 0) {
1612 dra = (dra << 4) | dra;
1615 if (i < DIMM_SOCKETS)
1616 dra0 |= (dra << (i*8));
1618 dra1 |= (dra << ((i - DIMM_SOCKETS)*8));
1621 MCHBAR16(C0DRA0) = dra0;
1622 MCHBAR16(C1DRA0) = dra1;
1624 printk(BIOS_DEBUG, "C0DRA = 0x%04x\n", dra0);
1625 printk(BIOS_DEBUG, "C1DRA = 0x%04x\n", dra1);
1630 static void sdram_set_bank_architecture(struct sys_info *sysinfo)
1635 MCHBAR16(C1BNKARC) &= 0xff00;
1636 MCHBAR16(C0BNKARC) &= 0xff00;
1639 for (i=0; i < 2 * DIMM_SOCKETS; i++) {
1640 /* Switch to second channel */
1641 if (i == DIMM_SOCKETS)
1644 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1647 if (sysinfo->banks[i] != 8)
1650 printk(BIOS_SPEW, "DIMM%d has 8 banks.\n", i);
1653 MCHBAR16(off32) |= 0x50;
1655 MCHBAR16(off32) |= 0x05;
1659 #define REFRESH_7_8US 1
1660 #define REFRESH_15_6US 0
1661 static void sdram_program_refresh_rate(struct sys_info *sysinfo)
1665 if (sysinfo->refresh == REFRESH_7_8US) {
1666 reg32 = (2 << 8); /* Refresh enabled at 7.8us */
1668 reg32 = (1 << 8); /* Refresh enabled at 15.6us */
1671 MCHBAR32(C0DRC0) &= ~(7 << 8);
1672 MCHBAR32(C0DRC0) |= reg32;
1674 MCHBAR32(C1DRC0) &= ~(7 << 8);
1675 MCHBAR32(C1DRC0) |= reg32;
1678 static void sdram_program_cke_tristate(struct sys_info *sysinfo)
1683 reg32 = MCHBAR32(C0DRC1);
1685 for (i=0; i < 4; i++) {
1686 if (sysinfo->banksize[i] == 0) {
1687 reg32 |= (1 << (16 + i));
1694 MCHBAR32(C0DRC1) = reg32;
1696 /* Do we have to do this if we're in Single Channel Mode? */
1697 reg32 = MCHBAR32(C1DRC1);
1699 for (i=4; i < 8; i++) {
1700 if (sysinfo->banksize[i] == 0) {
1701 reg32 |= (1 << (12 + i));
1708 MCHBAR32(C1DRC1) = reg32;
1711 static void sdram_program_odt_tristate(struct sys_info *sysinfo)
1716 reg32 = MCHBAR32(C0DRC2);
1718 for (i=0; i < 4; i++) {
1719 if (sysinfo->banksize[i] == 0) {
1720 reg32 |= (1 << (24 + i));
1723 MCHBAR32(C0DRC2) = reg32;
1725 reg32 = MCHBAR32(C1DRC2);
1727 for (i=4; i < 8; i++) {
1728 if (sysinfo->banksize[i] == 0) {
1729 reg32 |= (1 << (20 + i));
1732 MCHBAR32(C1DRC2) = reg32;
1735 static void sdram_set_timing_and_control(struct sys_info *sysinfo)
1742 static const u8 const drt0_table[] = {
1744 3, 4, 5, /* FSB533/400, DDR533/400 */
1745 4, 5, 6, /* FSB667, DDR533/400 */
1746 4, 5, 6, /* FSB667, DDR667 */
1749 static const u8 const cas_table[] = {
1753 reg32 = MCHBAR32(C0DRC0);
1754 reg32 |= (1 << 2); /* Burst Length 8 */
1755 reg32 &= ~( (1 << 13) | (1 << 12) );
1756 MCHBAR32(C0DRC0) = reg32;
1758 reg32 = MCHBAR32(C1DRC0);
1759 reg32 |= (1 << 2); /* Burst Length 8 */
1760 reg32 &= ~( (1 << 13) | (1 << 12) );
1761 MCHBAR32(C1DRC0) = reg32;
1763 if (!sysinfo->dual_channel && sysinfo->dimm[1] !=
1764 SYSINFO_DIMM_NOT_POPULATED) {
1765 reg32 = MCHBAR32(C0DRC0);
1767 MCHBAR32(C0DRC0) = reg32;
1770 sdram_program_refresh_rate(sysinfo);
1772 sdram_program_cke_tristate(sysinfo);
1774 sdram_program_odt_tristate(sysinfo);
1776 /* Calculate DRT0 */
1780 /* B2B Write Precharge (same bank) = CL-1 + BL/2 + tWR */
1781 reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + sysinfo->twr;
1782 temp_drt |= (reg32 << 28);
1784 /* Write Auto Precharge (same bank) = CL-1 + BL/2 + tWR + tRP */
1785 reg32 += sysinfo->trp;
1786 temp_drt |= (reg32 << 4);
1788 if (sysinfo->memory_frequency == 667) {
1789 tWTR = 3; /* 667MHz */
1791 tWTR = 2; /* 400 and 533 */
1794 /* B2B Write to Read Command Spacing */
1795 reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + tWTR;
1796 temp_drt |= (reg32 << 24);
1798 /* CxDRT0 [23:22], [21:20], [19:18] [16] have fixed values */
1799 temp_drt |= ( (1 << 22) | (3 << 20) | (1 << 18) | (0 << 16) );
1801 /* Program Write Auto Precharge to Activate */
1803 if (sysinfo->fsb_frequency == 667) { /* 667MHz FSB */
1806 if (sysinfo->memory_frequency == 667) {
1809 off32 += sysinfo->cas - 3;
1810 reg32 = drt0_table[off32];
1811 temp_drt |= (reg32 << 11);
1813 /* Read Auto Precharge to Activate */
1815 temp_drt |= (8 << 0);
1817 MCHBAR32(C0DRT0) = temp_drt;
1818 MCHBAR32(C1DRT0) = temp_drt;
1820 /* Calculate DRT1 */
1822 temp_drt = MCHBAR32(C0DRT1) & 0x00020088;
1824 /* DRAM RASB Precharge */
1825 temp_drt |= (sysinfo->trp - 2) << 0;
1827 /* DRAM RASB to CASB Delay */
1828 temp_drt |= (sysinfo->trcd - 2) << 4;
1831 temp_drt |= (cas_table[sysinfo->cas - 3]) << 8;
1833 /* Refresh Cycle Time */
1834 temp_drt |= (sysinfo->trfc) << 10;
1836 /* Pre-All to Activate Delay */
1837 temp_drt |= (0 << 16);
1839 /* Precharge to Precharge Delay stays at 1 clock */
1840 temp_drt |= (0 << 18);
1842 /* Activate to Precharge Delay */
1843 temp_drt |= (sysinfo->tras << 19);
1845 /* Read to Precharge (tRTP) */
1846 if (sysinfo->memory_frequency == 667) {
1847 temp_drt |= (1 << 28);
1849 temp_drt |= (0 << 28);
1852 /* Determine page size */
1854 page_size = 1; /* Default: 1k pagesize */
1855 for (i=0; i< 2*DIMM_SOCKETS; i++) {
1856 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS ||
1857 sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
1858 page_size = 2; /* 2k pagesize */
1861 if (sysinfo->memory_frequency == 533 && page_size == 2) {
1864 if (sysinfo->memory_frequency == 667) {
1868 temp_drt |= (reg32 << 30);
1870 MCHBAR32(C0DRT1) = temp_drt;
1871 MCHBAR32(C1DRT1) = temp_drt;
1874 reg32 = MCHBAR32(C0DRT2);
1876 MCHBAR32(C0DRT2) = reg32;
1878 reg32 = MCHBAR32(C1DRT2);
1880 MCHBAR32(C1DRT2) = reg32;
1882 /* Calculate DRT3 */
1883 temp_drt = MCHBAR32(C0DRT3) & ~0x07ffffff;
1885 /* Get old tRFC value */
1886 reg32 = MCHBAR32(C0DRT1) >> 10;
1890 switch (sysinfo->memory_frequency) {
1892 reg32 = ((78800 / 500) - reg32) & 0x1ff;
1893 reg32 |= (0x8c << 16) | (0x0c << 10); /* 1 us */
1895 case 533: /* 3.75nS */
1896 reg32 = ((78800 / 375) - reg32) & 0x1ff;
1897 reg32 |= (0xba << 16) | (0x10 << 10); /* 1 us */
1900 reg32 = ((78800 / 300) - reg32) & 0x1ff;
1901 reg32 |= (0xe9 << 16) | (0x14 << 10); /* 1 us */
1907 MCHBAR32(C0DRT3) = temp_drt;
1908 MCHBAR32(C1DRT3) = temp_drt;
1911 static void sdram_set_channel_mode(struct sys_info *sysinfo)
1915 printk(BIOS_DEBUG, "Setting mode of operation for memory channels...");
1917 if (sdram_capabilities_interleave() &&
1918 ( ( sysinfo->banksize[0] + sysinfo->banksize[1] +
1919 sysinfo->banksize[2] + sysinfo->banksize[3] ) ==
1920 ( sysinfo->banksize[4] + sysinfo->banksize[5] +
1921 sysinfo->banksize[6] + sysinfo->banksize[7] ) ) ) {
1922 /* Both channels equipped with DIMMs of the same size */
1923 sysinfo->interleaved = 1;
1925 sysinfo->interleaved = 0;
1928 reg32 = MCHBAR32(DCC);
1931 if(sysinfo->interleaved) {
1932 /* Dual Channel Interleaved */
1933 printk(BIOS_DEBUG, "Dual Channel Interleaved.\n");
1935 } else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED &&
1936 sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) {
1937 /* Channel 1 only */
1938 printk(BIOS_DEBUG, "Single Channel 1 only.\n");
1940 } else if (sdram_capabilities_dual_channel() && sysinfo->dimm[2] !=
1941 SYSINFO_DIMM_NOT_POPULATED) {
1942 /* Dual Channel Assymetric */
1943 printk(BIOS_DEBUG, "Dual Channel Assymetric.\n");
1946 /* All bits 0 means Single Channel 0 operation */
1947 printk(BIOS_DEBUG, "Single Channel 0 only.\n");
1950 /* Now disable channel XORing */
1953 MCHBAR32(DCC) = reg32;
1955 PRINTK_DEBUG("DCC=0x%08x\n", MCHBAR32(DCC));
1958 static void sdram_program_pll_settings(struct sys_info *sysinfo)
1962 MCHBAR32(PLLMON) = 0x80800000;
1964 sysinfo->fsb_frequency = fsbclk();
1965 if (sysinfo->fsb_frequency == 0xffff)
1966 die("Unsupported FSB speed");
1968 /* Program CPCTL according to FSB speed */
1969 /* Only write the lower byte */
1970 switch (sysinfo->fsb_frequency) {
1971 case 400: MCHBAR8(CPCTL) = 0x90; break; /* FSB400 */
1972 case 533: MCHBAR8(CPCTL) = 0x95; break; /* FSB533 */
1973 case 667: MCHBAR8(CPCTL) = 0x8d; break; /* FSB667 */
1976 MCHBAR16(CPCTL) &= ~(1 << 11);
1978 reg16 = MCHBAR16(CPCTL); /* Read back register to activate settings */
1981 static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
1985 u8 freq, second_vco, voltage;
1987 #define CRCLK_166MHz 0x00
1988 #define CRCLK_200MHz 0x01
1989 #define CRCLK_250MHz 0x03
1990 #define CRCLK_400MHz 0x05
1992 #define CDCLK_200MHz 0x00
1993 #define CDCLK_320MHz 0x40
1995 #define VOLTAGE_1_05 0x00
1996 #define VOLTAGE_1_50 0x01
1998 printk(BIOS_DEBUG, "Setting Graphics Frequency... \n");
2000 printk(BIOS_DEBUG, "FSB: %d MHz ", sysinfo->fsb_frequency);
2002 voltage = VOLTAGE_1_05;
2003 if (MCHBAR32(DFT_STRAP1) & (1 << 20))
2004 voltage = VOLTAGE_1_50;
2005 printk(BIOS_DEBUG, "Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
2007 /* Gate graphics hardware for frequency change */
2008 reg8 = pci_read_config16(PCI_DEV(0,2,0), GCFC + 1);
2009 reg8 = (1<<3) | (1<<1); /* disable crclk, gate cdclk */
2010 pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2012 /* Get graphics frequency capabilities */
2013 reg8 = sdram_capabilities_core_frequencies();
2015 freq = CRCLK_250MHz;
2017 case GFX_FREQUENCY_CAP_ALL:
2018 if (voltage == VOLTAGE_1_05)
2019 freq = CRCLK_250MHz;
2021 freq = CRCLK_400MHz; /* 1.5V requires 400MHz */
2023 case GFX_FREQUENCY_CAP_250MHZ: freq = CRCLK_250MHz; break;
2024 case GFX_FREQUENCY_CAP_200MHZ: freq = CRCLK_200MHz; break;
2025 case GFX_FREQUENCY_CAP_166MHZ: freq = CRCLK_166MHz; break;
2028 if (freq != CRCLK_400MHz) {
2029 /* What chipset are we? Force 166MHz for GMS */
2030 reg8 = (pci_read_config8(PCI_DEV(0, 0x00,0), 0xe7) & 0x70) >> 4;
2032 freq = CRCLK_166MHz;
2035 printk(BIOS_DEBUG, "Render: ");
2037 case CRCLK_166MHz: printk(BIOS_DEBUG, "166Mhz"); break;
2038 case CRCLK_200MHz: printk(BIOS_DEBUG, "200Mhz"); break;
2039 case CRCLK_250MHz: printk(BIOS_DEBUG, "250Mhz"); break;
2040 case CRCLK_400MHz: printk(BIOS_DEBUG, "400Mhz"); break;
2043 if (i945_silicon_revision() == 0) {
2044 sysinfo->mvco4x = 1;
2046 sysinfo->mvco4x = 0;
2051 if (voltage == VOLTAGE_1_50) {
2053 } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz)) {
2054 u16 mem = sysinfo->memory_frequency;
2055 u16 fsb = sysinfo->fsb_frequency;
2057 if ( (fsb == 667 && mem == 533) ||
2058 (fsb == 533 && mem == 533) ||
2059 (fsb == 533 && mem == 400)) {
2063 if (fsb == 667 && mem == 533)
2064 sysinfo->mvco4x = 1;
2068 sysinfo->clkcfg_bit7=1;
2070 sysinfo->clkcfg_bit7=0;
2073 /* Graphics Core Render Clock */
2074 reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC);
2075 reg16 &= ~( (7 << 0) | (1 << 13) );
2077 pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
2079 /* Graphics Core Display Clock */
2080 reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC);
2081 reg8 &= ~( (1<<7) | (7<<4) );
2083 if (voltage == VOLTAGE_1_05) {
2084 reg8 |= CDCLK_200MHz;
2085 printk(BIOS_DEBUG, " Display: 200MHz\n");
2087 reg8 |= CDCLK_320MHz;
2088 printk(BIOS_DEBUG, " Display: 320MHz\n");
2090 pci_write_config8(PCI_DEV(0,2,0), GCFC, reg8);
2092 reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC + 1);
2094 reg8 |= (1<<3) | (1<<1);
2095 pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2098 pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2100 /* Ungate core render and display clocks */
2102 pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2105 static void sdram_program_memory_frequency(struct sys_info *sysinfo)
2110 printk(BIOS_DEBUG, "Setting Memory Frequency... ");
2112 clkcfg = MCHBAR32(CLKCFG);
2114 printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", clkcfg);
2116 clkcfg &= ~( (1 << 12) | (1 << 7) | ( 7 << 4) );
2118 if (sysinfo->mvco4x) {
2119 printk(BIOS_DEBUG, "MVCO 4x, ");
2120 clkcfg &= ~(1 << 12);
2123 if (sysinfo->clkcfg_bit7) {
2124 printk(BIOS_DEBUG, "second VCO, ");
2129 switch (sysinfo->memory_frequency) {
2130 case 400: clkcfg |= (2 << 4); break;
2131 case 533: clkcfg |= (3 << 4); break;
2132 case 667: clkcfg |= (4 << 4); break;
2133 default: die("Target Memory Frequency Error");
2136 if (MCHBAR32(CLKCFG) == clkcfg) {
2137 printk(BIOS_DEBUG, "ok (unchanged)\n");
2141 MCHBAR32(CLKCFG) = clkcfg;
2143 /* Make sure the following code is in the
2144 * cache before we execute it.
2148 reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
2150 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
2152 clkcfg &= ~(1 << 10);
2153 MCHBAR32(CLKCFG) = clkcfg;
2154 clkcfg |= (1 << 10);
2155 MCHBAR32(CLKCFG) = clkcfg;
2158 " movl $0x100, %%ecx\n"
2164 " loop delay_update\n"
2170 clkcfg &= ~(1 << 10);
2171 MCHBAR32(CLKCFG) = clkcfg;
2178 printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
2179 printk(BIOS_DEBUG, "ok\n");
2182 static void sdram_program_clock_crossing(void)
2187 * We add the indices according to our clocks from CLKCFG.
2189 #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
2190 static const u32 data_clock_crossing[] = {
2191 0x00100401, 0x00000000, /* DDR400 FSB400 */
2192 0xffffffff, 0xffffffff, /* nonexistant */
2193 0xffffffff, 0xffffffff, /* nonexistant */
2195 0x08040120, 0x00000000, /* DDR400 FSB533 */
2196 0x00100401, 0x00000000, /* DDR533 FSB533 */
2197 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
2199 0x04020120, 0x00000010, /* DDR400 FSB667 */
2200 0x10040280, 0x00000040, /* DDR533 FSB667 */
2201 0x00100401, 0x00000000, /* DDR667 FSB667 */
2203 0xffffffff, 0xffffffff, /* nonexistant */
2204 0xffffffff, 0xffffffff, /* nonexistant */
2205 0xffffffff, 0xffffffff, /* nonexistant */
2207 0xffffffff, 0xffffffff, /* nonexistant */
2208 0xffffffff, 0xffffffff, /* nonexistant */
2209 0xffffffff, 0xffffffff, /* nonexistant */
2212 static const u32 command_clock_crossing[] = {
2213 0x04020208, 0x00000000, /* DDR400 FSB400 */
2214 0xffffffff, 0xffffffff, /* nonexistant */
2215 0xffffffff, 0xffffffff, /* nonexistant */
2217 0x00060108, 0x00000000, /* DDR400 FSB533 */
2218 0x04020108, 0x00000000, /* DDR533 FSB533 */
2219 0xffffffff, 0xffffffff, /* nonexistant */
2221 0x00040318, 0x00000000, /* DDR400 FSB667 */
2222 0x04020118, 0x00000000, /* DDR533 FSB667 */
2223 0x02010804, 0x00000000, /* DDR667 FSB667 */
2225 0xffffffff, 0xffffffff, /* nonexistant */
2226 0xffffffff, 0xffffffff, /* nonexistant */
2227 0xffffffff, 0xffffffff, /* nonexistant */
2229 0xffffffff, 0xffffffff, /* nonexistant */
2230 0xffffffff, 0xffffffff, /* nonexistant */
2231 0xffffffff, 0xffffffff, /* nonexistant */
2234 #elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
2236 static const u32 data_clock_crossing[] = {
2237 0xffffffff, 0xffffffff, /* nonexistant */
2238 0xffffffff, 0xffffffff, /* nonexistant */
2239 0xffffffff, 0xffffffff, /* nonexistant */
2241 0x10080201, 0x00000000, /* DDR400 FSB533 */
2242 0x00100401, 0x00000000, /* DDR533 FSB533 */
2243 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
2245 0xffffffff, 0xffffffff, /* nonexistant */
2246 0xffffffff, 0xffffffff, /* nonexistant */
2247 0xffffffff, 0xffffffff, /* nonexistant */
2249 0x04020108, 0x00000000, /* DDR400 FSB800 */
2250 0x00020108, 0x00000000, /* DDR533 FSB800 */
2251 0x00080201, 0x00000000, /* DDR667 FSB800 */
2253 0x00010402, 0x00000000, /* DDR400 FSB1066 */
2254 0x04020108, 0x00000000, /* DDR533 FSB1066 */
2255 0x08040110, 0x00000000, /* DDR667 FSB1066 */
2258 static const u32 command_clock_crossing[] = {
2259 0xffffffff, 0xffffffff, /* nonexistant */
2260 0xffffffff, 0xffffffff, /* nonexistant */
2261 0xffffffff, 0xffffffff, /* nonexistant */
2263 0x00010800, 0x00000402, /* DDR400 FSB533 */
2264 0x01000400, 0x00000200, /* DDR533 FSB533 */
2265 0x00020904, 0x00000000, /* DDR667 FSB533 - fake values */
2267 0xffffffff, 0xffffffff, /* nonexistant */
2268 0xffffffff, 0xffffffff, /* nonexistant */
2269 0xffffffff, 0xffffffff, /* nonexistant */
2271 0x02010804, 0x00000000, /* DDR400 FSB800 */
2272 0x00010402, 0x00000000, /* DDR533 FSB800 */
2273 0x04020180, 0x00000008, /* DDR667 FSB800 */
2275 0x00020904, 0x00000000, /* DDR400 FSB1066 */
2276 0x02010804, 0x00000000, /* DDR533 FSB1066 */
2277 0x180601c0, 0x00000020, /* DDR667 FSB1066 */
2281 printk(BIOS_DEBUG, "Programming Clock Crossing...");
2283 printk(BIOS_DEBUG, "MEM=");
2285 case 400: printk(BIOS_DEBUG, "400"); idx += 0; break;
2286 case 533: printk(BIOS_DEBUG, "533"); idx += 2; break;
2287 case 667: printk(BIOS_DEBUG, "667"); idx += 4; break;
2288 default: printk(BIOS_DEBUG, "RSVD %x", memclk()); return;
2291 printk(BIOS_DEBUG, " FSB=");
2293 case 400: printk(BIOS_DEBUG, "400"); idx += 0; break;
2294 case 533: printk(BIOS_DEBUG, "533"); idx += 6; break;
2295 case 667: printk(BIOS_DEBUG, "667"); idx += 12; break;
2296 case 800: printk(BIOS_DEBUG, "800"); idx += 18; break;
2297 case 1066: printk(BIOS_DEBUG, "1066"); idx += 24; break;
2298 default: printk(BIOS_DEBUG, "RSVD %x\n", fsbclk()); return;
2301 if (command_clock_crossing[idx]==0xffffffff) {
2302 printk(BIOS_DEBUG, "Invalid MEM/FSB combination!\n");
2305 MCHBAR32(CCCFT + 0) = command_clock_crossing[idx];
2306 MCHBAR32(CCCFT + 4) = command_clock_crossing[idx + 1];
2308 MCHBAR32(C0DCCFT + 0) = data_clock_crossing[idx];
2309 MCHBAR32(C0DCCFT + 4) = data_clock_crossing[idx + 1];
2310 MCHBAR32(C1DCCFT + 0) = data_clock_crossing[idx];
2311 MCHBAR32(C1DCCFT + 4) = data_clock_crossing[idx + 1];
2313 printk(BIOS_DEBUG, "... ok\n");
2316 static void sdram_disable_fast_dispatch(void)
2320 reg32 = MCHBAR32(FSBPMC3);
2322 MCHBAR32(FSBPMC3) = reg32;
2324 reg32 = MCHBAR32(SBTEST);
2326 MCHBAR32(SBTEST) = reg32;
2329 static void sdram_pre_jedec_initialization(void)
2333 reg32 = MCHBAR32(WCC);
2334 reg32 &= 0x113ff3ff;
2335 reg32 |= (4 << 29) | (3 << 25) | (1 << 10);
2336 MCHBAR32(WCC) = reg32;
2338 MCHBAR32(SMVREFC) |= (1 << 6);
2340 MCHBAR32(MMARB0) &= ~(3 << 17);
2341 MCHBAR32(MMARB0) |= (1 << 21) | (1 << 16);
2343 MCHBAR32(MMARB1) &= ~(7 << 8);
2344 MCHBAR32(MMARB1) |= (3 << 8);
2346 /* Adaptive Idle Timer Control */
2347 MCHBAR32(C0AIT) = 0x000006c4;
2348 MCHBAR32(C0AIT+4) = 0x871a066d;
2350 MCHBAR32(C1AIT) = 0x000006c4;
2351 MCHBAR32(C1AIT+4) = 0x871a066d;
2354 #define EA_DUALCHANNEL_XOR_BANK_RANK_MODE (0xd4 << 24)
2355 #define EA_DUALCHANNEL_XOR_BANK_MODE (0xf4 << 24)
2356 #define EA_DUALCHANNEL_BANK_RANK_MODE (0xc2 << 24)
2357 #define EA_DUALCHANNEL_BANK_MODE (0xe2 << 24)
2358 #define EA_SINGLECHANNEL_XOR_BANK_RANK_MODE (0x91 << 24)
2359 #define EA_SINGLECHANNEL_XOR_BANK_MODE (0xb1 << 24)
2360 #define EA_SINGLECHANNEL_BANK_RANK_MODE (0x80 << 24)
2361 #define EA_SINGLECHANNEL_BANK_MODE (0xa0 << 24)
2363 static void sdram_enhanced_addressing_mode(struct sys_info *sysinfo)
2365 u32 chan0 = 0, chan1 = 0;
2366 int chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated;
2368 chan0_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2369 sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2370 chan1_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2371 sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2372 chan0_dualsided = (sysinfo->banksize[1] || sysinfo->banksize[3]);
2373 chan1_dualsided = (sysinfo->banksize[5] || sysinfo->banksize[7]);
2375 if (sdram_capabilities_enhanced_addressing_xor()) {
2376 if (!sysinfo->interleaved) {
2377 /* Single Channel & Dual Channel Assymetric */
2378 if (chan0_populated) {
2379 if (chan0_dualsided) {
2380 chan0 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2382 chan0 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2385 if (chan1_populated) {
2386 if (chan1_dualsided) {
2387 chan1 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2389 chan1 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2393 /* Interleaved has always both channels populated */
2394 if (chan0_dualsided) {
2395 chan0 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2397 chan0 = EA_DUALCHANNEL_XOR_BANK_MODE;
2400 if (chan1_dualsided) {
2401 chan1 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2403 chan1 = EA_DUALCHANNEL_XOR_BANK_MODE;
2407 if (!sysinfo->interleaved) {
2408 /* Single Channel & Dual Channel Assymetric */
2409 if (chan0_populated) {
2410 if (chan0_dualsided) {
2411 chan0 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2413 chan0 = EA_SINGLECHANNEL_BANK_MODE;
2416 if (chan1_populated) {
2417 if (chan1_dualsided) {
2418 chan1 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2420 chan1 = EA_SINGLECHANNEL_BANK_MODE;
2424 /* Interleaved has always both channels populated */
2425 if (chan0_dualsided) {
2426 chan0 = EA_DUALCHANNEL_BANK_RANK_MODE;
2428 chan0 = EA_DUALCHANNEL_BANK_MODE;
2431 if (chan1_dualsided) {
2432 chan1 = EA_DUALCHANNEL_BANK_RANK_MODE;
2434 chan1 = EA_DUALCHANNEL_BANK_MODE;
2439 MCHBAR32(C0DRC1) &= 0x00ffffff;
2440 MCHBAR32(C0DRC1) |= chan0;
2441 MCHBAR32(C1DRC1) &= 0x00ffffff;
2442 MCHBAR32(C1DRC1) |= chan1;
2445 static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
2449 /* Enable Channel XORing for Dual Channel Interleave */
2450 if (sysinfo->interleaved) {
2452 reg32 = MCHBAR32(DCC);
2453 #if CONFIG_CHANNEL_XOR_RANDOMIZATION
2454 reg32 &= ~(1 << 10);
2459 MCHBAR32(DCC) = reg32;
2462 /* DRAM mode optimizations */
2463 sdram_enhanced_addressing_mode(sysinfo);
2465 reg32 = MCHBAR32(FSBPMC3);
2467 MCHBAR32(FSBPMC3) = reg32;
2469 reg32 = MCHBAR32(SBTEST);
2471 MCHBAR32(SBTEST) = reg32;
2473 reg32 = MCHBAR32(SBOCC);
2474 reg32 &= 0xffbdb6ff;
2475 reg32 |= (0xbdb6 << 8) | (1 << 0);
2476 MCHBAR32(SBOCC) = reg32;
2479 static void sdram_power_management(struct sys_info *sysinfo)
2484 int integrated_graphics = 1;
2487 reg32 = MCHBAR32(C0DRT2);
2488 reg32 &= 0xffffff00;
2489 /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2490 reg32 |= (1 << 5) | (1 << 4);
2491 MCHBAR32(C0DRT2) = reg32;
2493 reg32 = MCHBAR32(C1DRT2);
2494 reg32 &= 0xffffff00;
2495 /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2496 reg32 |= (1 << 5) | (1 << 4);
2497 MCHBAR32(C1DRT2) = reg32;
2499 reg32 = MCHBAR32(C0DRC1);
2501 reg32 |= (1 << 12) | (1 << 11);
2502 MCHBAR32(C0DRC1) = reg32;
2504 reg32 = MCHBAR32(C1DRC1);
2506 reg32 |= (1 << 12) | (1 << 11);
2507 MCHBAR32(C1DRC1) = reg32;
2509 if (i945_silicon_revision()>1) {
2510 /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
2511 u16 peg_bits = (1 << 5) | (1 << 0);
2513 MCHBAR16(UPMC1) = 0x1010 | peg_bits;
2515 /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
2516 u16 peg_bits = (1 << 5) | (1 << 0);
2519 MCHBAR16(UPMC1) = 0x0010 | peg_bits;
2522 reg16 = MCHBAR16(UPMC2);
2525 MCHBAR16(UPMC2) = reg16;
2527 MCHBAR32(UPMC3) = 0x000f06ff;
2529 for (i=0; i<5; i++) {
2530 MCHBAR32(UPMC3) &= ~(1 << 16);
2531 MCHBAR32(UPMC3) |= (1 << 16);
2534 MCHBAR32(GIPMC1) = 0x8000000c;
2536 reg16 = MCHBAR16(CPCTL);
2537 reg16 &= ~(7 << 11);
2538 if (i945_silicon_revision()>2) {
2543 MCHBAR16(CPCTL) = reg16;
2546 if ((MCHBAR32(ECO) & (1 << 16)) != 0) {
2548 if (i945_silicon_revision() != 0) {
2550 switch (sysinfo->fsb_frequency) {
2551 case 667: MCHBAR32(HGIPMC2) = 0x0d590d59; break;
2552 case 533: MCHBAR32(HGIPMC2) = 0x155b155b; break;
2555 switch (sysinfo->fsb_frequency) {
2556 case 667: MCHBAR32(HGIPMC2) = 0x09c409c4; break;
2557 case 533: MCHBAR32(HGIPMC2) = 0x0fa00fa0; break;
2561 MCHBAR32(FSBPMC1) = 0x8000000c;
2563 reg32 = MCHBAR32(C2C3TT);
2564 reg32 &= 0xffff0000;
2565 switch (sysinfo->fsb_frequency) {
2566 case 667: reg32 |= 0x0600; break;
2567 case 533: reg32 |= 0x0480; break;
2569 MCHBAR32(C2C3TT) = reg32;
2571 reg32 = MCHBAR32(C3C4TT);
2572 reg32 &= 0xffff0000;
2573 switch (sysinfo->fsb_frequency) {
2574 case 667: reg32 |= 0x0b80; break;
2575 case 533: reg32 |= 0x0980; break;
2577 MCHBAR32(C3C4TT) = reg32;
2579 if (i945_silicon_revision() == 0) {
2580 MCHBAR32(ECO) &= ~(1 << 16);
2582 MCHBAR32(ECO) |= (1 << 16);
2587 if (i945_silicon_revision() == 0) {
2588 MCHBAR32(FSBPMC3) &= ~(1 << 29);
2590 MCHBAR32(FSBPMC3) |= (1 << 29);
2593 MCHBAR32(FSBPMC3) &= ~(1 << 29);
2595 MCHBAR32(FSBPMC3) |= (1 << 21);
2597 MCHBAR32(FSBPMC3) &= ~(1 << 19);
2599 MCHBAR32(FSBPMC3) &= ~(1 << 13);
2601 reg32 = MCHBAR32(FSBPMC4);
2602 reg32 &= ~(3 << 24);
2603 reg32 |= ( 2 << 24);
2604 MCHBAR32(FSBPMC4) = reg32;
2606 MCHBAR32(FSBPMC4) |= (1 << 21);
2608 MCHBAR32(FSBPMC4) |= (1 << 5);
2610 if ((i945_silicon_revision() < 2) /* || cpuid() = 0x6e8 */ ) {
2611 /* stepping 0 and 1 or CPUID 6e8 */
2612 MCHBAR32(FSBPMC4) &= ~(1 << 4);
2614 MCHBAR32(FSBPMC4) |= (1 << 4);
2617 reg8 = pci_read_config8(PCI_DEV(0,0x0,0), 0xfc);
2619 pci_write_config8(PCI_DEV(0, 0x0, 0), 0xfc, reg8);
2621 reg8 = pci_read_config8(PCI_DEV(0,0x2,0), 0xc1);
2623 pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
2625 #ifdef C2_SELF_REFRESH_DISABLE
2627 if (integrated_graphics) {
2628 printk(BIOS_DEBUG, "C2 self-refresh with IGD\n");
2629 MCHBAR16(MIPMC4) = 0x0468;
2630 MCHBAR16(MIPMC5) = 0x046c;
2631 MCHBAR16(MIPMC6) = 0x046c;
2633 MCHBAR16(MIPMC4) = 0x6468;
2634 MCHBAR16(MIPMC5) = 0x646c;
2635 MCHBAR16(MIPMC6) = 0x646c;
2638 if (integrated_graphics) {
2639 MCHBAR16(MIPMC4) = 0x04f8;
2640 MCHBAR16(MIPMC5) = 0x04fc;
2641 MCHBAR16(MIPMC6) = 0x04fc;
2643 MCHBAR16(MIPMC4) = 0x64f8;
2644 MCHBAR16(MIPMC5) = 0x64fc;
2645 MCHBAR16(MIPMC6) = 0x64fc;
2650 reg32 = MCHBAR32(PMCFG);
2651 reg32 &= ~(3 << 17);
2653 MCHBAR32(PMCFG) = reg32;
2655 MCHBAR32(PMCFG) |= (1 << 4);
2657 reg32 = MCHBAR32(0xc30);
2658 reg32 &= 0xffffff00;
2660 MCHBAR32(0xc30) = reg32;
2662 MCHBAR32(0xb18) &= ~(1 << 21);
2665 static void sdram_thermal_management(void)
2668 MCHBAR8(TCO1) = 0x00;
2669 MCHBAR8(TCO0) = 0x00;
2671 /* The Thermal Sensors for DIMMs at 0x50, 0x52 are at I2C addr
2675 /* TODO This is not implemented yet. Volunteers? */
2678 static void sdram_save_receive_enable(void)
2684 /* The following values are stored to an unused CMOS
2685 * area and restored instead of recalculated in case
2688 * C0WL0REOST [7:0] -> 8 bit
2689 * C1WL0REOST [7:0] -> 8 bit
2690 * RCVENMT [11:8] [3:0] -> 8 bit
2691 * C0DRT1 [27:24] -> 4 bit
2692 * C1DRT1 [27:24] -> 4 bit
2695 values[0] = MCHBAR8(C0WL0REOST);
2696 values[1] = MCHBAR8(C1WL0REOST);
2698 reg32 = MCHBAR32(RCVENMT);
2699 values[2] = (u8)((reg32 >> (8 - 4)) & 0xf0) | (reg32 & 0x0f);
2701 reg32 = MCHBAR32(C0DRT1);
2702 values[3] = (reg32 >> 24) & 0x0f;
2703 reg32 = MCHBAR32(C1DRT1);
2704 values[3] |= (reg32 >> (24 - 4)) & 0xf0;
2706 /* coreboot only uses bytes 0 - 127 for its CMOS values so far
2707 * so we grab bytes 128 - 131 to save the receive enable values
2711 cmos_write(values[i], 128 + i);
2714 static void sdram_recover_receive_enable(void)
2721 values[i] = cmos_read(128 + i);
2723 MCHBAR8(C0WL0REOST) = values[0];
2724 MCHBAR8(C1WL0REOST) = values[1];
2726 reg32 = MCHBAR32(RCVENMT);
2727 reg32 &= ~((0x0f << 8) | (0x0f << 0));
2728 reg32 |= ((u32)(values[2] & 0xf0) << (8 - 4)) | (values[2] & 0x0f);
2729 MCHBAR32(RCVENMT) = reg32;
2731 reg32 = MCHBAR32(C0DRT1) & ~(0x0f << 24);
2732 reg32 |= (u32)(values[3] & 0x0f) << 24;
2733 MCHBAR32(C0DRT1) = reg32;
2735 reg32 = MCHBAR32(C1DRT1) & ~(0x0f << 24);
2736 reg32 |= (u32)(values[3] & 0xf0) << (24 - 4);
2737 MCHBAR32(C1DRT1) = reg32;
2742 static void sdram_program_receive_enable(struct sys_info *sysinfo)
2744 MCHBAR32(REPC) |= (1 << 0);
2746 /* enable upper CMOS */
2747 RCBA32(0x3400) = (1 << 2);
2749 /* Program Receive Enable Timings */
2750 if (sysinfo->boot_path == BOOT_PATH_RESUME) {
2751 sdram_recover_receive_enable();
2753 receive_enable_adjust(sysinfo);
2754 sdram_save_receive_enable();
2757 MCHBAR32(C0DRC1) |= (1 << 6);
2758 MCHBAR32(C1DRC1) |= (1 << 6);
2759 MCHBAR32(C0DRC1) &= ~(1 << 6);
2760 MCHBAR32(C1DRC1) &= ~(1 << 6);
2762 MCHBAR32(MIPMC3) |= (0x0f << 0);
2766 * @brief Enable On-Die Termination for DDR2.
2770 static void sdram_on_die_termination(struct sys_info *sysinfo)
2772 static const u32 odt[] = {
2773 0x00024911, 0xe0010000,
2774 0x00049211, 0xe0020000,
2775 0x0006db11, 0xe0030000,
2781 reg32 = MCHBAR32(ODTC);
2782 reg32 &= ~(3 << 16);
2783 reg32 |= (1 << 14) | (1 << 6) | (2 << 16);
2784 MCHBAR32(ODTC) = reg32;
2786 if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
2787 sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {
2788 printk(BIOS_DEBUG, "one dimm per channel config.. \n");
2790 reg32 = MCHBAR32(C0ODT);
2791 reg32 &= ~(7 << 28);
2792 MCHBAR32(C0ODT) = reg32;
2793 reg32 = MCHBAR32(C1ODT);
2794 reg32 &= ~(7 << 28);
2795 MCHBAR32(C1ODT) = reg32;
2800 reg32 = MCHBAR32(C0ODT) & 0xfff00000;
2801 reg32 |= odt[(cas-3) * 2];
2802 MCHBAR32(C0ODT) = reg32;
2804 reg32 = MCHBAR32(C1ODT) & 0xfff00000;
2805 reg32 |= odt[(cas-3) * 2];
2806 MCHBAR32(C1ODT) = reg32;
2808 reg32 = MCHBAR32(C0ODT + 4) & 0x1fc8ffff;
2809 reg32 |= odt[((cas-3) * 2) + 1];
2810 MCHBAR32(C0ODT + 4) = reg32;
2812 reg32 = MCHBAR32(C1ODT + 4) & 0x1fc8ffff;
2813 reg32 |= odt[((cas-3) * 2) + 1];
2814 MCHBAR32(C1ODT + 4) = reg32;
2818 * @brief Enable clocks to populated sockets
2821 static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
2823 u8 clocks[2] = { 0, 0 };
2825 #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
2826 #define CLOCKS_WIDTH 2
2827 #elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
2828 #define CLOCKS_WIDTH 3
2830 if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
2831 clocks[0] |= (1 << CLOCKS_WIDTH)-1;
2833 if (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
2834 clocks[0] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
2836 if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED)
2837 clocks[1] |= (1 << CLOCKS_WIDTH)-1;
2839 if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
2840 clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
2842 #if CONFIG_OVERRIDE_CLOCK_DISABLE
2843 /* Usually system firmware turns off system memory clock signals
2844 * to unused SO-DIMM slots to reduce EMI and power consumption.
2845 * However, the Kontron 986LCD-M does not like unused clock
2846 * signals to be disabled.
2849 clocks[0] = 0xf; /* force all clock gate pairs to enable */
2850 clocks[1] = 0xf; /* force all clock gate pairs to enable */
2853 MCHBAR8(C0DCLKDIS) = clocks[0];
2854 MCHBAR8(C1DCLKDIS) = clocks[1];
2857 #define RTT_ODT_NONE 0
2858 #define RTT_ODT_50_OHM ( (1 << 9) | (1 << 5) )
2859 #define RTT_ODT_75_OHM (1 << 5)
2860 #define RTT_ODT_150_OHM (1 << 9)
2862 #define EMRS_OCD_DEFAULT ( (1 << 12) | (1 << 11) | (1 << 10) )
2864 #define MRS_CAS_3 (3 << 7)
2865 #define MRS_CAS_4 (4 << 7)
2866 #define MRS_CAS_5 (5 << 7)
2868 #define MRS_TWR_3 (2 << 12)
2869 #define MRS_TWR_4 (3 << 12)
2870 #define MRS_TWR_5 (4 << 12)
2872 #define MRS_BT (1 << 6)
2874 #define MRS_BL4 (2 << 3)
2875 #define MRS_BL8 (3 << 3)
2877 static void sdram_jedec_enable(struct sys_info *sysinfo)
2880 u32 bankaddr = 0, tmpaddr, mrsaddr = 0;
2882 for (i = 0, nonzero = -1; i < 8; i++) {
2883 if (sysinfo->banksize[i] == 0) {
2887 printk(BIOS_DEBUG, "jedec enable sequence: bank %d\n", i);
2890 /* Start at address 0 */
2894 if (sysinfo->interleaved) {
2899 if (nonzero != -1) {
2900 printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", nonzero);
2901 bankaddr += sysinfo->banksize[nonzero] <<
2902 (sysinfo->interleaved ? 26 : 25);
2905 /* No populated bank hit before. Start at address 0 */
2909 /* We have a bank with a non-zero size.. Remember it
2910 * for the next offset we have to calculate
2914 /* Get CAS latency set up */
2915 switch (sysinfo->cas) {
2916 case 5: mrsaddr = MRS_CAS_5; break;
2917 case 4: mrsaddr = MRS_CAS_4; break;
2918 case 3: mrsaddr = MRS_CAS_3; break;
2919 default: die("Jedec Error (CAS).\n");
2923 switch (sysinfo->twr) {
2924 case 5: mrsaddr |= MRS_TWR_5; break;
2925 case 4: mrsaddr |= MRS_TWR_4; break;
2926 case 3: mrsaddr |= MRS_TWR_3; break;
2927 default: die("Jedec Error (tWR).\n");
2930 /* Set "Burst Type" */
2934 if (sysinfo->interleaved) {
2935 mrsaddr = mrsaddr << 1;
2938 /* Only burst length 8 supported */
2942 PRINTK_DEBUG("Apply NOP\n");
2943 do_ram_command(RAM_COMMAND_NOP);
2944 ram_read32(bankaddr);
2946 /* Precharge all banks */
2947 PRINTK_DEBUG("All Banks Precharge\n");
2948 do_ram_command(RAM_COMMAND_PRECHARGE);
2949 ram_read32(bankaddr);
2951 /* Extended Mode Register Set (2) */
2952 PRINTK_DEBUG("Extended Mode Register Set(2)\n");
2953 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_2);
2954 ram_read32(bankaddr);
2956 /* Extended Mode Register Set (3) */
2957 PRINTK_DEBUG("Extended Mode Register Set(3)\n");
2958 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_3);
2959 ram_read32(bankaddr);
2961 /* Extended Mode Register Set */
2962 PRINTK_DEBUG("Extended Mode Register Set\n");
2963 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2965 if (!sdram_capabilities_dual_channel()) {
2966 tmpaddr |= RTT_ODT_75_OHM;
2967 } else if (sysinfo->interleaved) {
2968 tmpaddr |= (RTT_ODT_150_OHM << 1);
2970 tmpaddr |= RTT_ODT_150_OHM;
2972 ram_read32(tmpaddr);
2974 /* Mode Register Set: Reset DLLs */
2975 PRINTK_DEBUG("MRS: Reset DLLs\n");
2976 do_ram_command(RAM_COMMAND_MRS);
2979 /* Set DLL reset bit */
2980 if (sysinfo->interleaved)
2981 tmpaddr |= (1 << 12);
2983 tmpaddr |= (1 << 11);
2984 ram_read32(tmpaddr);
2986 /* Precharge all banks */
2987 PRINTK_DEBUG("All Banks Precharge\n");
2988 do_ram_command(RAM_COMMAND_PRECHARGE);
2989 ram_read32(bankaddr);
2991 /* CAS before RAS Refresh */
2992 PRINTK_DEBUG("CAS before RAS\n");
2993 do_ram_command(RAM_COMMAND_CBR);
2995 /* CBR wants two READs */
2996 ram_read32(bankaddr);
2997 ram_read32(bankaddr);
2999 /* Mode Register Set: Enable DLLs */
3000 PRINTK_DEBUG("MRS: Enable DLLs\n");
3001 do_ram_command(RAM_COMMAND_MRS);
3005 ram_read32(tmpaddr);
3007 /* Extended Mode Register Set */
3008 PRINTK_DEBUG("Extended Mode Register Set: ODT/OCD\n");
3009 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
3012 if (!sdram_capabilities_dual_channel()) {
3014 tmpaddr |= RTT_ODT_75_OHM | EMRS_OCD_DEFAULT;
3015 } else if (sysinfo->interleaved) {
3016 tmpaddr |= ((RTT_ODT_150_OHM | EMRS_OCD_DEFAULT) << 1);
3018 tmpaddr |= RTT_ODT_150_OHM | EMRS_OCD_DEFAULT;
3020 ram_read32(tmpaddr);
3022 /* Extended Mode Register Set */
3023 PRINTK_DEBUG("Extended Mode Register Set: OCD Exit\n");
3024 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
3027 if (!sdram_capabilities_dual_channel()) {
3028 tmpaddr |= RTT_ODT_75_OHM;
3029 } else if (sysinfo->interleaved) {
3030 tmpaddr |= (RTT_ODT_150_OHM << 1);
3032 tmpaddr |= RTT_ODT_150_OHM;
3034 ram_read32(tmpaddr);
3038 static void sdram_init_complete(void)
3040 PRINTK_DEBUG("Normal Operation\n");
3041 do_ram_command(RAM_COMMAND_NORMAL);
3044 static void sdram_setup_processor_side(void)
3046 if (i945_silicon_revision() == 0)
3047 MCHBAR32(FSBPMC3) |= (1 << 2);
3049 MCHBAR8(0xb00) |= 1;
3051 if (i945_silicon_revision() == 0)
3052 MCHBAR32(SLPCTL) |= (1 << 8);
3056 * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3
3058 void sdram_initialize(int boot_path, const u8 *spd_addresses)
3060 struct sys_info sysinfo;
3063 printk(BIOS_DEBUG, "Setting up RAM controller.\n");
3065 memset(&sysinfo, 0, sizeof(sysinfo));
3067 sysinfo.boot_path = boot_path;
3068 sysinfo.spd_addresses = spd_addresses;
3070 /* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */
3071 sdram_get_dram_configuration(&sysinfo);
3073 /* If error, do cold boot */
3074 sdram_detect_errors(&sysinfo);
3076 /* Check whether we have stacked DIMMs */
3077 sdram_verify_package_type(&sysinfo);
3079 /* Determine common CAS */
3080 cas_mask = sdram_possible_cas_latencies(&sysinfo);
3082 /* Choose Common Frequency */
3083 sdram_detect_cas_latency_and_ram_speed(&sysinfo, cas_mask);
3085 /* Determine smallest common tRAS */
3086 sdram_detect_smallest_tRAS(&sysinfo);
3089 sdram_detect_smallest_tRP(&sysinfo);
3091 /* Determine tRCD */
3092 sdram_detect_smallest_tRCD(&sysinfo);
3094 /* Determine smallest refresh period */
3095 sdram_detect_smallest_refresh(&sysinfo);
3097 /* Verify all DIMMs support burst length 8 */
3098 sdram_verify_burst_length(&sysinfo);
3101 sdram_detect_smallest_tWR(&sysinfo);
3103 /* Determine DIMM size parameters (rows, columns banks) */
3104 sdram_detect_dimm_size(&sysinfo);
3106 /* determine tRFC */
3107 sdram_detect_smallest_tRFC(&sysinfo);
3109 /* Program PLL settings */
3110 sdram_program_pll_settings(&sysinfo);
3112 /* Program Graphics Frequency */
3113 sdram_program_graphics_frequency(&sysinfo);
3115 /* Program System Memory Frequency */
3116 sdram_program_memory_frequency(&sysinfo);
3118 /* Determine Mode of Operation (Interleaved etc) */
3119 sdram_set_channel_mode(&sysinfo);
3121 /* Program Clock Crossing values */
3122 sdram_program_clock_crossing();
3124 /* Disable fast dispatch */
3125 sdram_disable_fast_dispatch();
3127 /* Enable WIODLL Power Down in ACPI states */
3128 MCHBAR32(C0DMC) |= (1 << 24);
3129 MCHBAR32(C1DMC) |= (1 << 24);
3131 /* Program DRAM Row Boundary/Attribute Registers */
3133 /* program row size DRB and set TOLUD */
3134 sdram_program_row_boundaries(&sysinfo);
3136 /* program page size DRA */
3137 sdram_set_row_attributes(&sysinfo);
3139 /* Program CxBNKARC */
3140 sdram_set_bank_architecture(&sysinfo);
3142 /* Program DRAM Timing and Control registers based on SPD */
3143 sdram_set_timing_and_control(&sysinfo);
3145 /* On-Die Termination Adjustment */
3146 sdram_on_die_termination(&sysinfo);
3148 /* Pre Jedec Initialization */
3149 sdram_pre_jedec_initialization();
3151 /* Perform System Memory IO Initialization */
3152 sdram_initialize_system_memory_io(&sysinfo);
3154 /* Perform System Memory IO Buffer Enable */
3155 sdram_enable_system_memory_io(&sysinfo);
3157 /* Enable System Memory Clocks */
3158 sdram_enable_memory_clocks(&sysinfo);
3160 if (boot_path == BOOT_PATH_NORMAL) {
3161 /* Jedec Initialization sequence */
3162 sdram_jedec_enable(&sysinfo);
3165 /* Program Power Management Registers */
3166 sdram_power_management(&sysinfo);
3168 /* Post Jedec Init */
3169 sdram_post_jedec_initialization(&sysinfo);
3171 /* Program DRAM Throttling */
3172 sdram_thermal_management();
3174 /* Normal Operations */
3175 sdram_init_complete();
3177 /* Program Receive Enable Timings */
3178 sdram_program_receive_enable(&sysinfo);
3180 /* Enable Periodic RCOMP */
3181 sdram_enable_rcomp();
3183 /* Tell ICH7 that we're done */
3184 reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
3186 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
3188 printk(BIOS_DEBUG, "RAM initialization finished.\n");
3190 sdram_setup_processor_side();
3193 unsigned long get_top_of_ram(void)
3197 if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & ((1 << 4) | (1 << 3))) {
3198 /* IGD enabled, get top of Memory from BSM register */
3199 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
3201 tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24;
3204 /* if TSEG enabled subtract size */
3205 switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM)) {
3219 /* TSEG either disabled or invalid */
3222 return (unsigned long) tom;