src/northbridge/intel/i945/raminit.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <cpu/x86/mtrr.h>
  21 #include <cpu/x86/cache.h>
  22 #include <pc80/mc146818rtc.h>
  23 #include <spd.h>
  24 #include "raminit.h"
  25 #include "i945.h"
  26
  27 /* Debugging macros. */
  28 #if CONFIG_DEBUG_RAM_SETUP
  29 #define PRINTK_DEBUG(x...)      printk(BIOS_DEBUG, x)
  30 #else
  31 #define PRINTK_DEBUG(x...)
  32 #endif
  33
  34 #define RAM_INITIALIZATION_COMPLETE     (1 << 19)
  35
  36 #define RAM_COMMAND_SELF_REFRESH        (0x0 << 16)
  37 #define RAM_COMMAND_NOP                 (0x1 << 16)
  38 #define RAM_COMMAND_PRECHARGE           (0x2 << 16)
  39 #define RAM_COMMAND_MRS                 (0x3 << 16)
  40 #define RAM_COMMAND_EMRS                (0x4 << 16)
  41 #define RAM_COMMAND_CBR                 (0x6 << 16)
  42 #define RAM_COMMAND_NORMAL              (0x7 << 16)
  43
  44 #define RAM_EMRS_1                      (0x0 << 21)
  45 #define RAM_EMRS_2                      (0x1 << 21)
  46 #define RAM_EMRS_3                      (0x2 << 21)
  47
  48 static __attribute__((noinline)) void do_ram_command(u32 command)
  49 {
  50         u32 reg32;
  51
  52         reg32 = MCHBAR32(DCC);
  53         reg32 &= ~( (3<<21) | (1<<20) | (1<<19) | (7 << 16) );
  54         reg32 |= command;
  55
  56         /* Also set Init Complete */
  57         if (command == RAM_COMMAND_NORMAL)
  58                 reg32 |= RAM_INITIALIZATION_COMPLETE;
  59
  60         PRINTK_DEBUG("   Sending RAM command 0x%08x", reg32);
  61
  62         MCHBAR32(DCC) = reg32;  /* This is the actual magic */
  63
  64         PRINTK_DEBUG("...done\n");
  65 }
  66
  67 static void ram_read32(u32 offset)
  68 {
  69         PRINTK_DEBUG("   ram read: %08x\n", offset);
  70
  71         read32(offset);
  72 }
  73
  74 #if CONFIG_DEBUG_RAM_SETUP
  75 static void sdram_dump_mchbar_registers(void)
  76 {
  77         int i;
  78         printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n");
  79
  80         for (i=0; i<0xfff; i+=4) {
  81                 if (MCHBAR32(i) == 0)
  82                         continue;
  83                 printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i));
  84         }
  85 }
  86 #endif
  87
  88 static int memclk(void)
  89 {
  90         int offset = 0;
  91 #ifdef CHIPSET_I945GM
  92         offset++;
  93 #endif
  94         switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
  95         case 1: return 400;
  96         case 2: return 533;
  97         case 3: return 667;
  98         default: printk(BIOS_DEBUG, "memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
  99         }
 100         return -1;
 101 }
 102
 103 #ifdef CHIPSET_I945GM
 104 static int fsbclk(void)
 105 {
 106         switch (MCHBAR32(CLKCFG) & 7) {
 107         case 0: return 400;
 108         case 1: return 533;
 109         case 3: return 667;
 110         default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 111         }
 112         return -1;
 113 }
 114 #endif
 115 #ifdef CHIPSET_I945GC
 116 static int fsbclk(void)
 117 {
 118         switch (MCHBAR32(CLKCFG) & 7) {
 119         case 0: return 1066;
 120         case 1: return 533;
 121         case 2: return 800;
 122         default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 123         }
 124         return -1;
 125 }
 126 #endif
 127
 128 static int sdram_capabilities_max_supported_memory_frequency(void)
 129 {
 130         u32 reg32;
 131
 132 #ifdef MAXIMUM_SUPPORTED_FREQUENCY
 133         return MAXIMUM_SUPPORTED_FREQUENCY;
 134 #endif
 135
 136         reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4); /* CAPID0 + 4 */
 137         reg32 &= (7 << 0);
 138
 139         switch (reg32) {
 140         case 4: return 400;
 141         case 3: return 533;
 142         case 2: return 667;
 143         }
 144         /* Newer revisions of this chipset rather support faster memory clocks,
 145          * so if it's a reserved value, return the fastest memory clock that we
 146          * know of and can handle
 147          */
 148         return 667;
 149 }
 150
 151 /**
 152  * @brief determine whether chipset is capable of dual channel interleaved mode
 153  *
 154  * @return 1 if interleaving is supported, 0 otherwise
 155  */
 156 static int sdram_capabilities_interleave(void)
 157 {
 158         u32 reg32;
 159
 160         reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
 161         reg32 >>= 25;
 162         reg32 &= 1;
 163
 164         return (!reg32);
 165 }
 166
 167 /**
 168  * @brief determine whether chipset is capable of two memory channels
 169  *
 170  * @return 1 if dual channel operation is supported, 0 otherwise
 171  */
 172 static int sdram_capabilities_dual_channel(void)
 173 {
 174         u32 reg32;
 175
 176         reg32 = pci_read_config32(PCI_DEV(0, 0x00,0), 0xe4); /* CAPID0 + 4 */
 177         reg32 >>= 24;
 178         reg32 &= 1;
 179
 180         return (!reg32);
 181 }
 182
 183 static int sdram_capabilities_enhanced_addressing_xor(void)
 184 {
 185         u8 reg8;
 186
 187         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 188         reg8 &= (1 << 7);
 189
 190         return (!reg8);
 191 }
 192
 193 static int sdram_capabilities_two_dimms_per_channel(void)
 194 {
 195         u8 reg8;
 196
 197         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe8); /* CAPID0 + 8 */
 198         reg8 &= (1 << 0);
 199
 200         return (reg8 != 0);
 201 }
 202
 203 // TODO check if we ever need this function
 204 #if 0
 205 static int sdram_capabilities_MEM4G_disable(void)
 206 {
 207         u8 reg8;
 208
 209         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 210         reg8 &= (1 << 0);
 211
 212         return (reg8 != 0);
 213 }
 214 #endif
 215
 216 #define GFX_FREQUENCY_CAP_166MHZ        0x04
 217 #define GFX_FREQUENCY_CAP_200MHZ        0x03
 218 #define GFX_FREQUENCY_CAP_250MHZ        0x02
 219 #define GFX_FREQUENCY_CAP_ALL           0x00
 220
 221 static int sdram_capabilities_core_frequencies(void)
 222 {
 223         u8 reg8;
 224
 225         reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
 226         reg8 &= (1 << 3) | (1 << 2) | (1 << 1);
 227         reg8 >>= 1;
 228
 229         return (reg8);
 230 }
 231
 232 static void sdram_detect_errors(struct sys_info *sysinfo)
 233 {
 234         u8 reg8;
 235         u8 do_reset = 0;
 236
 237         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 238
 239         if (reg8 & ((1<<7)|(1<<2))) {
 240                 if (reg8 & (1<<2)) {
 241                         printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n");
 242                         /* Write back clears bit 2 */
 243                         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 244                         do_reset = 1;
 245
 246                 }
 247
 248                 if (reg8 & (1<<7)) {
 249                         printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n");
 250                         reg8 &= ~(1<<7);
 251                         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 252                         do_reset = 1;
 253                 }
 254
 255                 /* Set SLP_S3# Assertion Stretch Enable */
 256                 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */
 257                 reg8 |= (1 << 3);
 258                 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 259
 260                 if (do_reset) {
 261                         printk(BIOS_DEBUG, "Reset required.\n");
 262                         outb(0x00, 0xcf9);
 263                         outb(0x0e, 0xcf9);
 264                         for (;;) asm("hlt"); /* Wait for reset! */
 265                 }
 266         }
 267
 268         /* Set DRAM initialization bit in ICH7 */
 269         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 270         reg8 |= (1<<7);
 271         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 272
 273         /* clear self refresh if not wake-up from suspend */
 274         if (sysinfo->boot_path != 2) {
 275                 MCHBAR8(0xf14) |= 3;
 276         } else {
 277                 /* Validate self refresh config */
 278                 if (((sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) ||
 279                      (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) &&
 280                     !(MCHBAR8(0xf14) & (1<<0))) {
 281                         do_reset = 1;
 282                 }
 283                 if (((sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) ||
 284                      (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) &&
 285                     !(MCHBAR8(0xf14) & (1<<1))) {
 286                         do_reset = 1;
 287                 }
 288         }
 289
 290         if (do_reset) {
 291                 printk(BIOS_DEBUG, "Reset required.\n");
 292                 outb(0x00, 0xcf9);
 293                 outb(0x0e, 0xcf9);
 294                 for (;;) asm("hlt"); /* Wait for reset! */
 295         }
 296 }
 297
 298 /**
 299  * @brief Get generic DIMM parameters.
 300  * @param sysinfo Central memory controller information structure
 301  *
 302  * This function gathers several pieces of information for each system DIMM:
 303  *  o DIMM width (x8 / x16)
 304  *  o DIMM sides (single sided / dual sided)
 305  *
 306  *  Also, some non-supported scenarios are detected.
 307  */
 308
 309 static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 310 {
 311         u32 dimm_mask = 0;
 312         int i;
 313
 314         /**
 315          * i945 supports two DIMMs, in two configurations:
 316          *
 317          * - single channel with two dimms
 318          * - dual channel with one dimm per channel
 319          *
 320          * In practice dual channel mainboards have their spd at 0x50, 0x52
 321          * whereas single channel configurations have their spd at 0x50/x51
 322          *
 323          * The capability register knows a lot about the channel configuration
 324          * but for now we stick with the information we gather from the SPD
 325          * ROMs
 326          */
 327
 328         if (sdram_capabilities_dual_channel()) {
 329                 sysinfo->dual_channel = 1;
 330                 printk(BIOS_DEBUG, "This mainboard supports Dual Channel Operation.\n");
 331         } else {
 332                 sysinfo->dual_channel = 0;
 333                 printk(BIOS_DEBUG, "This mainboard supports only Single Channel Operation.\n");
 334         }
 335
 336         /**
 337          * Since we only support two DIMMs in total, there is a limited number
 338          * of combinations. This function returns the type of DIMMs.
 339          * return value:
 340          *   [0:7]  lower DIMM population
 341          *   [8-15] higher DIMM population
 342          *   [16]   dual channel?
 343          *
 344          * There are 5 different possible populations for a DIMM socket:
 345          * 1. x16 double sided (X16DS)
 346          * 2. x8 double sided  (X8DS)
 347          * 3. x16 single sided (X16SS)
 348          * 4. x8 double stacked (X8DDS)
 349          * 5. not populated (NC)
 350          *
 351          * For the return value we start counting at zero.
 352          *
 353          */
 354
 355         for (i=0; i<(2 * DIMM_SOCKETS); i++) {
 356                 u8 reg8, device = DIMM_SPD_BASE + i;
 357
 358                 /* Initialize the socket information with a sane value */
 359                 sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
 360
 361                 /* Dual Channel not supported, but Channel 1? Bail out */
 362                 if (!sdram_capabilities_dual_channel() && (i >> 1))
 363                         continue;
 364
 365                 /* Two DIMMs per channel not supported, but odd DIMM number? */
 366                 if (!sdram_capabilities_two_dimms_per_channel() && (i& 1))
 367                         continue;
 368
 369                 printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
 370
 371                 if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) {
 372                         printk(BIOS_DEBUG, "N/A\n");
 373                         continue;
 374                 }
 375
 376                 reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE);
 377                 if (reg8 == ERROR_SCHEME_ECC)
 378                         die("Error: ECC memory not supported by this chipset\n");
 379
 380                 reg8 = spd_read_byte(device, SPD_MODULE_ATTRIBUTES);
 381                 if (reg8 & MODULE_BUFFERED)
 382                         die("Error: Buffered memory not supported by this chipset\n");
 383                 if (reg8 & MODULE_REGISTERED)
 384                         die("Error: Registered memory not supported by this chipset\n");
 385
 386                 switch (spd_read_byte(device, SPD_PRIMARY_SDRAM_WIDTH)) {
 387                 case 0x08:
 388                         switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 389                         case 1:
 390                                 printk(BIOS_DEBUG, "x8DDS\n");
 391                                 sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS;
 392                                 break;
 393                         case 0:
 394                                 printk(BIOS_DEBUG, "x8DS\n");
 395                                 sysinfo->dimm[i] = SYSINFO_DIMM_X8DS;
 396                                 break;
 397                         default:
 398                                 printk(BIOS_DEBUG, "Unsupported.\n");
 399                         }
 400                         break;
 401                 case 0x10:
 402                         switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 403                         case 1:
 404                                 printk(BIOS_DEBUG, "x16DS\n");
 405                                 sysinfo->dimm[i] = SYSINFO_DIMM_X16DS;
 406                                 break;
 407                         case 0:
 408                                 printk(BIOS_DEBUG, "x16SS\n");
 409                                 sysinfo->dimm[i] = SYSINFO_DIMM_X16SS;
 410                                 break;
 411                         default:
 412                                 printk(BIOS_DEBUG, "Unsupported.\n");
 413                         }
 414                         break;
 415                 default:
 416                         die("Unsupported DDR-II memory width.\n");
 417                 }
 418
 419                 dimm_mask |= (1 << i);
 420         }
 421
 422         if (!dimm_mask) {
 423                 die("No memory installed.\n");
 424         }
 425
 426         if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
 427                 printk(BIOS_INFO, "Channel 0 has no memory populated.\n");
 428         }
 429 }
 430
 431 /**
 432  * @brief determine if any DIMMs are stacked
 433  *
 434  * @param sysinfo central sysinfo data structure.
 435  */
 436 static void sdram_verify_package_type(struct sys_info * sysinfo)
 437 {
 438         int i;
 439
 440         /* Assume no stacked DIMMs are available until we find one */
 441         sysinfo->package = 0;
 442         for (i=0; i<2*DIMM_SOCKETS; i++) {
 443                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 444                         continue;
 445
 446                 /* Is the current DIMM a stacked DIMM? */
 447                 if (spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & (1 << 4))
 448                         sysinfo->package = 1;
 449         }
 450 }
 451
 452 static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo)
 453 {
 454         int i;
 455         u8 cas_mask;
 456
 457         /* Setup CAS mask with all supported CAS Latencies */
 458         cas_mask = SPD_CAS_LATENCY_DDR2_3 |
 459                    SPD_CAS_LATENCY_DDR2_4 |
 460                    SPD_CAS_LATENCY_DDR2_5;
 461
 462         for (i=0; i<2*DIMM_SOCKETS; i++) {
 463                 if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED)
 464                         cas_mask &= spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 465         }
 466
 467         if(!cas_mask) {
 468                 die("No DDR-II modules with accepted CAS latencies found.\n");
 469         }
 470
 471         return cas_mask;
 472 }
 473
 474 static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 cas_mask)
 475 {
 476         int i, j, idx;
 477         int lowest_common_cas = 0;
 478         int max_ram_speed = 0;
 479
 480         const u8 ddr2_speeds_table[] = {
 481                 0x50, 0x60,     /* DDR2 400: tCLK = 5.0ns  tAC = 0.6ns  */
 482                 0x3d, 0x50,     /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns  */
 483                 0x30, 0x45,     /* DDR2 667: tCLK = 3.0ns  tAC = 0.45ns */
 484         };
 485
 486         const u8 spd_lookup_table[] = {
 487                 SPD_MIN_CYCLE_TIME_AT_CAS_MAX,  SPD_ACCESS_TIME_FROM_CLOCK,
 488                 SPD_SDRAM_CYCLE_TIME_2ND,       SPD_ACCESS_TIME_FROM_CLOCK_2ND,
 489                 SPD_SDRAM_CYCLE_TIME_3RD,       SPD_ACCESS_TIME_FROM_CLOCK_3RD
 490         };
 491
 492         switch (sdram_capabilities_max_supported_memory_frequency()) {
 493         case 400: max_ram_speed = 0; break;
 494         case 533: max_ram_speed = 1; break;
 495         case 667: max_ram_speed = 2; break;
 496         }
 497
 498         if (fsbclk() == 533)
 499                 max_ram_speed = 1;
 500
 501         sysinfo->memory_frequency = 0;
 502         sysinfo->cas = 0;
 503
 504         if (cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 505                 lowest_common_cas = 3;
 506         } else if (cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 507                 lowest_common_cas = 4;
 508         } else if (cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 509                 lowest_common_cas = 5;
 510         }
 511         PRINTK_DEBUG("lowest common cas = %d\n", lowest_common_cas);
 512
 513         for (j = max_ram_speed; j>=0; j--) {
 514                 int freq_cas_mask = cas_mask;
 515
 516                 PRINTK_DEBUG("Probing Speed %d\n", j);
 517                 for (i=0; i<2*DIMM_SOCKETS; i++) {
 518                         int current_cas_mask;
 519
 520                         PRINTK_DEBUG("  DIMM: %d\n", i);
 521                         if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
 522                                 continue;
 523                         }
 524
 525                         current_cas_mask = spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES);
 526
 527                         while (current_cas_mask) {
 528                                 int highest_supported_cas = 0, current_cas = 0;
 529                                 PRINTK_DEBUG("    Current CAS mask: %04x; ", current_cas_mask);
 530                                 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 531                                         highest_supported_cas = 5;
 532                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 533                                         highest_supported_cas = 4;
 534                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 535                                         highest_supported_cas = 3;
 536                                 }
 537                                 if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 538                                         current_cas = 3;
 539                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 540                                         current_cas = 4;
 541                                 } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 542                                         current_cas = 5;
 543                                 }
 544
 545                                 idx = highest_supported_cas - current_cas;
 546                                 PRINTK_DEBUG("idx=%d, ", idx);
 547                                 PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]));
 548                                 PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]));
 549
 550                                 if (spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] &&
 551                                                 spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) {
 552                                         PRINTK_DEBUG(":    OK\n");
 553                                         break;
 554                                 }
 555
 556                                 PRINTK_DEBUG(":    Not fast enough!\n");
 557
 558                                 current_cas_mask &= ~(1 << (current_cas));
 559                         }
 560
 561                         freq_cas_mask &= current_cas_mask;
 562                         if (!current_cas_mask) {
 563                                 PRINTK_DEBUG("    No valid CAS for this speed on DIMM %d\n", i);
 564                                 break;
 565                         }
 566                 }
 567                 PRINTK_DEBUG("  freq_cas_mask for speed %d: %04x\n", j, freq_cas_mask);
 568                 if (freq_cas_mask) {
 569                         switch (j) {
 570                         case 0: sysinfo->memory_frequency = 400; break;
 571                         case 1: sysinfo->memory_frequency = 533; break;
 572                         case 2: sysinfo->memory_frequency = 667; break;
 573                         }
 574                         if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_3) {
 575                                 sysinfo->cas = 3;
 576                         } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_4) {
 577                                 sysinfo->cas = 4;
 578                         } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_5) {
 579                                 sysinfo->cas = 5;
 580                         }
 581                         break;
 582                 }
 583         }
 584
 585         if (sysinfo->memory_frequency && sysinfo->cas) {
 586                 printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n",
 587                                 sysinfo->memory_frequency, sysinfo->cas);
 588         } else {
 589                 die("Could not find common memory frequency and CAS\n");
 590         }
 591 }
 592
 593 static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo)
 594 {
 595         int i;
 596         int tRAS_time;
 597         int tRAS_cycles;
 598         int freq_multiplier = 0;
 599
 600         switch (sysinfo->memory_frequency) {
 601         case 400: freq_multiplier = 0x14; break; /* 5ns */
 602         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 603         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 604         }
 605
 606         tRAS_cycles = 4; /* 4 clocks minimum */
 607         tRAS_time = tRAS_cycles * freq_multiplier;
 608
 609         for (i=0; i<2*DIMM_SOCKETS; i++) {
 610                 u8 reg8;
 611
 612                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 613                         continue;
 614
 615                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
 616                 if (!reg8) {
 617                         die("Invalid tRAS value.\n");
 618                 }
 619
 620                 while ((tRAS_time >> 2) < reg8) {
 621                         tRAS_time += freq_multiplier;
 622                         tRAS_cycles++;
 623                 }
 624         }
 625         if(tRAS_cycles > 0x18) {
 626                 die("DDR-II Module does not support this frequency (tRAS error)\n");
 627         }
 628
 629         printk(BIOS_DEBUG, "tRAS = %d cycles\n", tRAS_cycles);
 630         sysinfo->tras = tRAS_cycles;
 631 }
 632
 633 static void sdram_detect_smallest_tRP(struct sys_info * sysinfo)
 634 {
 635         int i;
 636         int tRP_time;
 637         int tRP_cycles;
 638         int freq_multiplier = 0;
 639
 640         switch (sysinfo->memory_frequency) {
 641         case 400: freq_multiplier = 0x14; break; /* 5ns */
 642         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 643         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 644         }
 645
 646         tRP_cycles = 2; /* 2 clocks minimum */
 647         tRP_time = tRP_cycles * freq_multiplier;
 648
 649         for (i=0; i<2*DIMM_SOCKETS; i++) {
 650                 u8 reg8;
 651
 652                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 653                         continue;
 654
 655                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ROW_PRECHARGE_TIME);
 656                 if (!reg8) {
 657                         die("Invalid tRP value.\n");
 658                 }
 659
 660                 while (tRP_time < reg8) {
 661                         tRP_time += freq_multiplier;
 662                         tRP_cycles++;
 663                 }
 664         }
 665
 666         if(tRP_cycles > 6) {
 667                 die("DDR-II Module does not support this frequency (tRP error)\n");
 668         }
 669
 670         printk(BIOS_DEBUG, "tRP = %d cycles\n", tRP_cycles);
 671         sysinfo->trp = tRP_cycles;
 672 }
 673
 674 static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
 675 {
 676         int i;
 677         int tRCD_time;
 678         int tRCD_cycles;
 679         int freq_multiplier = 0;
 680
 681         switch (sysinfo->memory_frequency) {
 682         case 400: freq_multiplier = 0x14; break; /* 5ns */
 683         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 684         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 685         }
 686
 687         tRCD_cycles = 2; /* 2 clocks minimum */
 688         tRCD_time = tRCD_cycles * freq_multiplier;
 689
 690         for (i=0; i<2*DIMM_SOCKETS; i++) {
 691                 u8 reg8;
 692
 693                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 694                         continue;
 695
 696                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_RAS_TO_CAS_DELAY);
 697                 if (!reg8) {
 698                         die("Invalid tRCD value.\n");
 699                 }
 700
 701                 while (tRCD_time < reg8) {
 702                         tRCD_time += freq_multiplier;
 703                         tRCD_cycles++;
 704                 }
 705         }
 706         if(tRCD_cycles > 6) {
 707                 die("DDR-II Module does not support this frequency (tRCD error)\n");
 708         }
 709
 710         printk(BIOS_DEBUG, "tRCD = %d cycles\n", tRCD_cycles);
 711         sysinfo->trcd = tRCD_cycles;
 712 }
 713
 714 static void sdram_detect_smallest_tWR(struct sys_info * sysinfo)
 715 {
 716         int i;
 717         int tWR_time;
 718         int tWR_cycles;
 719         int freq_multiplier = 0;
 720
 721         switch (sysinfo->memory_frequency) {
 722         case 400: freq_multiplier = 0x14; break; /* 5ns */
 723         case 533: freq_multiplier = 0x0f; break; /* 3.75ns */
 724         case 667: freq_multiplier = 0x0c; break; /* 3ns */
 725         }
 726
 727         tWR_cycles = 2; /* 2 clocks minimum */
 728         tWR_time = tWR_cycles * freq_multiplier;
 729
 730         for (i=0; i<2*DIMM_SOCKETS; i++) {
 731                 u8 reg8;
 732
 733                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 734                         continue;
 735
 736                 reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_WRITE_RECOVERY_TIME);
 737                 if (!reg8) {
 738                         die("Invalid tWR value.\n");
 739                 }
 740
 741                 while (tWR_time < reg8) {
 742                         tWR_time += freq_multiplier;
 743                         tWR_cycles++;
 744                 }
 745         }
 746         if(tWR_cycles > 5) {
 747                 die("DDR-II Module does not support this frequency (tWR error)\n");
 748         }
 749
 750         printk(BIOS_DEBUG, "tWR = %d cycles\n", tWR_cycles);
 751         sysinfo->twr = tWR_cycles;
 752 }
 753
 754 static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
 755 {
 756         int i, index = 0;
 757
 758         const u8 tRFC_cycles[] = {
 759              /* 75 105 127.5 */
 760                 15, 21, 26,     /* DDR2-400 */
 761                 20, 28, 34,     /* DDR2-533 */
 762                 25, 35, 43      /* DDR2-667 */
 763         };
 764
 765         for (i=0; i<2*DIMM_SOCKETS; i++) {
 766                 u8 reg8;
 767
 768                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 769                         continue;
 770
 771                 reg8 = sysinfo->banksize[i*2];
 772                 switch (reg8) {
 773                 case 0x04: reg8 = 0; break;
 774                 case 0x08: reg8 = 1; break;
 775                 case 0x10: reg8 = 2; break;
 776                 case 0x20: reg8 = 3; break;
 777                 }
 778
 779                 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS || sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
 780                         reg8++;
 781
 782                 if (reg8 > 3) {
 783                         /* Can this happen? Go back to 127.5ns just to be sure
 784                          * we don't run out of the array. This may be wrong
 785                          */
 786                         printk(BIOS_DEBUG, "DIMM %d is 1Gb x16.. Please report.\n", i);
 787                         reg8 = 3;
 788                 }
 789
 790                 if (reg8 > index)
 791                         index = reg8;
 792
 793         }
 794         index--;
 795         switch (sysinfo->memory_frequency) {
 796         case 667: index += 3; /* Fallthrough */
 797         case 533: index += 3; /* Fallthrough */
 798         case 400: break;
 799         }
 800
 801         sysinfo->trfc = tRFC_cycles[index];
 802         printk(BIOS_DEBUG, "tRFC = %d cycles\n", tRFC_cycles[index]);
 803 }
 804
 805 static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
 806 {
 807         int i;
 808
 809         sysinfo->refresh = 0;
 810
 811         for (i=0; i<2*DIMM_SOCKETS; i++) {
 812                 int refresh;
 813
 814                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 815                         continue;
 816
 817                 refresh = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH) & ~(1 << 7);
 818
 819                 /* 15.6us */
 820                 if (!refresh)
 821                         continue;
 822
 823                 /* Refresh is slower than 15.6us, use 15.6us */
 824                 if (refresh > 2)
 825                         continue;
 826
 827                 if (refresh == 2) {
 828                         sysinfo->refresh = 1;
 829                         break;
 830                 }
 831
 832                 die("DDR-II module has unsupported refresh value\n");
 833         }
 834         printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
 835 }
 836
 837 static void sdram_verify_burst_length(struct sys_info * sysinfo)
 838 {
 839         int i;
 840
 841         for (i=0; i<2*DIMM_SOCKETS; i++) {
 842                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
 843                         continue;
 844
 845                 if (!(spd_read_byte(DIMM_SPD_BASE + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8))
 846                         die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n");
 847         }
 848 }
 849
 850 static void sdram_program_dram_width(struct sys_info * sysinfo)
 851 {
 852         u16 c0dramw=0, c1dramw=0;
 853         int idx;
 854
 855         if (sysinfo->dual_channel)
 856                 idx = 2;
 857         else
 858                 idx = 1;
 859
 860         switch (sysinfo->dimm[0]) {
 861         case 0: c0dramw = 0x0000; break; /* x16DS */
 862         case 1: c0dramw = 0x0001; break; /* x8DS */
 863         case 2: c0dramw = 0x0000; break; /* x16SS */
 864         case 3: c0dramw = 0x0005; break; /* x8DDS */
 865         case 4: c0dramw = 0x0000; break; /* NC */
 866         }
 867
 868         switch (sysinfo->dimm[idx]) {
 869         case 0: c1dramw = 0x0000; break; /* x16DS */
 870         case 1: c1dramw = 0x0010; break; /* x8DS */
 871         case 2: c1dramw = 0x0000; break; /* x16SS */
 872         case 3: c1dramw = 0x0050; break; /* x8DDS */
 873         case 4: c1dramw = 0x0000; break; /* NC */
 874         }
 875
 876         if ( !sdram_capabilities_dual_channel() ) {
 877                 /* Single Channel */
 878                 c0dramw |= c1dramw;
 879                 c1dramw = 0;
 880         }
 881
 882         MCHBAR16(C0DRAMW) = c0dramw;
 883         MCHBAR16(C1DRAMW) = c1dramw;
 884 }
 885
 886 static void sdram_write_slew_rates(u32 offset, const u32 *slew_rate_table)
 887 {
 888         int i;
 889
 890         for (i=0; i<16; i++)
 891                 MCHBAR32(offset+(i*4)) = slew_rate_table[i];
 892 }
 893
 894 static const u32 dq2030[] = {
 895         0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
 896         0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
 897         0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
 898         0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
 899 };
 900
 901 static const u32 dq2330[] = {
 902         0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
 903         0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
 904         0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
 905         0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
 906 };
 907
 908 static const u32 cmd2710[] = {
 909         0x07060605, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
 910         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
 911         0x1110100f, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
 912         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
 913 };
 914
 915 static const u32 cmd3210[] = {
 916         0x0f0d0b0a, 0x17151311, 0x1f1d1b19, 0x1f1f1f1f,
 917         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
 918         0x18171615, 0x1f1f1c1a, 0x1f1f1f1f, 0x1f1f1f1f,
 919         0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
 920 };
 921
 922 static const u32 clk2030[] = {
 923         0x0e0d0d0c, 0x100f0f0e, 0x100f0e0d, 0x15131211,
 924         0x1d1b1917, 0x2523211f, 0x2a282927, 0x32302e2c,
 925         0x17161514, 0x1b1a1918, 0x1f1e1d1c, 0x23222120,
 926         0x27262524, 0x2d2b2928, 0x3533312f, 0x3d3b3937
 927 };
 928
 929 static const u32 ctl3215[] = {
 930         0x01010000, 0x03020101, 0x07060504, 0x0b0a0908,
 931         0x100f0e0d, 0x14131211, 0x18171615, 0x1c1b1a19,
 932         0x05040403, 0x07060605, 0x0a090807, 0x0f0d0c0b,
 933         0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d
 934 };
 935
 936 static const u32 ctl3220[] = {
 937         0x05040403, 0x07060505, 0x0e0c0a08, 0x1a171411,
 938         0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e,
 939         0x09080807, 0x0b0a0a09, 0x0f0d0c0b, 0x1b171311,
 940         0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e
 941 };
 942
 943 static const u32 nc[] = {
 944         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 945         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 946         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 947         0x00000000, 0x00000000, 0x00000000, 0x00000000
 948 };
 949
 950 enum {
 951         DQ2030,
 952         DQ2330,
 953         CMD2710,
 954         CMD3210,
 955         CLK2030,
 956         CTL3215,
 957         CTL3220,
 958         NC,
 959 };
 960
 961 static const u8 dual_channel_slew_group_lookup[] = {
 962         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 963         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 964         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 965         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710,
 966         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 967
 968         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 969         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 970         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 971         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD2710,
 972         DQ2030, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
 973
 974         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 975         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 976         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 977         DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710,
 978         DQ2030, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 979
 980         DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 981         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 982         DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210,
 983         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      DQ2030, CMD2710,
 984         DQ2030, CMD2710, CTL3215, NC,      CLK2030, NC,      NC,     NC,
 985
 986         NC,     NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 987         NC,     NC,      CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
 988         NC,     NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
 989         NC,     NC,      CTL3215, NC,      CLK2030, CLK2030, DQ2030, CMD2710
 990 };
 991
 992 static const u8 single_channel_slew_group_lookup[] = {
 993         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 994         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 995         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
 996         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
 997         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
 998
 999         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1000         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1001         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1002         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1003         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
1004
1005         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
1006         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1007         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, DQ2330, CMD3210,
1008         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1009         DQ2330, CMD3210, NC,      CTL3215, NC,      CLK2030, NC,     NC,
1010
1011         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1012         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1013         DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210,
1014         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      DQ2330, CMD3210,
1015         DQ2330, CMD3210, CTL3215, NC,      CLK2030, NC,      NC,     NC,
1016
1017         DQ2330, NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
1018         DQ2330, NC,      CTL3215, NC,      CLK2030, NC,      DQ2030, CMD3210,
1019         DQ2330, NC,      NC,      CTL3215, NC,      CLK2030, DQ2030, CMD3210,
1020         DQ2330, NC,      CTL3215, NC,      CLK2030, CLK2030, DQ2030, CMD3210
1021 };
1022
1023 static const u32 *slew_group_lookup(int dual_channel, int index)
1024 {
1025         const u8 *slew_group;
1026         /* Dual Channel needs different tables. */
1027         if (dual_channel)
1028                 slew_group   = dual_channel_slew_group_lookup;
1029         else
1030                 slew_group   = single_channel_slew_group_lookup;
1031
1032         switch (slew_group[index]) {
1033         case DQ2030:    return dq2030;
1034         case DQ2330:    return dq2330;
1035         case CMD2710:   return cmd2710;
1036         case CMD3210:   return cmd3210;
1037         case CLK2030:   return clk2030;
1038         case CTL3215:   return ctl3215;
1039         case CTL3220:   return ctl3220;
1040         case NC:        return nc;
1041         }
1042
1043         return nc;
1044 }
1045
1046 #ifdef CHIPSET_I945GM
1047 /* Strength multiplier tables */
1048 static const u8 dual_channel_strength_multiplier[] = {
1049         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1050         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1051         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1052         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
1053         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1054         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1055         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1056         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1057         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
1058         0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1059         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1060         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1061         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1062         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22,
1063         0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1064         0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1065         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1066         0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
1067         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22,
1068         0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1069         0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1070         0x00, 0x00, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11,
1071         0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11,
1072         0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x44, 0x22
1073 };
1074
1075 static const u8 single_channel_strength_multiplier[] = {
1076         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1077         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1078         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1079         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1080         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1081         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1082         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1083         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1084         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1085         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1086         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1087         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1088         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1089         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1090         0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00,
1091         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1092         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1093         0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11,
1094         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1095         0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00,
1096         0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1097         0x33, 0x00, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11,
1098         0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,
1099         0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11
1100 };
1101 #endif
1102 #ifdef CHIPSET_I945GC
1103 static const u8 dual_channel_strength_multiplier[] = {
1104         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1105         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1106         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1107         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1108         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1109         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1110         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1111         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1112         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1113         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1114         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1115         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1116         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1117         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1118         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1119         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1120         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1121         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1122         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
1123         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1124         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1125         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1126         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
1127         0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33
1128 };
1129
1130 static const u8 single_channel_strength_multiplier[] = {
1131         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1132         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1133         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1134         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1135         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1136         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1137         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1138         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1139         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1140         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1141         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1142         0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1143         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1144         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1145         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1146         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1147         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1148         0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1149         0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1150         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1151         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1152         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1153         0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
1154         0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00
1155 };
1156 #endif
1157
1158 static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
1159 {
1160         const u8 * strength_multiplier;
1161         int idx, dual_channel;
1162
1163         /* Set Strength Multipliers */
1164
1165         /* Dual Channel needs different tables. */
1166         if (sdram_capabilities_dual_channel()) {
1167                 printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n");
1168                 strength_multiplier = dual_channel_strength_multiplier;
1169                 dual_channel = 1;
1170                 idx = 5 * sysinfo->dimm[0] +  sysinfo->dimm[2];
1171         } else {
1172                 printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n");
1173                 strength_multiplier = single_channel_strength_multiplier;
1174                 dual_channel = 0;
1175                 idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1];
1176         }
1177
1178         printk(BIOS_DEBUG, "Table Index: %d\n", idx);
1179
1180         MCHBAR8(G1SC) = strength_multiplier[idx * 8 + 0];
1181         MCHBAR8(G2SC) = strength_multiplier[idx * 8 + 1];
1182         MCHBAR8(G3SC) = strength_multiplier[idx * 8 + 2];
1183         MCHBAR8(G4SC) = strength_multiplier[idx * 8 + 3];
1184         MCHBAR8(G5SC) = strength_multiplier[idx * 8 + 4];
1185         MCHBAR8(G6SC) = strength_multiplier[idx * 8 + 5];
1186         MCHBAR8(G7SC) = strength_multiplier[idx * 8 + 6];
1187         MCHBAR8(G8SC) = strength_multiplier[idx * 8 + 7];
1188
1189         /* Channel 0 */
1190         sdram_write_slew_rates(G1SRPUT, slew_group_lookup(dual_channel, idx * 8 + 0));
1191         sdram_write_slew_rates(G2SRPUT, slew_group_lookup(dual_channel, idx * 8 + 1));
1192         if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED)) {
1193
1194                 sdram_write_slew_rates(G3SRPUT, ctl3220);
1195         } else {
1196                 sdram_write_slew_rates(G3SRPUT, slew_group_lookup(dual_channel, idx * 8 + 2));
1197         }
1198         sdram_write_slew_rates(G4SRPUT, slew_group_lookup(dual_channel, idx * 8 + 3));
1199         sdram_write_slew_rates(G5SRPUT, slew_group_lookup(dual_channel, idx * 8 + 4));
1200         sdram_write_slew_rates(G6SRPUT, slew_group_lookup(dual_channel, idx * 8 + 5));
1201
1202         /* Channel 1 */
1203         if (sysinfo->dual_channel) {
1204                 sdram_write_slew_rates(G7SRPUT, slew_group_lookup(dual_channel, idx * 8 + 6));
1205                 sdram_write_slew_rates(G8SRPUT, slew_group_lookup(dual_channel, idx * 8 + 7));
1206         } else {
1207                 sdram_write_slew_rates(G7SRPUT, nc);
1208                 sdram_write_slew_rates(G8SRPUT, nc);
1209         }
1210 }
1211
1212 static void sdram_enable_rcomp(void)
1213 {
1214         u32 reg32;
1215         /* Enable Global Periodic RCOMP */
1216         udelay(300);
1217         reg32 = MCHBAR32(GBRCOMPCTL);
1218         reg32 &= ~(1 << 23);
1219         MCHBAR32(GBRCOMPCTL) = reg32;
1220 }
1221
1222 static void sdram_program_dll_timings(struct sys_info *sysinfo)
1223 {
1224         u32 chan0dll = 0, chan1dll = 0;
1225         int i;
1226
1227         printk(BIOS_DEBUG, "Programming DLL Timings... \n");
1228
1229         MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) );
1230         MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
1231
1232         /* We drive both channels with the same speed */
1233         switch (sysinfo->memory_frequency) {
1234         case 400: chan0dll = 0x26262626; chan1dll=0x26262626; break; /* 400MHz */
1235         case 533: chan0dll = 0x22222222; chan1dll=0x22222222; break; /* 533MHz */
1236         case 667: chan0dll = 0x11111111; chan1dll=0x11111111; break; /* 667MHz */
1237         }
1238
1239         for (i=0; i < 4; i++) {
1240                 MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = chan0dll;
1241                 MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = chan0dll;
1242                 MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = chan1dll;
1243                 MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = chan1dll;
1244         }
1245 }
1246
1247 static void sdram_force_rcomp(void)
1248 {
1249         u32 reg32;
1250         u8 reg8;
1251
1252         reg32 = MCHBAR32(ODTC);
1253         reg32 |= (1 << 28);
1254         MCHBAR32(ODTC) = reg32;
1255
1256         reg32 = MCHBAR32(SMSRCTL);
1257         reg32 |= (1 << 0);
1258         MCHBAR32(SMSRCTL) = reg32;
1259
1260         /* Start initial RCOMP */
1261         reg32 = MCHBAR32(GBRCOMPCTL);
1262         reg32 |= (1 << 8);
1263         MCHBAR32(GBRCOMPCTL) = reg32;
1264
1265         reg8 = i945_silicon_revision();
1266         if ((reg8 == 0 && (MCHBAR32(DCC) & (3 << 0)) == 0) || (reg8 == 1)) {
1267
1268                 reg32 = MCHBAR32(GBRCOMPCTL);
1269                 reg32 |= (3 << 5);
1270                 MCHBAR32(GBRCOMPCTL) = reg32;
1271         }
1272 }
1273
1274 static void sdram_initialize_system_memory_io(struct sys_info *sysinfo)
1275 {
1276         u8 reg8;
1277         u32 reg32;
1278
1279         printk(BIOS_DEBUG, "Initializing System Memory IO... \n");
1280         /* Enable Data Half Clock Pushout */
1281         reg8 = MCHBAR8(C0HCTC);
1282         reg8 &= ~0x1f;
1283         reg8 |= ( 1 << 0);
1284         MCHBAR8(C0HCTC) = reg8;
1285
1286         reg8 = MCHBAR8(C1HCTC);
1287         reg8 &= ~0x1f;
1288         reg8 |= ( 1 << 0);
1289         MCHBAR8(C1HCTC) = reg8;
1290
1291         MCHBAR16(WDLLBYPMODE) &= ~( (1 << 9) | (1 << 6) | (1 << 4) | (1 << 3) | (1 << 1) );
1292         MCHBAR16(WDLLBYPMODE) |= (1 << 8) | (1 << 7) | (1 << 5) | (1 << 2) | (1 << 0);
1293
1294         MCHBAR8(C0WDLLCMC) = 0;
1295         MCHBAR8(C1WDLLCMC) = 0;
1296
1297         /* Program RCOMP Settings */
1298         sdram_program_dram_width(sysinfo);
1299
1300         sdram_rcomp_buffer_strength_and_slew(sysinfo);
1301
1302         /* Indicate that RCOMP programming is done */
1303         reg32 = MCHBAR32(GBRCOMPCTL);
1304         reg32 &= ~( (1 << 29) | (1 << 26) | (3 << 21) | (3 << 2) );
1305         reg32 |= (3 << 27) | (3 << 0);
1306         MCHBAR32(GBRCOMPCTL) = reg32;
1307
1308         MCHBAR32(GBRCOMPCTL) |= (1 << 10);
1309
1310         /* Program DLL Timings */
1311         sdram_program_dll_timings(sysinfo);
1312
1313         /* Force RCOMP cycle */
1314         sdram_force_rcomp();
1315 }
1316
1317 static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
1318 {
1319         u32 reg32;
1320
1321         printk(BIOS_DEBUG, "Enabling System Memory IO... \n");
1322
1323         reg32 = MCHBAR32(RCVENMT);
1324         reg32 &= ~(0x3f << 6);
1325         MCHBAR32(RCVENMT) = reg32; /* [11:6] = 0 */
1326
1327         reg32 |= (1 << 11) | (1 << 9);
1328         MCHBAR32(RCVENMT) = reg32;
1329
1330         reg32 = MCHBAR32(DRTST);
1331         reg32 |= (1 << 3) | (1 << 2);
1332         MCHBAR32(DRTST) = reg32;
1333
1334         reg32 = MCHBAR32(DRTST);
1335         reg32 |= (1 << 6) | (1 << 4);
1336         MCHBAR32(DRTST) = reg32;
1337
1338         asm volatile ("nop; nop;" ::: "memory");
1339
1340         reg32 = MCHBAR32(DRTST);
1341
1342         /* Is channel 0 populated? */
1343         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1344                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
1345                 reg32 |= (1 << 7) | (1 << 5);
1346         else
1347                 reg32 |= (1 << 31);
1348
1349         /* Is channel 1 populated? */
1350         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1351                         sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
1352                 reg32 |= (1 << 9) | (1 << 8);
1353         else
1354                 reg32 |= (1 << 30);
1355
1356         MCHBAR32(DRTST) = reg32;
1357
1358         /* Activate DRAM Channel IO Buffers */
1359         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
1360                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) {
1361                 reg32 = MCHBAR32(C0DRC1);
1362                 reg32 |= (1 << 8);
1363                 MCHBAR32(C0DRC1) = reg32;
1364         }
1365         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED ||
1366                         sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) {
1367                 reg32 = MCHBAR32(C1DRC1);
1368                 reg32 |= (1 << 8);
1369                 MCHBAR32(C1DRC1) = reg32;
1370         }
1371 }
1372
1373 struct dimm_size {
1374         unsigned long side1;
1375         unsigned long side2;
1376 };
1377
1378 static struct dimm_size sdram_get_dimm_size(u16 device)
1379 {
1380         /* Calculate the log base 2 size of a DIMM in bits */
1381         struct dimm_size sz;
1382         int value, low, rows, columns;
1383
1384         sz.side1 = 0;
1385         sz.side2 = 0;
1386
1387         rows = spd_read_byte(device, SPD_NUM_ROWS);     /* rows */
1388         if (rows < 0) goto hw_err;
1389         if ((rows & 0xf) == 0) goto val_err;
1390         sz.side1 += rows & 0xf;
1391
1392         columns = spd_read_byte(device, SPD_NUM_COLUMNS);       /* columns */
1393         if (columns < 0) goto hw_err;
1394         if ((columns & 0xf) == 0) goto val_err;
1395         sz.side1 += columns & 0xf;
1396
1397         value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); /* banks */
1398         if (value < 0) goto hw_err;
1399         if ((value & 0xff) == 0) goto val_err;
1400         sz.side1 += log2(value & 0xff);
1401
1402         /* Get the module data width and convert it to a power of two */
1403         value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB);       /* (high byte) */
1404         if (value < 0) goto hw_err;
1405         value &= 0xff;
1406         value <<= 8;
1407
1408         low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* (low byte) */
1409         if (low < 0) goto hw_err;
1410         value = value | (low & 0xff);
1411         if ((value != 72) && (value != 64)) goto val_err;
1412         sz.side1 += log2(value);
1413
1414         /* side 2 */
1415         value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);      /* number of physical banks */
1416
1417         if (value < 0) goto hw_err;
1418         value &= 7;
1419         value++;
1420         if (value == 1) goto out;
1421         if (value != 2) goto val_err;
1422
1423         /* Start with the symmetrical case */
1424         sz.side2 = sz.side1;
1425
1426         if ((rows & 0xf0) == 0) goto out;       /* If symmetrical we are done */
1427
1428         /* Don't die here, I have not come across any of these to test what
1429          * actually happens.
1430          */
1431         printk(BIOS_ERR, "Assymetric DIMMs are not supported by this chipset\n");
1432
1433         sz.side2 -= (rows & 0x0f);              /* Subtract out rows on side 1 */
1434         sz.side2 += ((rows >> 4) & 0x0f);       /* Add in rows on side 2 */
1435
1436         sz.side2 -= (columns & 0x0f);           /* Subtract out columns on side 1 */
1437         sz.side2 += ((columns >> 4) & 0x0f);    /* Add in columns on side 2 */
1438
1439         goto out;
1440
1441  val_err:
1442         die("Bad SPD value\n");
1443  hw_err:
1444         /* If a hardware error occurs the spd rom probably does not exist.
1445          * In this case report that there is no memory
1446          */
1447         sz.side1 = 0;
1448         sz.side2 = 0;
1449  out:
1450         return sz;
1451 }
1452
1453 static void sdram_detect_dimm_size(struct sys_info * sysinfo)
1454 {
1455         int i;
1456
1457         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1458                 struct dimm_size sz;
1459
1460                 sysinfo->banksize[i * 2] = 0;
1461                 sysinfo->banksize[(i * 2) + 1] = 0;
1462
1463                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1464                         continue;
1465
1466                 sz = sdram_get_dimm_size(DIMM_SPD_BASE + i);
1467
1468                 sysinfo->banks[i] = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_BANKS_PER_SDRAM);  /* banks */
1469
1470                 if (sz.side1 < 30)
1471                         die("DDR-II rank size smaller than 128MB is not supported.\n");
1472
1473                 sysinfo->banksize[i * 2] = 1 << (sz.side1 - 28);
1474
1475                 printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
1476
1477                 if (!sz.side2)
1478                         continue;
1479
1480                 /* If there is a second side, it has to have at least 128M, too */
1481                 if (sz.side2 < 30)
1482                         die("DDR-II rank size smaller than 128MB is not supported.\n");
1483
1484                 sysinfo->banksize[(i * 2) + 1] = 1 << (sz.side2 - 28);
1485
1486                 printk(BIOS_DEBUG, "DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
1487         }
1488 }
1489
1490 static int sdram_program_row_boundaries(struct sys_info *sysinfo)
1491 {
1492         int i;
1493         int cum0, cum1, tolud, tom;
1494
1495         printk(BIOS_DEBUG, "Setting RAM size... \n");
1496
1497         cum0 = 0;
1498         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1499                 cum0 += sysinfo->banksize[i];
1500                 MCHBAR8(C0DRB0+i) = cum0;
1501         }
1502
1503         /* Assume we continue in Channel 1 where we stopped in Channel 0 */
1504         cum1 = cum0;
1505
1506         /* Exception: Interleaved starts from the beginning */
1507         if (sysinfo->interleaved)
1508                 cum1 = 0;
1509
1510 #if 0
1511         /* Exception: Channel 1 is not populated. C1DRB stays zero */
1512         if (sysinfo->dimm[2] == SYSINFO_DIMM_NOT_POPULATED &&
1513                         sysinfo->dimm[3] == SYSINFO_DIMM_NOT_POPULATED)
1514                 cum1 = 0;
1515 #endif
1516
1517         for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
1518                 cum1 += sysinfo->banksize[i + 4];
1519                 MCHBAR8(C1DRB0+i) = cum1;
1520         }
1521
1522         /* Set TOLUD Top Of Low Usable DRAM */
1523         if (sysinfo->interleaved)
1524                 tolud = (cum0 + cum1) << 1;
1525         else
1526                 tolud = (cum1 ? cum1 : cum0)  << 1;
1527
1528         /* The TOM register has a different format */
1529         tom = tolud >> 3;
1530
1531         /* Limit the value of TOLUD to leave some space for PCI memory. */
1532         if (tolud > 0xd0)
1533                 tolud = 0xd0;   /* 3.25GB : 0.75GB */
1534
1535         pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);
1536
1537         printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
1538         printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
1539         printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
1540
1541         pci_write_config16(PCI_DEV(0,0,0), TOM, tom);
1542
1543         return 0;
1544 }
1545
1546 static int sdram_set_row_attributes(struct sys_info *sysinfo)
1547 {
1548         int i, value;
1549         u16 dra0=0, dra1=0, dra = 0;
1550
1551         printk(BIOS_DEBUG, "Setting row attributes... \n");
1552         for(i=0; i < 2 * DIMM_SOCKETS; i++) {
1553                 u16 device;
1554                 u8 columnsrows;
1555
1556                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) {
1557                         continue;
1558                 }
1559
1560                 device = DIMM_SPD_BASE + i;
1561
1562                 value = spd_read_byte(device, SPD_NUM_ROWS);    /* rows */
1563                 columnsrows = (value & 0x0f);
1564
1565                 value = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */
1566                 columnsrows |= (value & 0xf) << 4;
1567
1568                 switch (columnsrows) {
1569                 case 0x9d: dra = 2; break;
1570                 case 0xad: dra = 3; break;
1571                 case 0xbd: dra = 4; break;
1572                 case 0xae: dra = 3; break;
1573                 case 0xbe: dra = 4; break;
1574                 default: die("Unsupported Rows/Columns. (DRA)");
1575                 }
1576
1577                 /* Double Sided DIMMs? */
1578                 if (sysinfo->banksize[(2 * i) + 1] != 0) {
1579                         dra = (dra << 4) | dra;
1580                 }
1581
1582                 if (i < DIMM_SOCKETS)
1583                         dra0 |= (dra << (i*8));
1584                 else
1585                         dra1 |= (dra << ((i - DIMM_SOCKETS)*8));
1586         }
1587
1588         MCHBAR16(C0DRA0) = dra0;
1589         MCHBAR16(C1DRA0) = dra1;
1590
1591         printk(BIOS_DEBUG, "C0DRA = 0x%04x\n", dra0);
1592         printk(BIOS_DEBUG, "C1DRA = 0x%04x\n", dra1);
1593
1594         return 0;
1595 }
1596
1597 static void sdram_set_bank_architecture(struct sys_info *sysinfo)
1598 {
1599         u32 off32;
1600         int i;
1601
1602         MCHBAR16(C1BNKARC) &= 0xff00;
1603         MCHBAR16(C0BNKARC) &= 0xff00;
1604
1605         off32 = C0BNKARC;
1606         for (i=0; i < 2 * DIMM_SOCKETS; i++) {
1607                 /* Switch to second channel */
1608                 if (i == DIMM_SOCKETS)
1609                         off32 = C1BNKARC;
1610
1611                 if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED)
1612                         continue;
1613
1614                 if (sysinfo->banks[i] != 8)
1615                         continue;
1616
1617                 printk(BIOS_SPEW, "DIMM%d has 8 banks.\n", i);
1618
1619                 if (i & 1)
1620                         MCHBAR16(off32) |= 0x50;
1621                 else
1622                         MCHBAR16(off32) |= 0x05;
1623         }
1624 }
1625
1626 #define REFRESH_7_8US   1
1627 #define REFRESH_15_6US  0
1628 static void sdram_program_refresh_rate(struct sys_info *sysinfo)
1629 {
1630         u32 reg32;
1631
1632         if (sysinfo->refresh == REFRESH_7_8US) {
1633                 reg32 = (2 << 8); /* Refresh enabled at 7.8us */
1634         } else {
1635                 reg32 = (1 << 8); /* Refresh enabled at 15.6us */
1636         }
1637
1638         MCHBAR32(C0DRC0) &= ~(7 << 8);
1639         MCHBAR32(C0DRC0) |= reg32;
1640
1641         MCHBAR32(C1DRC0) &= ~(7 << 8);
1642         MCHBAR32(C1DRC0) |= reg32;
1643 }
1644
1645 static void sdram_program_cke_tristate(struct sys_info *sysinfo)
1646 {
1647         u32 reg32;
1648         int i;
1649
1650         reg32 = MCHBAR32(C0DRC1);
1651
1652         for (i=0; i < 4; i++) {
1653                 if (sysinfo->banksize[i] == 0) {
1654                         reg32 |= (1 << (16 + i));
1655                 }
1656         }
1657
1658         reg32 |= (1 << 12);
1659
1660         reg32 |= (1 << 11);
1661         MCHBAR32(C0DRC1) = reg32;
1662
1663         /* Do we have to do this if we're in Single Channel Mode?  */
1664         reg32 = MCHBAR32(C1DRC1);
1665
1666         for (i=4; i < 8; i++) {
1667                 if (sysinfo->banksize[i] == 0) {
1668                         reg32 |= (1 << (12 + i));
1669                 }
1670         }
1671
1672         reg32 |= (1 << 12);
1673
1674         reg32 |= (1 << 11);
1675         MCHBAR32(C1DRC1) = reg32;
1676 }
1677
1678 static void sdram_program_odt_tristate(struct sys_info *sysinfo)
1679 {
1680         u32 reg32;
1681         int i;
1682
1683         reg32 = MCHBAR32(C0DRC2);
1684
1685         for (i=0; i < 4; i++) {
1686                 if (sysinfo->banksize[i] == 0) {
1687                         reg32 |= (1 << (24 + i));
1688                 }
1689         }
1690         MCHBAR32(C0DRC2) = reg32;
1691
1692         reg32 = MCHBAR32(C1DRC2);
1693
1694         for (i=4; i < 8; i++) {
1695                 if (sysinfo->banksize[i] == 0) {
1696                         reg32 |= (1 << (20 + i));
1697                 }
1698         }
1699         MCHBAR32(C1DRC2) = reg32;
1700 }
1701
1702 static void sdram_set_timing_and_control(struct sys_info *sysinfo)
1703 {
1704         u32 reg32, off32;
1705         u32 tWTR;
1706         u32 temp_drt;
1707         int i, page_size;
1708
1709         static const u8 const drt0_table[] = {
1710           /* CL 3, 4, 5 */
1711                 3, 4, 5,        /* FSB533/400, DDR533/400 */
1712                 4, 5, 6,        /* FSB667, DDR533/400 */
1713                 4, 5, 6,        /* FSB667, DDR667 */
1714         };
1715
1716         static const u8 const cas_table[] = {
1717                 2, 1, 0, 3
1718         };
1719
1720         reg32 = MCHBAR32(C0DRC0);
1721         reg32 |= (1 << 2);      /* Burst Length 8 */
1722         reg32 &= ~( (1 << 13) | (1 << 12) );
1723         MCHBAR32(C0DRC0) = reg32;
1724
1725         reg32 = MCHBAR32(C1DRC0);
1726         reg32 |= (1 << 2);      /* Burst Length 8 */
1727         reg32 &= ~( (1 << 13) | (1 << 12) );
1728         MCHBAR32(C1DRC0) = reg32;
1729
1730         if (!sysinfo->dual_channel && sysinfo->dimm[1] !=
1731                         SYSINFO_DIMM_NOT_POPULATED) {
1732                 reg32 = MCHBAR32(C0DRC0);
1733                 reg32 |= (1 << 15);
1734                 MCHBAR32(C0DRC0) = reg32;
1735         }
1736
1737         sdram_program_refresh_rate(sysinfo);
1738
1739         sdram_program_cke_tristate(sysinfo);
1740
1741         sdram_program_odt_tristate(sysinfo);
1742
1743         /* Calculate DRT0 */
1744
1745         temp_drt = 0;
1746
1747         /* B2B Write Precharge (same bank) = CL-1 + BL/2 + tWR */
1748         reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + sysinfo->twr;
1749         temp_drt |= (reg32 << 28);
1750
1751         /* Write Auto Precharge (same bank) = CL-1 + BL/2 + tWR + tRP */
1752         reg32 += sysinfo->trp;
1753         temp_drt |= (reg32 << 4);
1754
1755         if (sysinfo->memory_frequency == 667) {
1756                 tWTR = 3; /* 667MHz */
1757         } else {
1758                 tWTR = 2; /* 400 and 533 */
1759         }
1760
1761         /* B2B Write to Read Command Spacing */
1762         reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + tWTR;
1763         temp_drt |= (reg32 << 24);
1764
1765         /* CxDRT0 [23:22], [21:20], [19:18] [16] have fixed values */
1766         temp_drt |= ( (1 << 22) | (3 << 20) | (1 << 18) | (0 << 16) );
1767
1768         /* Program Write Auto Precharge to Activate */
1769         off32 = 0;
1770         if (sysinfo->fsb_frequency == 667) { /* 667MHz FSB */
1771                 off32 += 3;
1772         }
1773         if (sysinfo->memory_frequency == 667) {
1774                 off32 += 3;
1775         }
1776         off32 += sysinfo->cas - 3;
1777         reg32 = drt0_table[off32];
1778         temp_drt |= (reg32 << 11);
1779
1780         /* Read Auto Precharge to Activate */
1781
1782         temp_drt |= (8 << 0);
1783
1784         MCHBAR32(C0DRT0) = temp_drt;
1785         MCHBAR32(C1DRT0) = temp_drt;
1786
1787         /* Calculate DRT1 */
1788
1789         temp_drt = MCHBAR32(C0DRT1) & 0x00020088;
1790
1791         /* DRAM RASB Precharge */
1792         temp_drt |= (sysinfo->trp - 2) << 0;
1793
1794         /* DRAM RASB to CASB Delay */
1795         temp_drt |= (sysinfo->trcd - 2) << 4;
1796
1797         /* CASB Latency */
1798         temp_drt |= (cas_table[sysinfo->cas - 3]) << 8;
1799
1800         /* Refresh Cycle Time */
1801         temp_drt |= (sysinfo->trfc) << 10;
1802
1803         /* Pre-All to Activate Delay */
1804         temp_drt |= (0 << 16);
1805
1806         /* Precharge to Precharge Delay stays at 1 clock */
1807         temp_drt |= (0 << 18);
1808
1809         /* Activate to Precharge Delay */
1810         temp_drt |= (sysinfo->tras << 19);
1811
1812         /* Read to Precharge (tRTP) */
1813         if (sysinfo->memory_frequency == 667) {
1814                 temp_drt |= (1 << 28);
1815         } else {
1816                 temp_drt |= (0 << 28);
1817         }
1818
1819         /* Determine page size */
1820         reg32 = 0;
1821         page_size = 1; /* Default: 1k pagesize */
1822         for (i=0; i< 2*DIMM_SOCKETS; i++) {
1823                 if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS ||
1824                                 sysinfo->dimm[i] == SYSINFO_DIMM_X16SS)
1825                         page_size = 2; /* 2k pagesize */
1826         }
1827
1828         if (sysinfo->memory_frequency == 533 && page_size == 2) {
1829                 reg32 = 1;
1830         }
1831         if (sysinfo->memory_frequency == 667) {
1832                 reg32 = page_size;
1833         }
1834
1835         temp_drt |= (reg32 << 30);
1836
1837         MCHBAR32(C0DRT1) = temp_drt;
1838         MCHBAR32(C1DRT1) = temp_drt;
1839
1840         /* Program DRT2 */
1841         reg32 = MCHBAR32(C0DRT2);
1842         reg32 &= ~(1 << 8);
1843         MCHBAR32(C0DRT2) = reg32;
1844
1845         reg32 = MCHBAR32(C1DRT2);
1846         reg32 &= ~(1 << 8);
1847         MCHBAR32(C1DRT2) = reg32;
1848
1849         /* Calculate DRT3 */
1850         temp_drt = MCHBAR32(C0DRT3) & ~0x07ffffff;
1851
1852         /* Get old tRFC value */
1853         reg32 = MCHBAR32(C0DRT1) >> 10;
1854         reg32 &= 0x3f;
1855
1856         /* 788nS - tRFC */
1857         switch (sysinfo->memory_frequency) {
1858         case 400: /* 5nS */
1859                 reg32 = ((78800 / 500) - reg32) & 0x1ff;
1860                 reg32 |= (0x8c << 16) | (0x0c << 10); /* 1 us */
1861                 break;
1862         case 533: /* 3.75nS */
1863                 reg32 = ((78800 / 375) - reg32) & 0x1ff;
1864                 reg32 |= (0xba << 16) | (0x10 << 10); /* 1 us */
1865                 break;
1866         case 667: /* 3nS */
1867                 reg32 = ((78800 / 300) - reg32) & 0x1ff;
1868                 reg32 |= (0xe9 << 16) | (0x14 << 10); /* 1 us */
1869                 break;
1870         }
1871
1872         temp_drt |= reg32;
1873
1874         MCHBAR32(C0DRT3) = temp_drt;
1875         MCHBAR32(C1DRT3) = temp_drt;
1876 }
1877
1878 static void sdram_set_channel_mode(struct sys_info *sysinfo)
1879 {
1880         u32 reg32;
1881
1882         printk(BIOS_DEBUG, "Setting mode of operation for memory channels...");
1883
1884         if (sdram_capabilities_interleave() &&
1885                     ( ( sysinfo->banksize[0] + sysinfo->banksize[1] +
1886                         sysinfo->banksize[2] + sysinfo->banksize[3] ) ==
1887                       ( sysinfo->banksize[4] + sysinfo->banksize[5] +
1888                         sysinfo->banksize[6] + sysinfo->banksize[7] ) ) ) {
1889                 /* Both channels equipped with DIMMs of the same size */
1890                 sysinfo->interleaved = 1;
1891         } else {
1892                 sysinfo->interleaved = 0;
1893         }
1894
1895         reg32 = MCHBAR32(DCC);
1896         reg32 &= ~(7 << 0);
1897
1898         if(sysinfo->interleaved) {
1899                 /* Dual Channel Interleaved */
1900                 printk(BIOS_DEBUG, "Dual Channel Interleaved.\n");
1901                 reg32 |= (1 << 1);
1902         } else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED &&
1903                         sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) {
1904                 /* Channel 1 only */
1905                 printk(BIOS_DEBUG, "Single Channel 1 only.\n");
1906                 reg32 |= (1 << 2);
1907         } else if (sdram_capabilities_dual_channel() && sysinfo->dimm[2] !=
1908                         SYSINFO_DIMM_NOT_POPULATED) {
1909                 /* Dual Channel Assymetric */
1910                 printk(BIOS_DEBUG, "Dual Channel Assymetric.\n");
1911                 reg32 |= (1 << 0);
1912         } else {
1913                 /* All bits 0 means Single Channel 0 operation */
1914                 printk(BIOS_DEBUG, "Single Channel 0 only.\n");
1915         }
1916
1917         /* Now disable channel XORing */
1918         reg32 |= (1 << 10);
1919
1920         MCHBAR32(DCC) = reg32;
1921
1922         PRINTK_DEBUG("DCC=0x%08x\n", MCHBAR32(DCC));
1923 }
1924
1925 static void sdram_program_pll_settings(struct sys_info *sysinfo)
1926 {
1927         volatile u16 reg16;
1928
1929         MCHBAR32(PLLMON) = 0x80800000;
1930
1931         sysinfo->fsb_frequency = fsbclk();
1932         if (sysinfo->fsb_frequency == -1)
1933                 die("Unsupported FSB speed");
1934
1935         /* Program CPCTL according to FSB speed */
1936         /* Only write the lower byte */
1937         switch (sysinfo->fsb_frequency) {
1938         case 400: MCHBAR8(CPCTL) = 0x90; break; /* FSB400 */
1939         case 533: MCHBAR8(CPCTL) = 0x95; break; /* FSB533 */
1940         case 667: MCHBAR8(CPCTL) = 0x8d; break; /* FSB667 */
1941         }
1942
1943         MCHBAR16(CPCTL) &= ~(1 << 11);
1944
1945         reg16 = MCHBAR16(CPCTL); /* Read back register to activate settings */
1946 }
1947
1948 static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
1949 {
1950         u8  reg8;
1951         u16 reg16;
1952         u8  freq, second_vco, voltage;
1953
1954 #define CRCLK_166MHz    0x00
1955 #define CRCLK_200MHz    0x01
1956 #define CRCLK_250MHz    0x03
1957 #define CRCLK_400MHz    0x05
1958
1959 #define CDCLK_200MHz    0x00
1960 #define CDCLK_320MHz    0x40
1961
1962 #define VOLTAGE_1_05    0x00
1963 #define VOLTAGE_1_50    0x01
1964
1965         printk(BIOS_DEBUG, "Setting Graphics Frequency... \n");
1966
1967         printk(BIOS_DEBUG, "FSB: %d MHz ", sysinfo->fsb_frequency);
1968
1969         voltage = VOLTAGE_1_05;
1970         if (MCHBAR32(DFT_STRAP1) & (1 << 20))
1971                 voltage = VOLTAGE_1_50;
1972         printk(BIOS_DEBUG, "Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
1973
1974         /* Gate graphics hardware for frequency change */
1975         reg8 = pci_read_config16(PCI_DEV(0,2,0), GCFC + 1);
1976         reg8 = (1<<3) | (1<<1); /* disable crclk, gate cdclk */
1977         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
1978
1979         /* Get graphics frequency capabilities */
1980         reg8 = sdram_capabilities_core_frequencies();
1981
1982         freq = CRCLK_250MHz;
1983         switch (reg8) {
1984         case GFX_FREQUENCY_CAP_ALL:
1985                 if (voltage == VOLTAGE_1_05)
1986                         freq = CRCLK_250MHz;
1987                 else
1988                         freq = CRCLK_400MHz; /* 1.5V requires 400MHz */
1989                 break;
1990         case GFX_FREQUENCY_CAP_250MHZ: freq = CRCLK_250MHz; break;
1991         case GFX_FREQUENCY_CAP_200MHZ: freq = CRCLK_200MHz; break;
1992         case GFX_FREQUENCY_CAP_166MHZ: freq = CRCLK_166MHz; break;
1993         }
1994
1995         if (freq != CRCLK_400MHz) {
1996                 /* What chipset are we? Force 166MHz for GMS */
1997                 reg8 = (pci_read_config8(PCI_DEV(0, 0x00,0), 0xe7) & 0x70) >> 4;
1998                 if (reg8==2)
1999                         freq = CRCLK_166MHz;
2000         }
2001
2002         printk(BIOS_DEBUG, "Render: ");
2003         switch (freq) {
2004         case CRCLK_166MHz: printk(BIOS_DEBUG, "166Mhz"); break;
2005         case CRCLK_200MHz: printk(BIOS_DEBUG, "200Mhz"); break;
2006         case CRCLK_250MHz: printk(BIOS_DEBUG, "250Mhz"); break;
2007         case CRCLK_400MHz: printk(BIOS_DEBUG, "400Mhz"); break;
2008         }
2009
2010         if (i945_silicon_revision() == 0) {
2011                 sysinfo->mvco4x = 1;
2012         } else {
2013                 sysinfo->mvco4x = 0;
2014         }
2015
2016         second_vco = 0;
2017
2018         if (voltage == VOLTAGE_1_50) {
2019                 second_vco = 1;
2020         } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz))  {
2021                 u16 mem = sysinfo->memory_frequency;
2022                 u16 fsb = sysinfo->fsb_frequency;
2023
2024                 if ( (fsb == 667 && mem == 533) ||
2025                      (fsb == 533 && mem == 533) ||
2026                      (fsb == 533 && mem == 400)) {
2027                         second_vco = 1;
2028                 }
2029
2030                 if (fsb == 667 && mem == 533)
2031                         sysinfo->mvco4x = 1;
2032         }
2033
2034         if (second_vco) {
2035                 sysinfo->clkcfg_bit7=1;
2036         } else {
2037                 sysinfo->clkcfg_bit7=0;
2038         }
2039
2040         /* Graphics Core Render Clock */
2041         reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC);
2042         reg16 &= ~( (7 << 0) | (1 << 13) );
2043         reg16 |= freq;
2044         pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
2045
2046         /* Graphics Core Display Clock */
2047         reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC);
2048         reg8 &= ~( (1<<7) | (7<<4) );
2049
2050         if (voltage == VOLTAGE_1_05) {
2051                 reg8 |= CDCLK_200MHz;
2052                 printk(BIOS_DEBUG, " Display: 200MHz\n");
2053         } else {
2054                 reg8 |= CDCLK_320MHz;
2055                 printk(BIOS_DEBUG, " Display: 320MHz\n");
2056         }
2057         pci_write_config8(PCI_DEV(0,2,0), GCFC, reg8);
2058
2059         reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC + 1);
2060
2061         reg8 |= (1<<3) | (1<<1);
2062         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2063
2064         reg8 |= 0x0f;
2065         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2066
2067         /* Ungate core render and display clocks */
2068         reg8 &= 0xf0;
2069         pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
2070 }
2071
2072 static void sdram_program_memory_frequency(struct sys_info *sysinfo)
2073 {
2074         u32 clkcfg;
2075         u8 reg8;
2076
2077         printk(BIOS_DEBUG, "Setting Memory Frequency... ");
2078
2079         clkcfg = MCHBAR32(CLKCFG);
2080
2081         printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", clkcfg);
2082
2083         clkcfg &= ~( (1 << 12) | (1 << 7) | ( 7 << 4) );
2084
2085         if (sysinfo->mvco4x) {
2086                 printk(BIOS_DEBUG, "MVCO 4x, ");
2087                 clkcfg &= ~(1 << 12);
2088         }
2089
2090         if (sysinfo->clkcfg_bit7) {
2091                 printk(BIOS_DEBUG, "second VCO, ");
2092
2093                 clkcfg |= (1 << 7);
2094         }
2095
2096         switch (sysinfo->memory_frequency) {
2097         case 400: clkcfg |= (2 << 4); break;
2098         case 533: clkcfg |= (3 << 4); break;
2099         case 667: clkcfg |= (4 << 4); break;
2100         default: die("Target Memory Frequency Error");
2101         }
2102
2103         if (MCHBAR32(CLKCFG) == clkcfg) {
2104                 printk(BIOS_DEBUG, "ok (unchanged)\n");
2105                 return;
2106         }
2107
2108         MCHBAR32(CLKCFG) = clkcfg;
2109
2110         /* Make sure the following code is in the
2111          * cache before we execute it.
2112          */
2113         goto cache_code;
2114 vco_update:
2115         reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
2116         reg8 &= ~(1 << 7);
2117         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
2118
2119         clkcfg &= ~(1 << 10);
2120         MCHBAR32(CLKCFG) = clkcfg;
2121         clkcfg |= (1 << 10);
2122         MCHBAR32(CLKCFG) = clkcfg;
2123
2124         asm volatile (
2125                 "       movl $0x100, %%ecx\n"
2126                 "delay_update:\n"
2127                 "       nop\n"
2128                 "       nop\n"
2129                 "       nop\n"
2130                 "       nop\n"
2131                 "       loop delay_update\n"
2132                 : /* No outputs */
2133                 : /* No inputs */
2134                 : "%ecx", "memory"
2135                 );
2136
2137         clkcfg &= ~(1 << 10);
2138         MCHBAR32(CLKCFG) = clkcfg;
2139
2140         goto out;
2141 cache_code:
2142         goto vco_update;
2143 out:
2144
2145         printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
2146         printk(BIOS_DEBUG, "ok\n");
2147 }
2148
2149 static void sdram_program_clock_crossing(void)
2150 {
2151         int idx = 0;
2152
2153         /**
2154          * We add the indices according to our clocks from CLKCFG.
2155          */
2156 #ifdef CHIPSET_I945GM
2157         static const u32 data_clock_crossing[] = {
2158                 0x00100401, 0x00000000, /* DDR400 FSB400 */
2159                 0xffffffff, 0xffffffff, /*  nonexistant  */
2160                 0xffffffff, 0xffffffff, /*  nonexistant  */
2161
2162                 0x08040120, 0x00000000, /* DDR400 FSB533 */
2163                 0x00100401, 0x00000000, /* DDR533 FSB533 */
2164                 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
2165
2166                 0x04020120, 0x00000010, /* DDR400 FSB667 */
2167                 0x10040280, 0x00000040, /* DDR533 FSB667 */
2168                 0x00100401, 0x00000000, /* DDR667 FSB667 */
2169
2170                 0xffffffff, 0xffffffff, /*  nonexistant  */
2171                 0xffffffff, 0xffffffff, /*  nonexistant  */
2172                 0xffffffff, 0xffffffff, /*  nonexistant  */
2173
2174                 0xffffffff, 0xffffffff, /*  nonexistant  */
2175                 0xffffffff, 0xffffffff, /*  nonexistant  */
2176                 0xffffffff, 0xffffffff, /*  nonexistant  */
2177         };
2178
2179         static const u32 command_clock_crossing[] = {
2180                 0x04020208, 0x00000000, /* DDR400 FSB400 */
2181                 0xffffffff, 0xffffffff, /*  nonexistant  */
2182                 0xffffffff, 0xffffffff, /*  nonexistant  */
2183
2184                 0x00060108, 0x00000000, /* DDR400 FSB533 */
2185                 0x04020108, 0x00000000, /* DDR533 FSB533 */
2186                 0xffffffff, 0xffffffff, /*  nonexistant  */
2187
2188                 0x00040318, 0x00000000, /* DDR400 FSB667 */
2189                 0x04020118, 0x00000000, /* DDR533 FSB667 */
2190                 0x02010804, 0x00000000, /* DDR667 FSB667 */
2191
2192                 0xffffffff, 0xffffffff, /*  nonexistant  */
2193                 0xffffffff, 0xffffffff, /*  nonexistant  */
2194                 0xffffffff, 0xffffffff, /*  nonexistant  */
2195
2196                 0xffffffff, 0xffffffff, /*  nonexistant  */
2197                 0xffffffff, 0xffffffff, /*  nonexistant  */
2198                 0xffffffff, 0xffffffff, /*  nonexistant  */
2199         };
2200
2201 #endif
2202 #ifdef CHIPSET_I945GC
2203         /* i945 G/P */
2204         static const u32 data_clock_crossing[] = {
2205                 0xffffffff, 0xffffffff, /*  nonexistant  */
2206                 0xffffffff, 0xffffffff, /*  nonexistant  */
2207                 0xffffffff, 0xffffffff, /*  nonexistant  */
2208
2209                 0x10080201, 0x00000000, /* DDR400 FSB533 */
2210                 0x00100401, 0x00000000, /* DDR533 FSB533 */
2211                 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */
2212
2213                 0xffffffff, 0xffffffff, /*  nonexistant  */
2214                 0xffffffff, 0xffffffff, /*  nonexistant  */
2215                 0xffffffff, 0xffffffff, /*  nonexistant  */
2216
2217                 0x04020108, 0x00000000, /* DDR400 FSB800 */
2218                 0x00020108, 0x00000000, /* DDR533 FSB800 */
2219                 0x00080201, 0x00000000, /* DDR667 FSB800 */
2220
2221                 0x00010402, 0x00000000, /* DDR400 FSB1066 */
2222                 0x04020108, 0x00000000, /* DDR533 FSB1066 */
2223                 0x08040110, 0x00000000, /* DDR667 FSB1066 */
2224         };
2225
2226         static const u32 command_clock_crossing[] = {
2227                 0xffffffff, 0xffffffff, /*  nonexistant  */
2228                 0xffffffff, 0xffffffff, /*  nonexistant  */
2229                 0xffffffff, 0xffffffff, /*  nonexistant  */
2230
2231                 0x00010800, 0x00000402, /* DDR400 FSB533 */
2232                 0x01000400, 0x00000200, /* DDR533 FSB533 */
2233                 0x00020904, 0x00000000, /* DDR667 FSB533 - fake values */
2234
2235                 0xffffffff, 0xffffffff, /*  nonexistant  */
2236                 0xffffffff, 0xffffffff, /*  nonexistant  */
2237                 0xffffffff, 0xffffffff, /*  nonexistant  */
2238
2239                 0x02010804, 0x00000000, /* DDR400 FSB800 */
2240                 0x00010402, 0x00000000, /* DDR533 FSB800 */
2241                 0x04020180, 0x00000008, /* DDR667 FSB800 */
2242
2243                 0x00020904, 0x00000000, /* DDR400 FSB1066 */
2244                 0x02010804, 0x00000000, /* DDR533 FSB1066 */
2245                 0x180601c0, 0x00000020, /* DDR667 FSB1066 */
2246         };
2247 #endif
2248
2249         printk(BIOS_DEBUG, "Programming Clock Crossing...");
2250
2251         printk(BIOS_DEBUG, "MEM=");
2252         switch (memclk()) {
2253         case 400:       printk(BIOS_DEBUG, "400"); idx += 0; break;
2254         case 533:       printk(BIOS_DEBUG, "533"); idx += 2; break;
2255         case 667:       printk(BIOS_DEBUG, "667"); idx += 4; break;
2256         default: printk(BIOS_DEBUG, "RSVD %x", memclk()); return;
2257         }
2258
2259         printk(BIOS_DEBUG, " FSB=");
2260         switch (fsbclk()) {
2261         case 400:       printk(BIOS_DEBUG, "400"); idx += 0; break;
2262         case 533:       printk(BIOS_DEBUG, "533"); idx += 6; break;
2263         case 667:       printk(BIOS_DEBUG, "667"); idx += 12; break;
2264         case 800:       printk(BIOS_DEBUG, "800"); idx += 18; break;
2265         case 1066:      printk(BIOS_DEBUG, "1066"); idx += 24; break;
2266         default: printk(BIOS_DEBUG, "RSVD %x\n", fsbclk()); return;
2267         }
2268
2269         if (command_clock_crossing[idx]==0xffffffff) {
2270                 printk(BIOS_DEBUG, "Invalid MEM/FSB combination!\n");
2271         }
2272
2273         MCHBAR32(CCCFT + 0) = command_clock_crossing[idx];
2274         MCHBAR32(CCCFT + 4) = command_clock_crossing[idx + 1];
2275
2276         MCHBAR32(C0DCCFT + 0) = data_clock_crossing[idx];
2277         MCHBAR32(C0DCCFT + 4) = data_clock_crossing[idx + 1];
2278         MCHBAR32(C1DCCFT + 0) = data_clock_crossing[idx];
2279         MCHBAR32(C1DCCFT + 4) = data_clock_crossing[idx + 1];
2280
2281         printk(BIOS_DEBUG, "... ok\n");
2282 }
2283
2284 static void sdram_disable_fast_dispatch(void)
2285 {
2286         u32 reg32;
2287
2288         reg32 = MCHBAR32(FSBPMC3);
2289         reg32 |= (1 << 1);
2290         MCHBAR32(FSBPMC3) = reg32;
2291
2292         reg32 = MCHBAR32(SBTEST);
2293         reg32 |= (3 << 1);
2294         MCHBAR32(SBTEST) = reg32;
2295 }
2296
2297 static void sdram_pre_jedec_initialization(void)
2298 {
2299         u32 reg32;
2300
2301         reg32 = MCHBAR32(WCC);
2302         reg32 &= 0x113ff3ff;
2303         reg32 |= (4 << 29) | (3 << 25) | (1 << 10);
2304         MCHBAR32(WCC) = reg32;
2305
2306         MCHBAR32(SMVREFC) |= (1 << 6);
2307
2308         MCHBAR32(MMARB0) &= ~(3 << 17);
2309         MCHBAR32(MMARB0) |= (1 << 21) | (1 << 16);
2310
2311         MCHBAR32(MMARB1) &= ~(7 << 8);
2312         MCHBAR32(MMARB1) |= (3 << 8);
2313
2314         /* Adaptive Idle Timer Control */
2315         MCHBAR32(C0AIT) = 0x000006c4;
2316         MCHBAR32(C0AIT+4) = 0x871a066d;
2317
2318         MCHBAR32(C1AIT) = 0x000006c4;
2319         MCHBAR32(C1AIT+4) = 0x871a066d;
2320 }
2321
2322 #define EA_DUALCHANNEL_XOR_BANK_RANK_MODE       (0xd4 << 24)
2323 #define EA_DUALCHANNEL_XOR_BANK_MODE            (0xf4 << 24)
2324 #define EA_DUALCHANNEL_BANK_RANK_MODE           (0xc2 << 24)
2325 #define EA_DUALCHANNEL_BANK_MODE                (0xe2 << 24)
2326 #define EA_SINGLECHANNEL_XOR_BANK_RANK_MODE     (0x91 << 24)
2327 #define EA_SINGLECHANNEL_XOR_BANK_MODE          (0xb1 << 24)
2328 #define EA_SINGLECHANNEL_BANK_RANK_MODE         (0x80 << 24)
2329 #define EA_SINGLECHANNEL_BANK_MODE              (0xa0 << 24)
2330
2331 static void sdram_enhanced_addressing_mode(struct sys_info *sysinfo)
2332 {
2333         u32 chan0 = 0, chan1 = 0;
2334         int chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated;
2335
2336         chan0_populated =  (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2337                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2338         chan1_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
2339                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED);
2340         chan0_dualsided = (sysinfo->banksize[1] || sysinfo->banksize[3]);
2341         chan1_dualsided = (sysinfo->banksize[5] || sysinfo->banksize[7]);
2342
2343         if (sdram_capabilities_enhanced_addressing_xor()) {
2344                 if (!sysinfo->interleaved) {
2345                         /* Single Channel & Dual Channel Assymetric */
2346                         if (chan0_populated) {
2347                                 if (chan0_dualsided) {
2348                                         chan0 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2349                                 } else {
2350                                         chan0 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2351                                 }
2352                         }
2353                         if (chan1_populated) {
2354                                 if (chan1_dualsided) {
2355                                         chan1 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE;
2356                                 } else {
2357                                         chan1 = EA_SINGLECHANNEL_XOR_BANK_MODE;
2358                                 }
2359                         }
2360                 } else {
2361                         /* Interleaved has always both channels populated */
2362                         if (chan0_dualsided) {
2363                                 chan0 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2364                         } else {
2365                                 chan0 = EA_DUALCHANNEL_XOR_BANK_MODE;
2366                         }
2367
2368                         if (chan1_dualsided) {
2369                                 chan1 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE;
2370                         } else {
2371                                 chan1 = EA_DUALCHANNEL_XOR_BANK_MODE;
2372                         }
2373                 }
2374         } else {
2375                 if (!sysinfo->interleaved) {
2376                         /* Single Channel & Dual Channel Assymetric */
2377                         if (chan0_populated) {
2378                                 if (chan0_dualsided) {
2379                                         chan0 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2380                                 } else {
2381                                         chan0 = EA_SINGLECHANNEL_BANK_MODE;
2382                                 }
2383                         }
2384                         if (chan1_populated) {
2385                                 if (chan1_dualsided) {
2386                                         chan1 = EA_SINGLECHANNEL_BANK_RANK_MODE;
2387                                 } else {
2388                                         chan1 = EA_SINGLECHANNEL_BANK_MODE;
2389                                 }
2390                         }
2391                 } else {
2392                         /* Interleaved has always both channels populated */
2393                         if (chan0_dualsided) {
2394                                 chan0 = EA_DUALCHANNEL_BANK_RANK_MODE;
2395                         } else {
2396                                 chan0 = EA_DUALCHANNEL_BANK_MODE;
2397                         }
2398
2399                         if (chan1_dualsided) {
2400                                 chan1 = EA_DUALCHANNEL_BANK_RANK_MODE;
2401                         } else {
2402                                 chan1 = EA_DUALCHANNEL_BANK_MODE;
2403                         }
2404                 }
2405         }
2406
2407         MCHBAR32(C0DRC1) &= 0x00ffffff;
2408         MCHBAR32(C0DRC1) |= chan0;
2409         MCHBAR32(C1DRC1) &= 0x00ffffff;
2410         MCHBAR32(C1DRC1) |= chan1;
2411 }
2412
2413 static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
2414 {
2415         u32 reg32;
2416
2417         /* Enable Channel XORing for Dual Channel Interleave */
2418         if (sysinfo->interleaved) {
2419
2420                 reg32 = MCHBAR32(DCC);
2421 #if CHANNEL_XOR_RANDOMIZATION
2422                 reg32 &= ~(1 << 10);
2423                 reg32 |= (1 << 9);
2424 #else
2425                 reg32 &= ~(1 << 9);
2426 #endif
2427                 MCHBAR32(DCC) = reg32;
2428         }
2429
2430         /* DRAM mode optimizations */
2431         sdram_enhanced_addressing_mode(sysinfo);
2432
2433         reg32 = MCHBAR32(FSBPMC3);
2434         reg32 &= ~(1 << 1);
2435         MCHBAR32(FSBPMC3) = reg32;
2436
2437         reg32 = MCHBAR32(SBTEST);
2438         reg32 &= ~(1 << 2);
2439         MCHBAR32(SBTEST) = reg32;
2440
2441         reg32 = MCHBAR32(SBOCC);
2442         reg32 &= 0xffbdb6ff;
2443         reg32 |= (0xbdb6 << 8) | (1 << 0);
2444         MCHBAR32(SBOCC) = reg32;
2445 }
2446
2447 static void sdram_power_management(struct sys_info *sysinfo)
2448 {
2449         u8 reg8;
2450         u16 reg16;
2451         u32 reg32;
2452         int integrated_graphics = 1;
2453         int i;
2454
2455         reg32 = MCHBAR32(C0DRT2);
2456         reg32 &= 0xffffff00;
2457         /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2458         reg32 |= (1 << 5) | (1 << 4);
2459         MCHBAR32(C0DRT2) = reg32;
2460
2461         reg32 = MCHBAR32(C1DRT2);
2462         reg32 &= 0xffffff00;
2463         /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */
2464         reg32 |= (1 << 5) | (1 << 4);
2465         MCHBAR32(C1DRT2) = reg32;
2466
2467         reg32 = MCHBAR32(C0DRC1);
2468
2469         reg32 |= (1 << 12) | (1 << 11);
2470         MCHBAR32(C0DRC1) = reg32;
2471
2472         reg32 = MCHBAR32(C1DRC1);
2473
2474         reg32 |= (1 << 12) | (1 << 11);
2475         MCHBAR32(C1DRC1) = reg32;
2476
2477         if (i945_silicon_revision()>1) {
2478                 /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
2479                 u16 peg_bits = (1 << 5) | (1 << 0);
2480
2481                 MCHBAR16(UPMC1) = 0x1010 | peg_bits;
2482         } else {
2483                 /* FIXME bits 5 and 0 only if PCIe graphics is disabled */
2484                 u16 peg_bits = (1 << 5) | (1 << 0);
2485
2486                 /* Rev 0 and 1 */
2487                 MCHBAR16(UPMC1) = 0x0010 | peg_bits;
2488         }
2489
2490         reg16 = MCHBAR16(UPMC2);
2491         reg16 &= 0xfc00;
2492         reg16 |= 0x0100;
2493         MCHBAR16(UPMC2) = reg16;
2494
2495         MCHBAR32(UPMC3) = 0x000f06ff;
2496
2497         for (i=0; i<5; i++) {
2498                 MCHBAR32(UPMC3) &= ~(1 << 16);
2499                 MCHBAR32(UPMC3) |= (1 << 16);
2500         }
2501
2502         MCHBAR32(GIPMC1) = 0x8000000c;
2503
2504         reg16 = MCHBAR16(CPCTL);
2505         reg16 &= ~(7 << 11);
2506         if (i945_silicon_revision()>2) {
2507                 reg16 |= (6 << 11);
2508         } else {
2509                 reg16 |= (4 << 11);
2510         }
2511         MCHBAR16(CPCTL) = reg16;
2512
2513 #if 0
2514         if ((MCHBAR32(ECO) & (1 << 16)) != 0) {
2515 #else
2516         if (i945_silicon_revision() != 0) {
2517 #endif
2518                 switch (sysinfo->fsb_frequency) {
2519                 case 667: MCHBAR32(HGIPMC2) = 0x0d590d59; break;
2520                 case 533: MCHBAR32(HGIPMC2) = 0x155b155b; break;
2521                 }
2522         } else {
2523                 switch (sysinfo->fsb_frequency) {
2524                 case 667: MCHBAR32(HGIPMC2) = 0x09c409c4; break;
2525                 case 533: MCHBAR32(HGIPMC2) = 0x0fa00fa0; break;
2526                 }
2527         }
2528
2529         MCHBAR32(FSBPMC1) = 0x8000000c;
2530
2531         reg32 = MCHBAR32(C2C3TT);
2532         reg32 &= 0xffff0000;
2533         switch (sysinfo->fsb_frequency) {
2534         case 667: reg32 |= 0x0600; break;
2535         case 533: reg32 |= 0x0480; break;
2536         }
2537         MCHBAR32(C2C3TT) = reg32;
2538
2539         reg32 = MCHBAR32(C3C4TT);
2540         reg32 &= 0xffff0000;
2541         switch (sysinfo->fsb_frequency) {
2542         case 667: reg32 |= 0x0b80; break;
2543         case 533: reg32 |= 0x0980; break;
2544         }
2545         MCHBAR32(C3C4TT) = reg32;
2546
2547         if (i945_silicon_revision() == 0) {
2548                 MCHBAR32(ECO) &= ~(1 << 16);
2549         } else {
2550                 MCHBAR32(ECO) |= (1 << 16);
2551         }
2552
2553 #if 0
2554
2555         if (i945_silicon_revision() == 0) {
2556                 MCHBAR32(FSBPMC3) &= ~(1 << 29);
2557         } else {
2558                 MCHBAR32(FSBPMC3) |= (1 << 29);
2559         }
2560 #endif
2561         MCHBAR32(FSBPMC3) &= ~(1 << 29);
2562
2563         MCHBAR32(FSBPMC3) |= (1 << 21);
2564
2565         MCHBAR32(FSBPMC3) &= ~(1 << 19);
2566
2567         MCHBAR32(FSBPMC3) &= ~(1 << 13);
2568
2569         reg32 = MCHBAR32(FSBPMC4);
2570         reg32 &= ~(3 << 24);
2571         reg32 |= ( 2 << 24);
2572         MCHBAR32(FSBPMC4) = reg32;
2573
2574         MCHBAR32(FSBPMC4) |= (1 << 21);
2575
2576         MCHBAR32(FSBPMC4) |= (1 << 5);
2577
2578         if ((i945_silicon_revision() < 2) /* || cpuid() = 0x6e8 */ ) {
2579                 /* stepping 0 and 1 or CPUID 6e8 */
2580                 MCHBAR32(FSBPMC4) &= ~(1 << 4);
2581         } else {
2582                 MCHBAR32(FSBPMC4) |= (1 << 4);
2583         }
2584
2585         reg8 = pci_read_config8(PCI_DEV(0,0x0,0), 0xfc);
2586         reg8 |= (1 << 4);
2587         pci_write_config8(PCI_DEV(0, 0x0, 0), 0xfc, reg8);
2588
2589         reg8 = pci_read_config8(PCI_DEV(0,0x2,0), 0xc1);
2590         reg8 |= (1 << 2);
2591         pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
2592
2593 #ifdef C2_SELF_REFRESH_DISABLE
2594
2595         if (integrated_graphics) {
2596                 printk(BIOS_DEBUG, "C2 self-refresh with IGD\n");
2597                 MCHBAR16(MIPMC4) = 0x0468;
2598                 MCHBAR16(MIPMC5) = 0x046c;
2599                 MCHBAR16(MIPMC6) = 0x046c;
2600         } else {
2601                 MCHBAR16(MIPMC4) = 0x6468;
2602                 MCHBAR16(MIPMC5) = 0x646c;
2603                 MCHBAR16(MIPMC6) = 0x646c;
2604         }
2605 #else
2606         if (integrated_graphics) {
2607                 MCHBAR16(MIPMC4) = 0x04f8;
2608                 MCHBAR16(MIPMC5) = 0x04fc;
2609                 MCHBAR16(MIPMC6) = 0x04fc;
2610         } else {
2611                 MCHBAR16(MIPMC4) = 0x64f8;
2612                 MCHBAR16(MIPMC5) = 0x64fc;
2613                 MCHBAR16(MIPMC6) = 0x64fc;
2614         }
2615
2616 #endif
2617
2618         reg32 = MCHBAR32(PMCFG);
2619         reg32 &= ~(3 << 17);
2620         reg32 |= (2 << 17);
2621         MCHBAR32(PMCFG) = reg32;
2622
2623         MCHBAR32(PMCFG) |= (1 << 4);
2624
2625         reg32 = MCHBAR32(0xc30);
2626         reg32 &= 0xffffff00;
2627         reg32 |= 0x01;
2628         MCHBAR32(0xc30) = reg32;
2629
2630         MCHBAR32(0xb18) &= ~(1 << 21);
2631 }
2632
2633 static void sdram_thermal_management(void)
2634 {
2635
2636         MCHBAR8(TCO1) = 0x00;
2637         MCHBAR8(TCO0) = 0x00;
2638
2639         /* The Thermal Sensors for DIMMs at 0x50, 0x52 are at I2C addr
2640          * 0x30/0x32.
2641          */
2642
2643         /* TODO This is not implemented yet. Volunteers? */
2644 }
2645
2646 static void sdram_save_receive_enable(void)
2647 {
2648         int i;
2649         u32 reg32;
2650         u8 values[4];
2651
2652         /* The following values are stored to an unused CMOS
2653          * area and restored instead of recalculated in case
2654          * of an S3 resume.
2655          *
2656          * C0WL0REOST [7:0]             -> 8 bit
2657          * C1WL0REOST [7:0]             -> 8 bit
2658          * RCVENMT    [11:8] [3:0]      -> 8 bit
2659          * C0DRT1     [27:24]           -> 4 bit
2660          * C1DRT1     [27:24]           -> 4 bit
2661          */
2662
2663         values[0] = MCHBAR8(C0WL0REOST);
2664         values[1] = MCHBAR8(C1WL0REOST);
2665
2666         reg32 = MCHBAR32(RCVENMT);
2667         values[2] = (u8)((reg32 >> (8 - 4)) & 0xf0) | (reg32 & 0x0f);
2668
2669         reg32 = MCHBAR32(C0DRT1);
2670         values[3] = (reg32 >> 24) & 0x0f;
2671         reg32 = MCHBAR32(C1DRT1);
2672         values[3] |= (reg32 >> (24 - 4)) & 0xf0;
2673
2674         /* coreboot only uses bytes 0 - 127 for its CMOS values so far
2675          * so we grab bytes 128 - 131 to save the receive enable values
2676          */
2677
2678         for (i=0; i<4; i++)
2679                 cmos_write(values[i], 128 + i);
2680 }
2681
2682 static void sdram_recover_receive_enable(void)
2683 {
2684         int i;
2685         u32 reg32;
2686         u8 values[4];
2687
2688         for (i=0; i<4; i++)
2689                 values[i] = cmos_read(128 + i);
2690
2691         MCHBAR8(C0WL0REOST) = values[0];
2692         MCHBAR8(C1WL0REOST) = values[1];
2693
2694         reg32 = MCHBAR32(RCVENMT);
2695         reg32 &= ~((0x0f << 8) | (0x0f << 0));
2696         reg32 |= ((u32)(values[2] & 0xf0) << (8 - 4)) | (values[2] & 0x0f);
2697         MCHBAR32(RCVENMT) = reg32;
2698
2699         reg32 = MCHBAR32(C0DRT1) & ~(0x0f << 24);
2700         reg32 |= (u32)(values[3] & 0x0f) << 24;
2701         MCHBAR32(C0DRT1) = reg32;
2702
2703         reg32 = MCHBAR32(C1DRT1) & ~(0x0f << 24);
2704         reg32 |= (u32)(values[3] & 0xf0) << (24 - 4);
2705         MCHBAR32(C1DRT1) = reg32;
2706 }
2707
2708 #include "rcven.c"
2709
2710 static void sdram_program_receive_enable(struct sys_info *sysinfo)
2711 {
2712         MCHBAR32(REPC) |= (1 << 0);
2713
2714         /* enable upper CMOS */
2715         RCBA32(0x3400) = (1 << 2);
2716
2717         /* Program Receive Enable Timings */
2718         if (sysinfo->boot_path == BOOT_PATH_RESUME) {
2719                 sdram_recover_receive_enable();
2720         } else {
2721                 receive_enable_adjust(sysinfo);
2722                 sdram_save_receive_enable();
2723         }
2724
2725         MCHBAR32(C0DRC1) |= (1 << 6);
2726         MCHBAR32(C1DRC1) |= (1 << 6);
2727         MCHBAR32(C0DRC1) &= ~(1 << 6);
2728         MCHBAR32(C1DRC1) &= ~(1 << 6);
2729
2730         MCHBAR32(MIPMC3) |= (0x0f << 0);
2731 }
2732
2733 /**
2734  * @brief Enable On-Die Termination for DDR2.
2735  *
2736  */
2737
2738 static void sdram_on_die_termination(struct sys_info *sysinfo)
2739 {
2740         static const u32 odt[] = {
2741                 0x00024911, 0xe0010000,
2742                 0x00049211, 0xe0020000,
2743                 0x0006db11, 0xe0030000,
2744         };
2745
2746         u32 reg32;
2747         int cas;
2748
2749         reg32 = MCHBAR32(ODTC);
2750         reg32 &= ~(3 << 16);
2751         reg32 |= (1 << 14) | (1 << 6) | (2 << 16);
2752         MCHBAR32(ODTC) = reg32;
2753
2754         if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
2755                         sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {
2756                 printk(BIOS_DEBUG, "one dimm per channel config.. \n");
2757
2758                 reg32 = MCHBAR32(C0ODT);
2759                 reg32 &= ~(7 << 28);
2760                 MCHBAR32(C0ODT) = reg32;
2761                 reg32 = MCHBAR32(C1ODT);
2762                 reg32 &= ~(7 << 28);
2763                 MCHBAR32(C1ODT) = reg32;
2764         }
2765
2766         cas = sysinfo->cas;
2767
2768         reg32 = MCHBAR32(C0ODT) & 0xfff00000;
2769         reg32 |= odt[(cas-3) * 2];
2770         MCHBAR32(C0ODT) = reg32;
2771
2772         reg32 = MCHBAR32(C1ODT) & 0xfff00000;
2773         reg32 |= odt[(cas-3) * 2];
2774         MCHBAR32(C1ODT) = reg32;
2775
2776         reg32 = MCHBAR32(C0ODT + 4) & 0x1fc8ffff;
2777         reg32 |= odt[((cas-3) * 2) + 1];
2778         MCHBAR32(C0ODT + 4) = reg32;
2779
2780         reg32 = MCHBAR32(C1ODT + 4) & 0x1fc8ffff;
2781         reg32 |= odt[((cas-3) * 2) + 1];
2782         MCHBAR32(C1ODT + 4) = reg32;
2783 }
2784
2785 /**
2786  * @brief Enable clocks to populated sockets
2787  */
2788
2789 static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
2790 {
2791         u8 clocks[2] = { 0, 0 };
2792
2793 #ifdef CHIPSET_I945GM
2794 #define CLOCKS_WIDTH 2
2795 #endif
2796 #ifdef CHIPSET_I945GC
2797 #define CLOCKS_WIDTH 3
2798 #endif
2799         if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
2800                 clocks[0] |= (1 << CLOCKS_WIDTH)-1;
2801
2802         if (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
2803                 clocks[0] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
2804
2805         if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED)
2806                 clocks[1] |= (1 << CLOCKS_WIDTH)-1;
2807
2808         if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
2809                 clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
2810
2811 #ifdef OVERRIDE_CLOCK_DISABLE
2812         /* Usually system firmware turns off system memory clock signals
2813          * to unused SO-DIMM slots to reduce EMI and power consumption.
2814          * However, the Kontron 986LCD-M does not like unused clock
2815          * signals to be disabled.
2816          * If other similar mainboard occur, it would make sense to make
2817          * this an entry in the sysinfo structure, and pre-initialize that
2818          * structure in the mainboard's romstage.c main() function.
2819          * For now an #ifdef will do.
2820          */
2821
2822         clocks[0] = 0xf; /* force all clock gate pairs to enable */
2823         clocks[1] = 0xf; /* force all clock gate pairs to enable */
2824 #endif
2825
2826         MCHBAR8(C0DCLKDIS) = clocks[0];
2827         MCHBAR8(C1DCLKDIS) = clocks[1];
2828 }
2829
2830 #define RTT_ODT_NONE    0
2831 #define RTT_ODT_50_OHM  ( (1 << 9) | (1 << 5) )
2832 #define RTT_ODT_75_OHM  (1 << 5)
2833 #define RTT_ODT_150_OHM (1 << 9)
2834
2835 #define EMRS_OCD_DEFAULT        ( (1 << 12) | (1 << 11) | (1 << 10) )
2836
2837 #define MRS_CAS_3       (3 << 7)
2838 #define MRS_CAS_4       (4 << 7)
2839 #define MRS_CAS_5       (5 << 7)
2840
2841 #define MRS_TWR_3       (2 << 12)
2842 #define MRS_TWR_4       (3 << 12)
2843 #define MRS_TWR_5       (4 << 12)
2844
2845 #define MRS_BT          (1 << 6)
2846
2847 #define MRS_BL4         (2 << 3)
2848 #define MRS_BL8         (3 << 3)
2849
2850 static void sdram_jedec_enable(struct sys_info *sysinfo)
2851 {
2852         int i, nonzero;
2853         u32 bankaddr = 0, tmpaddr, mrsaddr = 0;
2854
2855         for (i = 0, nonzero = -1; i < 8; i++) {
2856                 if (sysinfo->banksize[i]  == 0) {
2857                         continue;
2858                 }
2859
2860                 printk(BIOS_DEBUG, "jedec enable sequence: bank %d\n", i);
2861                 switch (i) {
2862                 case 0:
2863                         /* Start at address 0 */
2864                         bankaddr = 0;
2865                         break;
2866                 case 4:
2867                         if (sysinfo->interleaved) {
2868                                 bankaddr = 0x40;
2869                                 break;
2870                         }
2871                 default:
2872                         if (nonzero != -1) {
2873                                 printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", nonzero);
2874                                 bankaddr += sysinfo->banksize[nonzero] <<
2875                                         (sysinfo->interleaved ? 26 : 25);
2876                                 break;
2877                         }
2878                         /* No populated bank hit before. Start at address 0 */
2879                         bankaddr = 0;
2880                 }
2881
2882                 /* We have a bank with a non-zero size.. Remember it
2883                  * for the next offset we have to calculate
2884                  */
2885                 nonzero = i;
2886
2887                 /* Get CAS latency set up */
2888                 switch (sysinfo->cas) {
2889                 case 5: mrsaddr = MRS_CAS_5; break;
2890                 case 4: mrsaddr = MRS_CAS_4; break;
2891                 case 3: mrsaddr = MRS_CAS_3; break;
2892                 default: die("Jedec Error (CAS).\n");
2893                 }
2894
2895                 /* Get tWR set */
2896                 switch (sysinfo->twr) {
2897                 case 5: mrsaddr |= MRS_TWR_5; break;
2898                 case 4: mrsaddr |= MRS_TWR_4; break;
2899                 case 3: mrsaddr |= MRS_TWR_3; break;
2900                 default: die("Jedec Error (tWR).\n");
2901                 }
2902
2903                 /* Set "Burst Type" */
2904                 mrsaddr |= MRS_BT;
2905
2906                 /* Interleaved */
2907                 if (sysinfo->interleaved) {
2908                         mrsaddr = mrsaddr << 1;
2909                 }
2910
2911                 /* Only burst length 8 supported */
2912                 mrsaddr |= MRS_BL8;
2913
2914                 /* Apply NOP */
2915                 PRINTK_DEBUG("Apply NOP\n");
2916                 do_ram_command(RAM_COMMAND_NOP);
2917                 ram_read32(bankaddr);
2918
2919                 /* Precharge all banks */
2920                 PRINTK_DEBUG("All Banks Precharge\n");
2921                 do_ram_command(RAM_COMMAND_PRECHARGE);
2922                 ram_read32(bankaddr);
2923
2924                 /* Extended Mode Register Set (2) */
2925                 PRINTK_DEBUG("Extended Mode Register Set(2)\n");
2926                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_2);
2927                 ram_read32(bankaddr);
2928
2929                 /* Extended Mode Register Set (3) */
2930                 PRINTK_DEBUG("Extended Mode Register Set(3)\n");
2931                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_3);
2932                 ram_read32(bankaddr);
2933
2934                 /* Extended Mode Register Set */
2935                 PRINTK_DEBUG("Extended Mode Register Set\n");
2936                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2937                 tmpaddr = bankaddr;
2938                 if (!sdram_capabilities_dual_channel()) {
2939                         tmpaddr |= RTT_ODT_75_OHM;
2940                 } else if (sysinfo->interleaved) {
2941                         tmpaddr |= (RTT_ODT_150_OHM << 1);
2942                 } else {
2943                         tmpaddr |= RTT_ODT_150_OHM;
2944                 }
2945                 ram_read32(tmpaddr);
2946
2947                 /* Mode Register Set: Reset DLLs */
2948                 PRINTK_DEBUG("MRS: Reset DLLs\n");
2949                 do_ram_command(RAM_COMMAND_MRS);
2950                 tmpaddr = bankaddr;
2951                 tmpaddr |= mrsaddr;
2952                 /* Set DLL reset bit */
2953                 if (sysinfo->interleaved)
2954                         tmpaddr |= (1 << 12);
2955                 else
2956                         tmpaddr |= (1 << 11);
2957                 ram_read32(tmpaddr);
2958
2959                 /* Precharge all banks */
2960                 PRINTK_DEBUG("All Banks Precharge\n");
2961                 do_ram_command(RAM_COMMAND_PRECHARGE);
2962                 ram_read32(bankaddr);
2963
2964                 /* CAS before RAS Refresh */
2965                 PRINTK_DEBUG("CAS before RAS\n");
2966                 do_ram_command(RAM_COMMAND_CBR);
2967
2968                 /* CBR wants two READs */
2969                 ram_read32(bankaddr);
2970                 ram_read32(bankaddr);
2971
2972                 /* Mode Register Set: Enable DLLs */
2973                 PRINTK_DEBUG("MRS: Enable DLLs\n");
2974                 do_ram_command(RAM_COMMAND_MRS);
2975
2976                 tmpaddr = bankaddr;
2977                 tmpaddr |= mrsaddr;
2978                 ram_read32(tmpaddr);
2979
2980                 /* Extended Mode Register Set */
2981                 PRINTK_DEBUG("Extended Mode Register Set: ODT/OCD\n");
2982                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2983
2984                 tmpaddr = bankaddr;
2985                 if (!sdram_capabilities_dual_channel()) {
2986
2987                         tmpaddr |= RTT_ODT_75_OHM | EMRS_OCD_DEFAULT;
2988                 } else if (sysinfo->interleaved) {
2989                         tmpaddr |= ((RTT_ODT_150_OHM | EMRS_OCD_DEFAULT) << 1);
2990                 } else {
2991                         tmpaddr |= RTT_ODT_150_OHM | EMRS_OCD_DEFAULT;
2992                 }
2993                 ram_read32(tmpaddr);
2994
2995                 /* Extended Mode Register Set */
2996                 PRINTK_DEBUG("Extended Mode Register Set: OCD Exit\n");
2997                 do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1);
2998
2999                 tmpaddr = bankaddr;
3000                 if (!sdram_capabilities_dual_channel()) {
3001                         tmpaddr |= RTT_ODT_75_OHM;
3002                 } else if (sysinfo->interleaved) {
3003                         tmpaddr |= (RTT_ODT_150_OHM << 1);
3004                 } else {
3005                         tmpaddr |= RTT_ODT_150_OHM;
3006                 }
3007                 ram_read32(tmpaddr);
3008         }
3009 }
3010
3011 static void sdram_init_complete(void)
3012 {
3013         PRINTK_DEBUG("Normal Operation\n");
3014         do_ram_command(RAM_COMMAND_NORMAL);
3015 }
3016
3017 static void sdram_setup_processor_side(void)
3018 {
3019         if (i945_silicon_revision() == 0)
3020                 MCHBAR32(FSBPMC3) |= (1 << 2);
3021
3022         MCHBAR8(0xb00) |= 1;
3023
3024         if (i945_silicon_revision() == 0)
3025                 MCHBAR32(SLPCTL) |= (1 << 8);
3026 }
3027
3028 /**
3029  * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3
3030  */
3031 void sdram_initialize(int boot_path)
3032 {
3033         struct sys_info sysinfo;
3034         u8 reg8, cas_mask;
3035
3036         printk(BIOS_DEBUG, "Setting up RAM controller.\n");
3037
3038         memset(&sysinfo, 0, sizeof(sysinfo));
3039
3040         sysinfo.boot_path = boot_path;
3041
3042         /* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */
3043         sdram_get_dram_configuration(&sysinfo);
3044
3045         /* If error, do cold boot */
3046         sdram_detect_errors(&sysinfo);
3047
3048         /* Check whether we have stacked DIMMs */
3049         sdram_verify_package_type(&sysinfo);
3050
3051         /* Determine common CAS */
3052         cas_mask = sdram_possible_cas_latencies(&sysinfo);
3053
3054         /* Choose Common Frequency */
3055         sdram_detect_cas_latency_and_ram_speed(&sysinfo, cas_mask);
3056
3057         /* Determine smallest common tRAS */
3058         sdram_detect_smallest_tRAS(&sysinfo);
3059
3060         /* Determine tRP */
3061         sdram_detect_smallest_tRP(&sysinfo);
3062
3063         /* Determine tRCD */
3064         sdram_detect_smallest_tRCD(&sysinfo);
3065
3066         /* Determine smallest refresh period */
3067         sdram_detect_smallest_refresh(&sysinfo);
3068
3069         /* Verify all DIMMs support burst length 8 */
3070         sdram_verify_burst_length(&sysinfo);
3071
3072         /* determine tWR */
3073         sdram_detect_smallest_tWR(&sysinfo);
3074
3075         /* Determine DIMM size parameters (rows, columns banks) */
3076         sdram_detect_dimm_size(&sysinfo);
3077
3078         /* determine tRFC */
3079         sdram_detect_smallest_tRFC(&sysinfo);
3080
3081         /* Program PLL settings */
3082         sdram_program_pll_settings(&sysinfo);
3083
3084         /* Program Graphics Frequency */
3085         sdram_program_graphics_frequency(&sysinfo);
3086
3087         /* Program System Memory Frequency */
3088         sdram_program_memory_frequency(&sysinfo);
3089
3090         /* Determine Mode of Operation (Interleaved etc) */
3091         sdram_set_channel_mode(&sysinfo);
3092
3093         /* Program Clock Crossing values */
3094         sdram_program_clock_crossing();
3095
3096         /* Disable fast dispatch */
3097         sdram_disable_fast_dispatch();
3098
3099         /* Enable WIODLL Power Down in ACPI states */
3100         MCHBAR32(C0DMC) |= (1 << 24);
3101         MCHBAR32(C1DMC) |= (1 << 24);
3102
3103         /* Program DRAM Row Boundary/Attribute Registers */
3104
3105         /* program row size DRB and set TOLUD */
3106         sdram_program_row_boundaries(&sysinfo);
3107
3108         /* program page size DRA */
3109         sdram_set_row_attributes(&sysinfo);
3110
3111         /* Program CxBNKARC */
3112         sdram_set_bank_architecture(&sysinfo);
3113
3114         /* Program DRAM Timing and Control registers based on SPD */
3115         sdram_set_timing_and_control(&sysinfo);
3116
3117         /* On-Die Termination Adjustment */
3118         sdram_on_die_termination(&sysinfo);
3119
3120         /* Pre Jedec Initialization */
3121         sdram_pre_jedec_initialization();
3122
3123         /* Perform System Memory IO Initialization */
3124         sdram_initialize_system_memory_io(&sysinfo);
3125
3126         /* Perform System Memory IO Buffer Enable */
3127         sdram_enable_system_memory_io(&sysinfo);
3128
3129         /* Enable System Memory Clocks */
3130         sdram_enable_memory_clocks(&sysinfo);
3131
3132         if (boot_path == BOOT_PATH_NORMAL) {
3133                 /* Jedec Initialization sequence */
3134                 sdram_jedec_enable(&sysinfo);
3135         }
3136
3137         /* Program Power Management Registers */
3138         sdram_power_management(&sysinfo);
3139
3140         /* Post Jedec Init */
3141         sdram_post_jedec_initialization(&sysinfo);
3142
3143         /* Program DRAM Throttling */
3144         sdram_thermal_management();
3145
3146         /* Normal Operations */
3147         sdram_init_complete();
3148
3149         /* Program Receive Enable Timings */
3150         sdram_program_receive_enable(&sysinfo);
3151
3152         /* Enable Periodic RCOMP */
3153         sdram_enable_rcomp();
3154
3155         /* Tell ICH7 that we're done */
3156         reg8 = pci_read_config8(PCI_DEV(0,0x1f,0), 0xa2);
3157         reg8 &= ~(1 << 7);
3158         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
3159
3160         printk(BIOS_DEBUG, "RAM initialization finished.\n");
3161
3162         sdram_setup_processor_side();
3163 }
3164
3165 unsigned long get_top_of_ram(void)
3166 {
3167         /* This will not work if TSEG is in place! */
3168         u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
3169
3170         return (unsigned long) tom;
3171 }
3172