2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
24 #include <device/device.h>
25 #include <device/pci.h>
26 #include <device/pci_ids.h>
32 #include "northbridge.h"
35 static void northbridge_init(device_t dev)
37 printk_spew("Northbridge init\n");
40 static struct device_operations northbridge_operations = {
41 .read_resources = pci_dev_read_resources,
42 .set_resources = pci_dev_set_resources,
43 .enable_resources = pci_dev_enable_resources,
44 .init = northbridge_init,
49 static const struct pci_driver northbridge_driver __pci_driver = {
50 .ops = &northbridge_operations,
51 .vendor = PCI_VENDOR_ID_INTEL,
55 static void ram_resource(device_t dev, unsigned long index,
56 unsigned long basek, unsigned long sizek)
58 struct resource *resource;
63 resource = new_resource(dev, index);
64 resource->base = ((resource_t) basek) << 10;
65 resource->size = ((resource_t) sizek) << 10;
66 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
67 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
70 static void tolm_test(void *gp, struct device *dev, struct resource *new)
72 struct resource **best_p = gp;
73 struct resource *best;
75 if (!best || (best->base > new->base)) {
81 static uint32_t find_pci_tolm(struct bus *bus)
86 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test,
89 if (min && tolm > min->base) {
95 /* Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value.
96 * Note that 2 is a value which the DRP should never be programmed to.
97 * Some size values appear twice, due to single-sided vs dual-sided banks.
99 static int translate_i82810_to_mb[] = {
100 /* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */
101 /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256,
104 #if CONFIG_HAVE_HIGH_TABLES==1
105 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
106 extern uint64_t high_tables_base, high_tables_size;
109 static void pci_domain_set_resources(device_t dev)
114 pci_tolm = find_pci_tolm(&dev->link[0]);
115 mc_dev = dev->link[0].children;
118 /* Figure out which areas are/should be occupied by RAM.
119 * This is all computed in kilobytes and converted to/from
120 * the memory controller right at the edges.
121 * Having different variables in different units is
122 * too confusing to get right. Kilobytes are good up to
123 * 4 Terabytes of RAM...
125 unsigned long tomk, tolmk;
129 /* First get the value for DIMM 0. */
130 drp_value = pci_read_config8(mc_dev, DRP);
131 /* Translate it to MB and add to tomk. */
132 tomk = (unsigned long)(translate_i82810_to_mb[drp_value & 0xf]);
133 /* Now do the same for DIMM 1. */
134 drp_value = drp_value >> 4; // >>= 4; //? mess with later
135 tomk += (unsigned long)(translate_i82810_to_mb[drp_value]);
137 printk_debug("Setting RAM size to %d MB\n", tomk);
139 /* Convert tomk from MB to KB. */
142 /* Compute the top of Low memory. */
143 tolmk = pci_tolm >> 10;
145 /* The PCI hole does does not overlap the memory. */
149 /* Report the memory regions. */
151 ram_resource(dev, idx++, 0, 640);
152 ram_resource(dev, idx++, 768, tolmk - 768);
154 #if CONFIG_HAVE_HIGH_TABLES==1
155 /* Leave some space for ACPI, PIRQ and MP tables */
156 high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
157 high_tables_size = HIGH_TABLES_SIZE * 1024;
160 assign_resources(&dev->link[0]);
163 static struct device_operations pci_domain_ops = {
164 .read_resources = pci_domain_read_resources,
165 .set_resources = pci_domain_set_resources,
166 .enable_resources = enable_childrens_resources,
168 .scan_bus = pci_domain_scan_bus,
171 static void cpu_bus_init(device_t dev)
173 initialize_cpus(&dev->link[0]);
176 static void cpu_bus_noop(device_t dev)
180 static struct device_operations cpu_bus_ops = {
181 .read_resources = cpu_bus_noop,
182 .set_resources = cpu_bus_noop,
183 .enable_resources = cpu_bus_noop,
184 .init = cpu_bus_init,
188 static void enable_dev(struct device *dev)
190 struct device_path path;
192 /* Set the operations if it is a special bus type */
193 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
194 dev->ops = &pci_domain_ops;
196 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
197 dev->ops = &cpu_bus_ops;
201 struct chip_operations northbridge_intel_i82810_ops = {
202 CHIP_NAME("Intel 82810 Northbridge")
203 .enable_dev = enable_dev,