2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Arastra, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 /* This code is based on src/northbridge/intel/e7520/northbridge.c */
23 #include <console/console.h>
26 #include <device/device.h>
27 #include <device/pci.h>
28 #include <device/pci_ids.h>
29 #include <device/hypertransport.h>
40 static void ram_resource(device_t dev, u32 index,
43 struct resource *resource;
45 resource = new_resource(dev, index);
46 resource->base = ((resource_t)basek) << 10;
47 resource->size = ((resource_t)sizek) << 10;
48 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
49 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
53 static void pci_domain_read_resources(device_t dev)
55 struct resource *resource;
57 /* Initialize the system wide io space constraints */
58 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
63 resource->limit = 0xffffUL;
64 resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
66 /* Initialize the system wide memory resources constraints */
67 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
72 resource->limit = 0xffffffffUL;
73 resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
76 static void tolm_test(void *gp, struct device *dev, struct resource *new)
78 struct resource **best_p = gp;
79 struct resource *best;
81 if (!best || (best->base > new->base)) {
87 static u32 find_pci_tolm(struct bus *bus)
92 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
94 if (min && tolm > min->base) {
101 static void pci_domain_set_resources(device_t dev)
106 pci_tolm = find_pci_tolm(&dev->link[0]);
109 printk_debug("PCI mem marker = %x\n", pci_tolm);
111 /* FIXME Me temporary hack */
112 if(pci_tolm > 0xe0000000)
113 pci_tolm = 0xe0000000;
114 /* Ensure pci_tolm is 128M aligned */
115 pci_tolm &= 0xf8000000;
116 mc_dev = dev->link[0].children;
118 /* Figure out which areas are/should be occupied by RAM.
119 * This is all computed in kilobytes and converted to/from
120 * the memory controller right at the edges.
121 * Having different variables in different units is
122 * too confusing to get right. Kilobytes are good up to
123 * 4 Terabytes of RAM...
125 u16 tolm_r, remapbase_r, remaplimit_r, remapoffset_r;
127 u32 remapbasek, remaplimitk, remapoffsetk;
129 /* Get the Top of Memory address, units are 128M */
130 tomk = ((u32)pci_read_config16(mc_dev, TOM)) << 17;
131 /* Compute the Top of Low Memory */
132 tolmk = (pci_tolm & 0xf8000000) >> 10;
135 /* The PCI hole does not overlap memory
136 * we won't use the remap window.
139 remapbasek = 0x3ff << 16;
140 remaplimitk = 0 << 16;
141 remapoffsetk = 0 << 16;
144 /* The PCI memory hole overlaps memory
145 * setup the remap window.
147 /* Find the bottom of the remap window
150 remapbasek = 4*1024*1024;
151 if (tomk > remapbasek) {
154 /* Find the limit of the remap window */
155 remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
156 /* Find the offset of the remap window from tolm */
157 remapoffsetk = remapbasek - tolmk;
159 /* Write the ram configruation registers,
160 * preserving the reserved bits.
162 tolm_r = pci_read_config16(mc_dev, 0xc4);
163 tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
164 pci_write_config16(mc_dev, 0xc4, tolm_r);
166 remapbase_r = pci_read_config16(mc_dev, 0xc6);
167 remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
168 pci_write_config16(mc_dev, 0xc6, remapbase_r);
170 remaplimit_r = pci_read_config16(mc_dev, 0xc8);
171 remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
172 pci_write_config16(mc_dev, 0xc8, remaplimit_r);
174 remapoffset_r = pci_read_config16(mc_dev, 0xca);
175 remapoffset_r = (remapoffsetk >> 16) | (remapoffset_r & 0xfc00);
176 pci_write_config16(mc_dev, 0xca, remapoffset_r);
178 /* Report the memory regions */
179 ram_resource(dev, 3, 0, 640);
180 ram_resource(dev, 4, 768, (tolmk - 768));
181 if (tomk > 4*1024*1024) {
182 ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
184 if (remaplimitk >= remapbasek) {
185 ram_resource(dev, 6, remapbasek,
186 (remaplimitk + 64*1024) - remapbasek);
189 assign_resources(&dev->link[0]);
192 static u32 pci_domain_scan_bus(device_t dev, u32 max)
194 max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
201 static struct device_operations pci_domain_ops = {
202 .read_resources = pci_domain_read_resources,
203 .set_resources = pci_domain_set_resources,
204 .enable_resources = enable_childrens_resources,
206 .scan_bus = pci_domain_scan_bus,
207 .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
210 static void mc_read_resources(device_t dev)
212 struct resource *resource;
214 pci_dev_read_resources(dev);
216 resource = new_resource(dev, 0xcf);
217 resource->base = 0xe0000000;
218 resource->size = max_bus * 4096*256;
219 resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
222 static void mc_set_resources(device_t dev)
224 struct resource *resource, *last;
226 last = &dev->resource[dev->resources];
227 resource = find_resource(dev, 0xcf);
229 report_resource_stored(dev, resource, "<mmconfig>");
231 pci_dev_set_resources(dev);
234 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
236 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
237 ((device & 0xffff) << 16) | (vendor & 0xffff));
240 static struct pci_operations intel_pci_ops = {
241 .set_subsystem = intel_set_subsystem,
244 static struct device_operations mc_ops = {
245 .read_resources = mc_read_resources,
246 .set_resources = mc_set_resources,
247 .enable_resources = pci_dev_enable_resources,
250 .ops_pci = &intel_pci_ops,
253 static struct pci_driver mc_driver __pci_driver = {
255 .vendor = PCI_VENDOR_ID_INTEL,
256 .device = PCI_DEVICE_ID_INTEL_3100_MC,
259 static void cpu_bus_init(device_t dev)
261 initialize_cpus(&dev->link[0]);
264 static void cpu_bus_noop(device_t dev)
268 static struct device_operations cpu_bus_ops = {
269 .read_resources = cpu_bus_noop,
270 .set_resources = cpu_bus_noop,
271 .enable_resources = cpu_bus_noop,
272 .init = cpu_bus_init,
277 static void enable_dev(device_t dev)
279 /* Set the operations if it is a special bus type */
280 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
281 dev->ops = &pci_domain_ops;
283 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
284 dev->ops = &cpu_bus_ops;
288 struct chip_operations northbridge_intel_i3100_ops = {
289 CHIP_NAME("Intel 3100 Northbridge")
290 .enable_dev = enable_dev,