src/northbridge/intel/e7520/northbridge.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <device/hypertransport.h>
   8 #include <stdlib.h>
   9 #include <string.h>
  10 #include <bitops.h>
  11 #include <cpu/cpu.h>
  12 #include "chip.h"
  13 #include "northbridge.h"
  14 #include "e7520.h"
  15
  16
  17 static unsigned int max_bus;
  18
  19 static void ram_resource(device_t dev, unsigned long index,
  20         unsigned long basek, unsigned long sizek)
  21 {
  22         struct resource *resource;
  23
  24         resource = new_resource(dev, index);
  25         resource->base  = ((resource_t)basek) << 10;
  26         resource->size  = ((resource_t)sizek) << 10;
  27         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  28                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
  29 }
  30
  31
  32 static void pci_domain_read_resources(device_t dev)
  33 {
  34         struct resource *resource;
  35
  36         /* Initialize the system wide io space constraints */
  37         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
  38         resource->base  = 0;
  39         resource->size  = 0;
  40         resource->align = 0;
  41         resource->gran  = 0;
  42         resource->limit = 0xffffUL;
  43         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  44
  45         /* Initialize the system wide memory resources constraints */
  46         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
  47         resource->base  = 0;
  48         resource->size  = 0;
  49         resource->align = 0;
  50         resource->gran  = 0;
  51         resource->limit = 0xffffffffUL;
  52         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  53 }
  54
  55 static void tolm_test(void *gp, struct device *dev, struct resource *new)
  56 {
  57         struct resource **best_p = gp;
  58         struct resource *best;
  59         best = *best_p;
  60         if (!best || (best->base > new->base)) {
  61                 best = new;
  62         }
  63         *best_p = best;
  64 }
  65
  66 static uint32_t find_pci_tolm(struct bus *bus)
  67 {
  68         struct resource *min;
  69         uint32_t tolm;
  70         min = 0;
  71         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
  72         tolm = 0xffffffffUL;
  73         if (min && tolm > min->base) {
  74                 tolm = min->base;
  75         }
  76         return tolm;
  77 }
  78
  79 #if CONFIG_HAVE_HIGH_TABLES==1
  80 #define HIGH_TABLES_SIZE 64     // maximum size of high tables in KB
  81 extern uint64_t high_tables_base, high_tables_size;
  82 #endif
  83
  84 static void pci_domain_set_resources(device_t dev)
  85 {
  86         device_t mc_dev;
  87         uint32_t pci_tolm;
  88
  89         pci_tolm = find_pci_tolm(&dev->link[0]);
  90
  91 #if 1
  92         printk_debug("PCI mem marker = %x\n", pci_tolm);
  93 #endif
  94         /* FIXME Me temporary hack */
  95         if(pci_tolm > 0xe0000000)
  96                 pci_tolm = 0xe0000000;
  97         /* Ensure pci_tolm is 128M aligned */
  98         pci_tolm &= 0xf8000000;
  99         mc_dev = dev->link[0].children;
 100         if (mc_dev) {
 101                 /* Figure out which areas are/should be occupied by RAM.
 102                  * This is all computed in kilobytes and converted to/from
 103                  * the memory controller right at the edges.
 104                  * Having different variables in different units is
 105                  * too confusing to get right.  Kilobytes are good up to
 106                  * 4 Terabytes of RAM...
 107                  */
 108                 uint16_t tolm_r, remapbase_r, remaplimit_r, remapoffset_r;
 109                 unsigned long tomk, tolmk;
 110                 unsigned long remapbasek, remaplimitk, remapoffsetk;
 111
 112                 /* Get the Top of Memory address, units are 128M */
 113                 tomk = ((unsigned long)pci_read_config16(mc_dev, TOM)) << 17;
 114                 /* Compute the Top of Low Memory */
 115                 tolmk = (pci_tolm  & 0xf8000000) >> 10;
 116
 117                 if (tolmk >= tomk) {
 118                         /* The PCI hole does not overlap memory
 119                          * we won't use the remap window.
 120                          */
 121                         tolmk = tomk;
 122                         remapbasek   = 0x3ff << 16;
 123                         remaplimitk  = 0 << 16;
 124                         remapoffsetk = 0 << 16;
 125                 }
 126                 else {
 127                         /* The PCI memory hole overlaps memory
 128                          * setup the remap window.
 129                          */
 130                         /* Find the bottom of the remap window
 131                          * is it above 4G?
 132                          */
 133                         remapbasek = 4*1024*1024;
 134                         if (tomk > remapbasek) {
 135                                 remapbasek = tomk;
 136                         }
 137                         /* Find the limit of the remap window */
 138                         remaplimitk  = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
 139                         /* Find the offset of the remap window from tolm */
 140                         remapoffsetk = remapbasek - tolmk;
 141                 }
 142                 /* Write the ram configruation registers,
 143                  * preserving the reserved bits.
 144                  */
 145                 tolm_r = pci_read_config16(mc_dev, 0xc4);
 146                 tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
 147                 pci_write_config16(mc_dev, 0xc4, tolm_r);
 148
 149                 remapbase_r = pci_read_config16(mc_dev, 0xc6);
 150                 remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
 151                 pci_write_config16(mc_dev, 0xc6, remapbase_r);
 152
 153                 remaplimit_r = pci_read_config16(mc_dev, 0xc8);
 154                 remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
 155                 pci_write_config16(mc_dev, 0xc8, remaplimit_r);
 156
 157                 remapoffset_r = pci_read_config16(mc_dev, 0xca);
 158                 remapoffset_r = (remapoffsetk >> 16) | (remapoffset_r & 0xfc00);
 159                 pci_write_config16(mc_dev, 0xca, remapoffset_r);
 160
 161                 /* Report the memory regions */
 162                 ram_resource(dev, 3,   0, 640);
 163                 ram_resource(dev, 4, 768, (tolmk - 768));
 164                 if (tomk > 4*1024*1024) {
 165                         ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
 166                 }
 167                 if (remaplimitk >= remapbasek) {
 168                         ram_resource(dev, 6, remapbasek,
 169                                 (remaplimitk + 64*1024) - remapbasek);
 170                 }
 171
 172 #if CONFIG_HAVE_HIGH_TABLES==1
 173                 /* Leave some space for ACPI, PIRQ and MP tables */
 174                 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
 175                 high_tables_size = HIGH_TABLES_SIZE * 1024;
 176 #endif
 177         }
 178         assign_resources(&dev->link[0]);
 179 }
 180
 181 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 182 {
 183         max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
 184         if (max > max_bus) {
 185                 max_bus = max;
 186         }
 187         return max;
 188 }
 189
 190 static struct device_operations pci_domain_ops = {
 191         .read_resources   = pci_domain_read_resources,
 192         .set_resources    = pci_domain_set_resources,
 193         .enable_resources = enable_childrens_resources,
 194         .init             = 0,
 195         .scan_bus         = pci_domain_scan_bus,
 196         .ops_pci_bus      = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
 197 };
 198
 199 static void mc_read_resources(device_t dev)
 200 {
 201         struct resource *resource;
 202
 203         pci_dev_read_resources(dev);
 204
 205         resource = new_resource(dev, 0xcf);
 206         resource->base = 0xe0000000;
 207         resource->size = max_bus * 4096*256;
 208         resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |  IORESOURCE_ASSIGNED;
 209 }
 210
 211 static void mc_set_resources(device_t dev)
 212 {
 213         struct resource *resource, *last;
 214
 215         last = &dev->resource[dev->resources];
 216         resource = find_resource(dev, 0xcf);
 217         if (resource) {
 218                 report_resource_stored(dev, resource, "<mmconfig>");
 219         }
 220         pci_dev_set_resources(dev);
 221 }
 222
 223 static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 224 {
 225         pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 226                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 227 }
 228
 229 static struct pci_operations intel_pci_ops = {
 230         .set_subsystem = intel_set_subsystem,
 231 };
 232
 233 static struct device_operations mc_ops = {
 234         .read_resources   = mc_read_resources,
 235         .set_resources    = mc_set_resources,
 236         .enable_resources = pci_dev_enable_resources,
 237         .init             = 0,
 238         .scan_bus         = 0,
 239         .ops_pci          = &intel_pci_ops,
 240 };
 241
 242 static const struct pci_driver mc_driver __pci_driver = {
 243         .ops = &mc_ops,
 244         .vendor = PCI_VENDOR_ID_INTEL,
 245         .device = 0x3590,
 246 };
 247
 248 static void cpu_bus_init(device_t dev)
 249 {
 250         initialize_cpus(&dev->link[0]);
 251 }
 252
 253 static void cpu_bus_noop(device_t dev)
 254 {
 255 }
 256
 257 static struct device_operations cpu_bus_ops = {
 258         .read_resources   = cpu_bus_noop,
 259         .set_resources    = cpu_bus_noop,
 260         .enable_resources = cpu_bus_noop,
 261         .init             = cpu_bus_init,
 262         .scan_bus         = 0,
 263 };
 264
 265
 266 static void enable_dev(device_t dev)
 267 {
 268         /* Set the operations if it is a special bus type */
 269         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 270                 dev->ops = &pci_domain_ops;
 271         }
 272         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 273                 dev->ops = &cpu_bus_ops;
 274         }
 275 }
 276
 277 struct chip_operations northbridge_intel_e7520_ops = {
 278         CHIP_NAME("Intel E7520 Northbridge")
 279         .enable_dev = enable_dev,
 280 };