src/northbridge/intel/e7501/raminit.c

   1 /* This was originally for the e7500, modified for e7501
   2  * The primary differences are that 7501 apparently can
   3  * support single channel RAM (i haven't tested),
   4  * CAS1.5 is no longer supported, The ECC scrubber
   5  * now supports a mode to zero RAM and init ECC in one step
   6  * and the undocumented registers at 0x80 require new
   7  * (undocumented) values determined by guesswork and
   8  * comparison w/ OEM BIOS values.
   9  * Steven James 02/06/2003
  10  */
  11
  12 /* converted to C 6/2004 yhlu */
  13
  14 #include <assert.h>
  15 #include <spd.h>
  16 #include <sdram_mode.h>
  17 #include <stdlib.h>
  18 #include "e7501.h"
  19
  20 // Uncomment this to enable run-time checking of DIMM parameters
  21 // for dual-channel operation
  22 // Unfortunately the code seems to chew up several K of space.
  23 //#define VALIDATE_DIMM_COMPATIBILITY
  24
  25 #if CONFIG_DEBUG_RAM_SETUP
  26 #define RAM_DEBUG_MESSAGE(x)    print_debug(x)
  27 #define RAM_DEBUG_HEX32(x)              print_debug_hex32(x)
  28 #define RAM_DEBUG_HEX8(x)               print_debug_hex8(x)
  29 #define DUMPNORTH()                             dump_pci_device(PCI_DEV(0, 0, 0))
  30 #else
  31 #define RAM_DEBUG_MESSAGE(x)
  32 #define RAM_DEBUG_HEX32(x)
  33 #define RAM_DEBUG_HEX8(x)
  34 #define DUMPNORTH()
  35 #endif
  36
  37 #define E7501_SDRAM_MODE        (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4)
  38 #define SPD_ERROR                       "Error reading SPD info\n"
  39
  40 // NOTE: This used to be 0x100000.
  41 //               That doesn't work on systems where A20M# is asserted, because
  42 //               attempts to access 0x1000NN end up accessing 0x0000NN.
  43 #define RCOMP_MMIO 0x200000
  44
  45 struct dimm_size {
  46         unsigned long side1;
  47         unsigned long side2;
  48 };
  49
  50 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
  51 /*                                                                      DEFINITIONS                                                                       */
  52 /**********************************************************************************/
  53
  54 static const uint32_t refresh_frequency[]= {
  55         /* Relative frequency (array value) of each E7501 Refresh Mode Select
  56          * (RMS) value (array index)
  57          * 0 == least frequent refresh (longest interval between refreshes)
  58          * [0] disabled  -> 0
  59          * [1] 15.6 usec -> 2
  60          * [2]  7.8 usec -> 3
  61          * [3] 64   usec -> 1
  62          * [4] reserved  -> 0
  63          * [5] reserved  -> 0
  64          * [6] reserved  -> 0
  65          * [7] 64 clocks -> 4
  66          */
  67         0, 2, 3, 1, 0, 0, 0, 4 };
  68
  69 static const uint32_t refresh_rate_map[] = {
  70         /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode
  71          * Select values (array value)
  72          * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0
  73          * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and
  74          * 64 clock (481 ns) (7) refresh.
  75          * [0] ==  15.625 us -> 15.6 us
  76          * [1] ==   3.9   us -> 481  ns
  77          * [2] ==   7.8   us ->  7.8 us
  78          * [3] ==  31.3   us -> 15.6 us
  79          * [4] ==  62.5   us -> 15.6 us
  80          * [5] == 125     us -> 64   us
  81          */
  82         1, 7, 2, 1, 1, 3
  83 };
  84 #define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1)
  85
  86
  87 // SPD parameters that must match for dual-channel operation
  88 static const uint8_t dual_channel_parameters[] = {
  89         SPD_MEMORY_TYPE,
  90         SPD_MODULE_VOLTAGE,
  91         SPD_NUM_COLUMNS,
  92         SPD_NUM_ROWS,
  93         SPD_NUM_DIMM_BANKS,
  94         SPD_PRIMARY_SDRAM_WIDTH,
  95         SPD_NUM_BANKS_PER_SDRAM
  96 };
  97
  98         /*
  99          * Table:       constant_register_values
 100          */
 101 static const long constant_register_values[] = {
 102         /* SVID - Subsystem Vendor Identification Register
 103          * 0x2c - 0x2d
 104          * [15:00] Subsytem Vendor ID (Indicates system board vendor)
 105          */
 106         /* SID - Subsystem Identification Register
 107          * 0x2e - 0x2f
 108          * [15:00] Subsystem ID
 109          */
 110          // Not everyone wants to be Super Micro Computer, Inc.
 111          // The mainboard should set this if desired.
 112          // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16),
 113
 114         /* Undocumented
 115          * (DRAM Read Timing Control, if similar to 855PM?)
 116          * 0x80 - 0x81
 117          * This register has something to do with CAS latencies,
 118          * possibily this is the real chipset control.
 119          * At 0x00 CAS latency 1.5 works.
 120          * At 0x06 CAS latency 2.5 works.
 121          * At 0x01 CAS latency 2.0 works.
 122          */
 123         /* This is still undocumented in e7501, but with different values
 124          * CAS 2.0 values taken from Intel BIOS settings, others are a guess
 125          * and may be terribly wrong. Old values preserved as comments until I
 126          * figure this out for sure.
 127          * e7501 docs claim that CAS1.5 is unsupported, so it may or may not
 128          * work at all.
 129          * Steven James 02/06/2003
 130          */
 131     /* NOTE: values now configured in configure_e7501_cas_latency() based
 132          *       on SPD info and total number of DIMMs (per Intel)
 133          */
 134
 135         /* FDHC - Fixed DRAM Hole Control
 136          * 0x58
 137          * [7:7] Hole_Enable
 138          *       0 == No memory Hole
 139          *       1 == Memory Hole from 15MB to 16MB
 140          * [6:0] Reserved
 141          *
 142          * PAM - Programmable Attribute Map
 143          * 0x59 [1:0] Reserved
 144          * 0x59 [5:4] 0xF0000 - 0xFFFFF
 145          * 0x5A [1:0] 0xC0000 - 0xC3FFF
 146          * 0x5A [5:4] 0xC4000 - 0xC7FFF
 147          * 0x5B [1:0] 0xC8000 - 0xCBFFF
 148          * 0x5B [5:4] 0xCC000 - 0xCFFFF
 149          * 0x5C [1:0] 0xD0000 - 0xD3FFF
 150          * 0x5C [5:4] 0xD4000 - 0xD7FFF
 151          * 0x5D [1:0] 0xD8000 - 0xDBFFF
 152          * 0x5D [5:4] 0xDC000 - 0xDFFFF
 153          * 0x5E [1:0] 0xE0000 - 0xE3FFF
 154          * 0x5E [5:4] 0xE4000 - 0xE7FFF
 155          * 0x5F [1:0] 0xE8000 - 0xEBFFF
 156          * 0x5F [5:4] 0xEC000 - 0xEFFFF
 157          *       00 == DRAM Disabled (All Access go to memory mapped I/O space)
 158          *       01 == Read Only (Reads to DRAM, Writes to memory mapped I/O space)
 159          *       10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space)
 160          *       11 == Normal (All Access go to DRAM)
 161          */
 162
 163         // Map all legacy ranges to DRAM
 164         0x58, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24),
 165         0x5C, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24),
 166
 167         /* DRB - DRAM Row Boundary Registers
 168          * 0x60 - 0x6F
 169          *     An array of 8 byte registers, which hold the ending
 170          *     memory address assigned  to each pair of DIMMS, in 64MB
 171          *     granularity.
 172          */
 173         // Conservatively say each row has 64MB of ram, we will fix this up later
 174         // NOTE: These defaults allow us to prime all of the DIMMs on the board
 175         //               without jumping through 36-bit adddressing hoops, even if the
 176         //               total memory is > 4 GB. Changing these values may break do_ram_command()!
 177         0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24),
 178         0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24),
 179
 180         /* DRA - DRAM Row Attribute Register
 181          * 0x70 Row 0,1
 182          * 0x71 Row 2,3
 183          * 0x72 Row 4,5
 184          * 0x73 Row 6,7
 185          * [7:7] Device width for Odd numbered rows
 186          *       0 == 8 bits wide x8
 187          *       1 == 4 bits wide x4
 188          * [6:4] Row Attributes for Odd numbered rows
 189          *       010 == 8KB (for dual-channel)
 190          *       011 == 16KB (for dual-channel)
 191          *       100 == 32KB (for dual-channel)
 192          *       101 == 64KB (for dual-channel)
 193          *       Others == Reserved
 194          * [3:3] Device width for Even numbered rows
 195          *       0 == 8 bits wide x8
 196          *       1 == 4 bits wide x4
 197          * [2:0] Row Attributes for Even numbered rows
 198          *       010 == 8KB (for dual-channel)
 199          *       011 == 16KB (for dual-channel)
 200          *       100 == 32KB (for dual-channel)
 201          *       101 == 64KB (This page size appears broken)
 202          *       Others == Reserved
 203          */
 204          // NOTE: overridden by configure_e7501_row_attributes(), later
 205         0x70, 0x00000000, 0,
 206
 207         /* DRT - DRAM Timing Register
 208          * 0x78
 209          * [31:30] Reserved
 210          * [29:29] Back to Back Write-Read Turn Around
 211          *         0 == 3 clocks between WR-RD commands
 212          *         1 == 2 clocks between WR-RD commands
 213          * [28:28] Back to Back Read-Write Turn Around
 214          *         0 == 5 clocks between RD-WR commands
 215          *         1 == 4 clocks between RD-WR commands
 216          * [27:27] Back to Back Read Turn Around
 217          *         0 == 4 clocks between RD commands
 218          *         1 == 3 clocks between RD commands
 219          * [26:24] Read Delay (tRD)
 220          *         000 == 7 clocks
 221          *         001 == 6 clocks
 222          *         010 == 5 clocks
 223          *         Others == Reserved
 224          * [23:19] Reserved
 225          * [18:16] DRAM idle timer
 226          *      000 == infinite
 227          *      011 == 16 dram clocks
 228          *      001 == 0 clocks
 229          * [15:11] Reserved
 230          * [10:09] Active to Precharge (tRAS)
 231          *         00 == 7 clocks
 232          *         01 == 6 clocks
 233          *         10 == 5 clocks
 234          *         11 == Reserved
 235          * [08:06] Reserved
 236          * [05:04] Cas Latency (tCL)
 237          *         00 == 2.5 Clocks
 238          *         01 == 2.0 Clocks
 239          *         10 == Reserved (was 1.5 Clocks for E7500)
 240          *         11 == Reserved
 241          * [03:03] Write Ras# to Cas# Delay (tRCD)
 242          *         0 == 3 DRAM Clocks
 243          *         1 == 2 DRAM Clocks
 244          * [02:01] Read RAS# to CAS# Delay (tRCD)
 245          *         00 == reserved
 246          *         01 == reserved
 247          *         10 == 3 DRAM Clocks
 248          *         11 == 2 DRAM Clocks
 249          * [00:00] DRAM RAS# to Precharge (tRP)
 250          *         0 == 3 DRAM Clocks
 251          *         1 == 2 DRAM Clocks
 252          */
 253
 254          // Some earlier settings:
 255         /* Most aggressive settings possible */
 256 //      0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|CAS_LATENCY|(1<<3)|(1<<1)|(1<<0),
 257 //      0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0),
 258 //      0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0),
 259
 260         // The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and
 261         // Back-to-Back Write-Read Turnaround. All others are configured based on SPD.
 262         0x78, 0xD7F8FFFF, (1<<29)|(1<<27)|(1<<16),
 263
 264         /* FIXME why was I attempting to set a reserved bit? */
 265         /* 0x0100040f */
 266
 267         /* DRC - DRAM Contoller Mode Register
 268          * 0x7c
 269          * [31:30] Reserved
 270          * [29:29] Initialization Complete
 271          *         0 == Not Complete
 272          *         1 == Complete
 273          * [28:23] Reserved
 274          * [22:22]         Channels
 275          *              0 == Single channel
 276          *              1 == Dual Channel
 277          * [21:20] DRAM Data Integrity Mode
 278          *         00 == Disabled, no ECC
 279          *         01 == Reserved
 280          *         10 == Error checking, using chip-kill, with correction
 281          *         11 == Reserved
 282          * [19:18] DRB Granularity (Read-Only)
 283          *         00 == 32 MB quantities (single channel mode)
 284          *                 01 == 64 MB quantities (dual-channel mode)
 285          *                 10 == Reserved
 286          *                 11 == Reserved
 287          * [17:17] (Intel Undocumented) should always be set to 1       (SJM: comment inconsistent with current setting, below)
 288          * [16:16] Command Per Clock - Address/Control Assertion Rule (CPC)
 289          *         0 == 2n Rule
 290          *         1 == 1n rule
 291          * [15:11] Reserved
 292          * [10:08] Refresh mode select
 293          *         000 == Refresh disabled
 294          *         001 == Refresh interval 15.6 usec
 295          *         010 == Refresh interval 7.8 usec
 296          *         011 == Refresh interval 64 usec
 297          *         111 == Refresh every 64 clocks (fast refresh)
 298          * [07:07] Reserved
 299          * [06:04] Mode Select (SMS)
 300          *         000 == Reserved (was Self Refresh Mode in E7500)
 301          *         001 == NOP Command
 302          *         010 == All Banks Precharge
 303          *         011 == Mode Register Set
 304          *         100 == Extended Mode Register Set
 305          *         101 == Reserved
 306          *         110 == CBR Refresh
 307          *         111 == Normal Operation
 308          * [03:00] Reserved
 309          */
 310 //      .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8),
 311 //      .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8),
 312 //      .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8),
 313
 314         // Default to dual-channel mode, ECC, 1-clock address/cmd hold
 315         // NOTE: configure_e7501_dram_controller_mode() configures further
 316         0x7c, 0xff8ef8ff, (1<<22)|(2<<20)|(1<<16)|(0<<8),
 317
 318         /* Another Intel undocumented register
 319          * 0x88 - 0x8B
 320          * [31:31]      Purpose unknown
 321          * [26:26]      Master DLL Reset?
 322          *                      0 == Normal operation?
 323          *                      1 == Reset?
 324          * [07:07]      Periodic memory recalibration?
 325          *                      0 == Disabled?
 326          *                      1 == Enabled?
 327          * [04:04]      Receive FIFO RE-Sync?
 328          *                      0 == Normal operation?
 329          *                      1 == Reset?
 330          */
 331          // NOTE: Some factory BIOSs don't do this.
 332          //               Doesn't seem to matter either way.
 333         0x88, 0xffffff00, 0x80,
 334
 335         /* CLOCK_DIS - CK/CK# Disable Register
 336          * 0x8C
 337          * [7:7] DDR Frequency
 338          *               0 == 100 MHz (200 MHz data rate)
 339          *               1 == 133 MHz (266 MHz data rate)
 340          * [6:4] Reserved
 341          * [3:3] CK3
 342          *       0 == Enable
 343          *       1 == Disable
 344          * [2:2] CK2
 345          *       0 == Enable
 346          *       1 == Disable
 347          * [1:1] CK1
 348          *       0 == Enable
 349          *       1 == Disable
 350          * [0:0] CK0
 351          *       0 == Enable
 352          *       1 == Disable
 353          */
 354         // NOTE: Disable all clocks initially; turn ones we need back on
 355         //               in enable_e7501_clocks()
 356         0x8C, 0xfffffff0, 0xf,
 357
 358         /* TOLM - Top of Low Memory Register
 359          * 0xC4 - 0xC5
 360          * [15:11] Top of low memory (TOLM)
 361          *         The address below 4GB that should be treated as RAM,
 362          *         on a 128MB granularity.
 363          * [10:00] Reserved
 364          */
 365         /* REMAPBASE - Remap Base Address Regsiter
 366          * 0xC6 - 0xC7
 367          * [15:10] Reserved
 368          * [09:00] Remap Base Address [35:26] 64M aligned
 369          *         Bits [25:0] are assumed to be 0.
 370          */
 371
 372         // NOTE: TOLM overridden by configure_e7501_ram_addresses()
 373         0xc4, 0xfc0007ff, (0x2000 << 0) | (0x3ff << 16),
 374
 375         /* REMAPLIMIT - Remap Limit Address Register
 376          * 0xC8 - 0xC9
 377          * [15:10] Reserved
 378          * [09:00] Remap Limit Address [35:26] 64M aligned
 379          * When remaplimit < remapbase the remap window is disabled.
 380          */
 381         0xc8, 0xfffffc00, 0,
 382
 383         /* DVNP - Device Not Present Register
 384          * 0xE0 - 0xE1
 385          * [15:05] Reserved
 386          * [04:04] Device 4 Function 1 Present
 387          *         0 == Present
 388          *         1 == Absent
 389          * [03:03] Device 3 Function 1 Present
 390          *         0 == Present
 391          *         1 == Absent
 392          * [02:02] Device 2 Function 1 Present
 393          *         0 == Present
 394          *         1 == Absent
 395          * [01:01] Reserved
 396          * [00:00] Device 0 Function 1 Present
 397          *         0 == Present
 398          *         1 == Absent
 399          */
 400
 401         // Enable D0:D1, disable D2:F1, D3:F1, D4:F1
 402         0xe0, 0xffffffe2, (1<<4)|(1<<3)|(1<<2)|(0<<0),
 403
 404         // Undocumented
 405         0xd8, 0xffff9fff, 0x00000000,
 406
 407         // Undocumented - this is pure conjecture based on similarity to 855PM
 408         /* MCHTST - MCH Test Register
 409          * 0xF4 - 0xF7
 410          * [31:31] Purpose unknown
 411          * [30:30] Purpose unknown
 412          * [29:23] Unknown - not used?
 413          * [22:22] System Memory MMR Enable
 414          *         0 == Disable: mem space and BAR at 0x14 are not accessible
 415          *         1 == Enable: mem space and BAR at 0x14 are accessible
 416          * [21:20] Purpose unknown
 417          * [19:02] Unknown - not used?
 418          * [01:01] D6EN (Device #6 enable)
 419          *         0 == Disable
 420          *         1 == Enable
 421          * [00:00] Unknown - not used?
 422          */
 423
 424         0xf4, 0x3f8ffffd, 0x40300002,
 425
 426 #ifdef SUSPICIOUS_LOOKING_CODE
 427         // SJM: Undocumented.
 428         //              This will access D2:F0:0x50, is this correct??
 429         0x1050, 0xffffffcf, 0x00000030,
 430 #endif
 431 };
 432
 433         /* DDR RECOMP tables */
 434
 435 // Slew table for 1x drive?
 436 static const uint32_t maybe_1x_slew_table[] = {
 437         0x44332211, 0xc9776655, 0xffffffff, 0xffffffff,
 438         0x22111111, 0x55444332, 0xfffca876, 0xffffffff,
 439 };
 440
 441 // Slew table for 2x drive?
 442 static const uint32_t maybe_2x_slew_table[] = {
 443         0x00000000, 0x76543210, 0xffffeca8, 0xffffffff,
 444         0x21000000, 0xa8765432, 0xffffffec, 0xffffffff,
 445 };
 446
 447 // Pull Up / Pull Down offset table, if analogous to IXP2800?
 448 static const uint32_t maybe_pull_updown_offset_table[] = {
 449         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 450         0x88888888, 0x88888888, 0x88888888, 0x88888888,
 451 };
 452
 453 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
 454 /*                                                                              TABLES                                                                    */
 455 /**********************************************************************************/
 456 #define SLOW_DOWN_IO inb(0x80);
 457 //#define SLOW_DOWN_IO udelay(40);
 458
 459         /* Estimate that SLOW_DOWN_IO takes about 50&76us*/
 460         /* delay for 200us */
 461
 462 #if 1
 463 static void do_delay(void)
 464 {
 465         int i;
 466         for(i = 0; i < 16; i++) { SLOW_DOWN_IO }
 467 }
 468 #define DO_DELAY do_delay();
 469 #else
 470 #define DO_DELAY \
 471         udelay(200);
 472 #endif
 473
 474 #define EXTRA_DELAY DO_DELAY
 475
 476
 477 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
 478 /*                                                                      DELAY FUNCTIONS                                                           */
 479 /**********************************************************************************/
 480
 481 static void die_on_spd_error(int spd_return_value)
 482 {
 483         if (spd_return_value < 0)
 484                 die("Error reading SPD info\n");
 485 }
 486
 487 //----------------------------------------------------------------------------------
 488 // Function:            sdram_spd_get_page_size
 489 // Parameters:          dimm_socket_address - SMBus address of DIMM socket to interrogate
 490 // Return Value:        struct dimm_size - log2(page size) for each side of the DIMM.
 491 // Description:         Calculate the page size for each physical bank of the DIMM:
 492 //                                              log2(page size) = (# columns) + log2(data width)
 493 //
 494 //                                      NOTE: page size is the total number of data bits in a row.
 495 //
 496 static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)
 497 {
 498         uint16_t module_data_width;
 499         int value;
 500         struct dimm_size pgsz;
 501
 502         pgsz.side1 = 0;
 503         pgsz.side2 = 0;
 504
 505         // Side 1
 506         value  = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
 507         if (value < 0) goto hw_err;
 508         pgsz.side1 = value & 0xf;                       // # columns in bank 1
 509
 510         /* Get the module data width and convert it to a power of two */
 511         value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB);
 512         if (value < 0) goto hw_err;
 513         module_data_width = (value & 0xff) << 8;
 514
 515         value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB);
 516         if (value < 0) goto hw_err;
 517         module_data_width |= (value & 0xff);
 518
 519         pgsz.side1 += log2(module_data_width);
 520
 521         /* side two */
 522         value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
 523         if (value < 0) goto hw_err;
 524         if (value > 2)
 525                 die("Bad SPD value\n");
 526         if (value == 2) {
 527
 528                 pgsz.side2 = pgsz.side1;                // Assume symmetric banks until we know differently
 529                 value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
 530                 if (value < 0) goto hw_err;
 531                 if ((value & 0xf0) != 0) {
 532                         // Asymmetric banks
 533                         pgsz.side2 -= value & 0xf;              /* Subtract out columns on side 1 */
 534                         pgsz.side2 += (value>>4) & 0xf; /* Add in columns on side 2 */
 535                 }
 536         }
 537
 538         return pgsz;
 539
 540 hw_err:
 541         die(SPD_ERROR);
 542         return pgsz;    // Never reached
 543 }
 544
 545
 546 //----------------------------------------------------------------------------------
 547 // Function:            sdram_spd_get_width
 548 // Parameters:          dimm_socket_address - SMBus address of DIMM socket to interrogate
 549 // Return Value:        dimm_size - width in bits of each DIMM side's DRAMs.
 550 // Description:         Read the width in bits of each DIMM side's DRAMs via SPD.
 551 //                                      (i.e. 4, 8, 16)
 552 //
 553 static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address)
 554 {
 555         int value;
 556         struct dimm_size width;
 557
 558         width.side1 = 0;
 559         width.side2 = 0;
 560
 561         value = spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH);
 562         die_on_spd_error(value);
 563
 564         width.side1 = value & 0x7f;                     // Mask off bank 2 flag
 565
 566         if (value & 0x80) {
 567                 width.side2 = width.side1 << 1; // Bank 2 exists and is double-width
 568         } else {
 569                 // If bank 2 exists, it's the same width as bank 1
 570                 value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
 571                 die_on_spd_error(value);
 572
 573 #ifdef ROMCC_IF_BUG_FIXED
 574                 if (value == 2)
 575                         width.side2 = width.side1;
 576 #else
 577                 switch (value) {
 578                 case 2:
 579                         width.side2 = width.side1;
 580                         break;
 581
 582                 default:
 583                         break;
 584                 }
 585 #endif
 586         }
 587
 588         return width;
 589 }
 590
 591 //----------------------------------------------------------------------------------
 592 // Function:            spd_get_dimm_size
 593 // Parameters:          dimm_socket_address - SMBus address of DIMM socket to interrogate
 594 // Return Value:        dimm_size - log2(number of bits) for each side of the DIMM
 595 // Description:         Calculate the log base 2 size in bits of both DIMM sides.
 596 //                                              log2(# bits) = (# columns) + log2(data width) +
 597 //                                                                         (# rows) + log2(banks per SDRAM)
 598 //
 599 //                                      Note that it might be easier to use SPD byte 31 here, it has the
 600 //                                      DIMM size as a multiple of 4MB.  The way we do it now we can size
 601 //                                      both sides of an asymmetric dimm.
 602 //
 603 static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address)
 604 {
 605    int value;
 606
 607         // Start with log2(page size)
 608     struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address);
 609
 610         if (sz.side1 > 0) {
 611
 612                 value = spd_read_byte(dimm_socket_address, SPD_NUM_ROWS);
 613                 die_on_spd_error(value);
 614
 615         sz.side1 += value & 0xf;
 616
 617                 if (sz.side2 > 0) {
 618
 619                         // Double-sided DIMM
 620                         if (value & 0xF0)
 621                                 sz.side2 += value >> 4;         // Asymmetric
 622                         else
 623                                 sz.side2 += value;                      // Symmetric
 624                 }
 625
 626         value = spd_read_byte(dimm_socket_address, SPD_NUM_BANKS_PER_SDRAM);
 627         die_on_spd_error(value);
 628
 629                 value = log2(value);
 630         sz.side1 += value;
 631                 if (sz.side2 > 0)
 632                 sz.side2 += value;
 633         }
 634
 635         return sz;
 636 }
 637
 638 //----------------------------------------------------------------------------------
 639 // Function:            are_spd_values_equal
 640 // Parameters:          spd_byte_number -
 641 //                                      dimmN_address - SMBus addresses of DIMM sockets to interrogate
 642 // Return Value:        1 if both DIMM sockets report the same value for the specified
 643 //                                              SPD parameter; 0 if the values differed or an error occurred.
 644 // Description:         Determine whether two DIMMs have the same value for a SPD parameter.
 645 //
 646 static uint8_t are_spd_values_equal(uint8_t spd_byte_number, uint16_t dimm0_address,
 647                                                                         uint16_t dimm1_address)
 648 {
 649         uint8_t bEqual = 0;
 650
 651         int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number);
 652         int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number);
 653
 654         if ((dimm0_value >= 0) && (dimm1_value >= 0) && (dimm0_value == dimm1_value))
 655                 bEqual = 1;
 656
 657         return bEqual;
 658 }
 659
 660 //----------------------------------------------------------------------------------
 661 // Function:            spd_get_supported_dimms
 662 // Parameters:          ctrl - PCI addresses of memory controller functions, and
 663 //                                              SMBus addresses of DIMM slots on the mainboard
 664 // Return Value:        uint8_t - a bitmask indicating which of the possible sockets
 665 //                                              for each channel was found to contain a compatible DIMM.
 666 //                                              Bit 0 corresponds to the closest socket for channel 0,
 667 //                                              Bit 1 to the next socket for channel 0,
 668 //                                              ...
 669 //                                              Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0,
 670 //                                              Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1,
 671 //                                              ...
 672 //                                              Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1
 673 // Description:         Scan for compatible DIMMs.
 674 //                                      The code in this module only supports dual-channel operation,
 675 //                                      so we test that compatible DIMMs are paired.
 676 //
 677 static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
 678 {
 679         int i;
 680         uint8_t dimm_mask = 0;
 681
 682         // Have to increase size of dimm_mask if this assertion is violated
 683         ASSERT(MAX_DIMM_SOCKETS_PER_CHANNEL <= 4);
 684
 685         // Find DIMMs we can support on channel 0.
 686         // Then see if the corresponding channel 1 DIMM has the same parameters,
 687         // since we only support dual-channel.
 688
 689     for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
 690
 691         uint16_t channel0_dimm = ctrl->channel0[i];
 692                 uint16_t channel1_dimm = ctrl->channel1[i];
 693                 uint8_t bDualChannel = 1;
 694                 struct dimm_size        page_size;
 695                 struct dimm_size        sdram_width;
 696                 int spd_value;
 697                 int j;
 698
 699                 if (channel0_dimm == 0)
 700                         continue;               // No such socket on this mainboard
 701
 702         if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR)
 703                         continue;
 704
 705 #ifdef VALIDATE_DIMM_COMPATIBILITY
 706                 if (spd_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) != SPD_VOLTAGE_SSTL2)
 707                         continue;               // Unsupported voltage
 708
 709                 // E7501 does not support unregistered DIMMs
 710                 spd_value = spd_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES);
 711                 if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0))
 712                         continue;
 713
 714         // Must support burst = 4 for dual-channel operation on E7501
 715                 // NOTE: for single-channel, burst = 8 is required
 716                 spd_value = spd_read_byte(channel0_dimm, SPD_SUPPORTED_BURST_LENGTHS);
 717                 if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
 718                         continue;
 719
 720         page_size       = sdram_spd_get_page_size(channel0_dimm);
 721                 sdram_width = sdram_spd_get_width(channel0_dimm);
 722
 723                 // Validate DIMM page size
 724                 // The E7501 only supports page sizes of 4, 8, 16, or 32 KB per channel
 725                 // NOTE: 4 KB =  32 Kb = 2^15
 726                 //              32 KB = 262 Kb = 2^18
 727
 728                 if ((page_size.side1 < 15) || (page_size.side1 > 18))
 729                         continue;
 730
 731                 // If DIMM is double-sided, verify side2 page size
 732         if (page_size.side2 != 0) {
 733             if ((page_size.side2 < 15) || (page_size.side2 > 18))
 734                                 continue;
 735                 }
 736
 737                 // Validate SDRAM width
 738                 // The E7501 only supports x4 and x8 devices
 739
 740                 if ((sdram_width.side1 != 4) && (sdram_width.side1 != 8))
 741                         continue;
 742
 743                 // If DIMM is double-sided, verify side2 width
 744         if (sdram_width.side2 != 0) {
 745                         if ((sdram_width.side2 != 4) && (sdram_width.side2 != 8))
 746                                 continue;
 747                 }
 748 #endif
 749                 // Channel 0 DIMM looks compatible.
 750                 // Now see if it is paired with the proper DIMM on channel 1.
 751
 752                 ASSERT(channel1_dimm != 0);             // No such socket on this mainboard??
 753
 754                 // NOTE: unpopulated DIMMs cause read to fail
 755                 spd_value = spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
 756                 if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
 757
 758                         print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
 759                         continue;
 760                 }
 761
 762 #ifdef VALIDATE_DIMM_COMPATIBILITY
 763                 spd_value = spd_read_byte(channel1_dimm, SPD_SUPPORTED_BURST_LENGTHS);
 764                 if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
 765                         continue;
 766
 767                 for (j=0; j<sizeof(dual_channel_parameters); ++j) {
 768                         if (!are_spd_values_equal(dual_channel_parameters[j], channel0_dimm, channel1_dimm)) {
 769
 770                                 bDualChannel = 0;
 771                                 break;
 772                         }
 773                 }
 774 #endif
 775
 776                 // Code around ROMCC bug in optimization of "if" statements
 777 #ifdef ROMCC_IF_BUG_FIXED
 778                 if (bDualChannel) {
 779                         // Made it through all the checks, this DIMM pair is usable
 780                         dimm_mask |= ((1<<i) | (1<<(MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
 781                 }
 782                 else
 783                         print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
 784 #else
 785                 switch (bDualChannel) {
 786                 case 0:
 787                         print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
 788                         break;
 789
 790                 default:
 791                         // Made it through all the checks, this DIMM pair is usable
 792                         dimm_mask |= (1<<i) | (1<<(MAX_DIMM_SOCKETS_PER_CHANNEL + i));
 793                         break;
 794                 }
 795 #endif
 796         }
 797
 798         return dimm_mask;
 799 }
 800
 801 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
 802 /*                                              SPD (SERIAL PRESENCE DETECT) FUNCTIONS                                    */
 803 /**********************************************************************************/
 804
 805 //----------------------------------------------------------------------------------
 806 // Function:            do_ram_command
 807 // Parameters:
 808 //                                      command - specifies the command to be sent to the DIMMs:
 809 //                                              RAM_COMMAND_NOP                 - No Operation
 810 //                                              RAM_COMMAND_PRECHARGE   - Precharge all banks
 811 //                                              RAM_COMMAND_MRS                 - Load Mode Register
 812 //                                              RAM_COMMAND_EMRS                - Load Extended Mode Register
 813 //                                              RAM_COMMAND_CBR                 - Auto Refresh ("CAS-before-RAS")
 814 //                                              RAM_COMMAND_NORMAL              - Normal operation
 815 //                                      jedec_mode_bits - for mode register set & extended mode register set
 816 //                                              commands, bits 0-12 contain the register value in JEDEC format.
 817 // Return Value:        None
 818 // Description:         Send the specified command to all DIMMs.
 819 //
 820 static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
 821 {
 822     int i;
 823         uint32_t dram_controller_mode;
 824         uint8_t dimm_start_64M_multiple = 0;
 825         uint16_t e7501_mode_bits = jedec_mode_bits;
 826
 827         // Configure the RAM command
 828     dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
 829     dram_controller_mode &= 0xFFFFFF8F;
 830     dram_controller_mode |= command;
 831     pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
 832
 833         // RAM_COMMAND_NORMAL is an exception.
 834         // It affects only the memory controller and does not need to be "sent" to the DIMMs.
 835
 836         if (command != RAM_COMMAND_NORMAL) {
 837
 838                 // Send the command to all DIMMs by accessing a memory location within each
 839                 // NOTE: for mode select commands, some of the location address bits
 840                 //               are part of the command
 841
 842                 // Map JEDEC mode bits to E7501
 843                 if (command == RAM_COMMAND_MRS) {
 844                         // Host address lines [15:5] map to DIMM address lines [12:11, 9:1]
 845                         // The E7501 hard-sets DIMM address lines 10 & 0 to zero
 846
 847                         ASSERT(!(jedec_mode_bits & 0x0401));
 848
 849                         e7501_mode_bits = ((jedec_mode_bits & 0x1800) << (15-12)) |             // JEDEC bits 11-12 move to bits 14-15
 850                                                           ((jedec_mode_bits & 0x03FE) << (13-9));               // JEDEC bits 1-9 move to bits 5-13
 851
 852                 } else if (command == RAM_COMMAND_EMRS) {
 853                         // Host address lines [15:3] map to DIMM address lines [12:0]
 854                         e7501_mode_bits = jedec_mode_bits <<= 3;
 855                 } else
 856                         ASSERT(jedec_mode_bits == 0);
 857
 858
 859                 dimm_start_64M_multiple = 0;
 860
 861                 for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
 862
 863                         uint8_t dimm_end_64M_multiple = pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i);
 864                         if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
 865
 866                                 // This code assumes DRAM row boundaries are all set below 4 GB
 867                                 // NOTE: 0x40 * 64 MB == 4 GB
 868                                 ASSERT(dimm_start_64M_multiple < 0x40);
 869
 870                                 // NOTE: 2^26 == 64 MB
 871
 872                                 uint32_t dimm_start_address = dimm_start_64M_multiple << 26;
 873
 874                                 RAM_DEBUG_MESSAGE("    Sending RAM command to 0x");
 875                                 RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits);
 876                                 RAM_DEBUG_MESSAGE("\n");
 877                                 read32(dimm_start_address + e7501_mode_bits);
 878
 879                                 // Set the start of the next DIMM
 880                                 dimm_start_64M_multiple = dimm_end_64M_multiple;
 881                         }
 882                 }
 883         }
 884 }
 885
 886 //----------------------------------------------------------------------------------
 887 // Function:            set_ram_mode
 888 // Parameters:          jedec_mode_bits - for mode register set & extended mode register set
 889 //                      commands, bits 0-12 contain the register value in JEDEC format.
 890 // Return Value:        None
 891 // Description:         Set the mode register of all DIMMs. The proper CAS# latency
 892 //                                      setting is added to the mode bits specified by the caller.
 893 //
 894 static void set_ram_mode(uint16_t jedec_mode_bits)
 895 {
 896         ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK));
 897
 898         uint32_t dram_cas_latency = pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK;
 899
 900         switch (dram_cas_latency) {
 901         case DRT_CAS_2_5:
 902                 jedec_mode_bits |= SDRAM_CAS_2_5;
 903                 break;
 904
 905         case DRT_CAS_2_0:
 906                 jedec_mode_bits |= SDRAM_CAS_2_0;
 907                 break;
 908
 909         default:
 910                 BUG();
 911                 break;
 912         }
 913
 914         do_ram_command(RAM_COMMAND_MRS, jedec_mode_bits);
 915 }
 916
 917 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
 918 /*                                                      SDRAM CONFIGURATION FUNCTIONS                                             */
 919 /**********************************************************************************/
 920
 921 //----------------------------------------------------------------------------------
 922 // Function:            configure_dimm_row_boundaries
 923 // Parameters:
 924 //                                      dimm_log2_num_bits - log2(number of bits) for each side of the DIMM
 925 //                                      total_dram_64M_multiple - total DRAM in the system (as a
 926 //                                              multiple of 64 MB) for DIMMs < dimm_index
 927 //                                      dimm_index - which DIMM pair is being processed
 928 //                                                               (0..MAX_DIMM_SOCKETS_PER_CHANNEL)
 929 // Return Value:        New multiple of 64 MB total DRAM in the system
 930 // Description:         Configure the E7501's DRAM Row Boundary registers for the memory
 931 //                                      present in the specified DIMM.
 932 //
 933 static uint8_t configure_dimm_row_boundaries(
 934                                                                                          struct dimm_size dimm_log2_num_bits,
 935                                                                                          uint8_t total_dram_64M_multiple,
 936                                                                                          unsigned dimm_index)
 937 {
 938         int i;
 939
 940         ASSERT(dimm_index < MAX_DIMM_SOCKETS_PER_CHANNEL);
 941
 942         // DIMM sides must be at least 32 MB
 943         ASSERT(dimm_log2_num_bits.side1 >= 28);
 944         ASSERT((dimm_log2_num_bits.side2 == 0) || (dimm_log2_num_bits.side2 >= 28));
 945
 946         // In dual-channel mode, we are called only once for each pair of DIMMs.
 947         // Each time we process twice the capacity of a single DIMM.
 948
 949         // Convert single DIMM capacity to paired DIMM capacity
 950         // (multiply by two ==> add 1 to log2)
 951         dimm_log2_num_bits.side1++;
 952         if (dimm_log2_num_bits.side2 > 0)
 953                 dimm_log2_num_bits.side2++;
 954
 955         // Add the capacity of side 1 this DIMM pair (as a multiple of 64 MB)
 956         // to the total capacity of the system
 957         // NOTE: 64 MB == 512 Mb, and log2(512 Mb) == 29
 958
 959         total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29));
 960
 961         // Configure the boundary address for the row on side 1
 962         pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0+(dimm_index<<1), total_dram_64M_multiple);
 963
 964         // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair
 965         // (as a multiple of 64 MB) to the total capacity of the system
 966     if (dimm_log2_num_bits.side2 >= 29)
 967                 total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side2 - 29));
 968
 969         // Configure the boundary address for the row (if any) on side 2
 970     pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1+(dimm_index<<1), total_dram_64M_multiple);
 971
 972         // Update boundaries for rows subsequent to these.
 973         // These settings will be overridden by a subsequent call if a populated physical slot exists
 974
 975     for(i=dimm_index+1; i<MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
 976                 pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0+(i<<1), total_dram_64M_multiple);
 977         pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1+(i<<1), total_dram_64M_multiple);
 978         }
 979
 980     return total_dram_64M_multiple;
 981 }
 982
 983 //----------------------------------------------------------------------------------
 984 // Function:            configure_e7501_ram_addresses
 985 // Parameters:          ctrl - PCI addresses of memory controller functions, and
 986 //                                              SMBus addresses of DIMM slots on the mainboard
 987 //                                      dimm_mask - bitmask of populated DIMMs on the board - see
 988 //                                                              spd_get_supported_dimms()
 989 // Return Value:        None
 990 // Description:         Program the E7501's DRAM row boundary addresses and its Top Of
 991 //                                      Low Memory (TOLM). If necessary, set up a remap window so we
 992 //                                      don't waste DRAM that ordinarily would lie behind addresses
 993 //                                      reserved for memory-mapped I/O.
 994 //
 995 static void configure_e7501_ram_addresses(const struct mem_controller *ctrl,
 996                                                                                   uint8_t dimm_mask)
 997 {
 998         int i;
 999     uint8_t total_dram_64M_multiple = 0;
1000
1001         // Configure the E7501's DRAM row boundaries
1002         // Start by zeroing out the temporary initial configuration
1003         pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_0, 0);
1004         pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_4, 0);
1005
1006         for(i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1007
1008         uint16_t dimm_socket_address = ctrl->channel0[i];
1009                 struct dimm_size sz;
1010
1011         if (!(dimm_mask & (1 << i)))
1012                         continue;               // This DIMM not present
1013
1014         sz = spd_get_dimm_size(dimm_socket_address);
1015
1016         RAM_DEBUG_MESSAGE("dimm size =");
1017         RAM_DEBUG_HEX32(sz.side1);
1018         RAM_DEBUG_MESSAGE(" ");
1019         RAM_DEBUG_HEX32(sz.side2);
1020         RAM_DEBUG_MESSAGE("\n");
1021
1022                 if (sz.side1 == 0)
1023                         die("Bad SPD value\n");
1024
1025                 total_dram_64M_multiple = configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i);
1026         }
1027
1028         // Configure the Top Of Low Memory (TOLM) in the E7501
1029         // This address must be a multiple of 128 MB that is less than 4 GB.
1030         // NOTE: 16-bit wide TOLM register stores only the highest 5 bits of a 32-bit address
1031         //               in the highest 5 bits.
1032
1033         // We set TOLM to the smaller of 0xC0000000 (3 GB) or the total DRAM in the system.
1034         // This reserves addresses from 0xC0000000 - 0xFFFFFFFF for non-DRAM purposes
1035         // such as flash and memory-mapped I/O.
1036
1037         // If there is more than 3 GB of DRAM, we define a remap window which
1038         // makes the DRAM "behind" the reserved region available above the top of physical
1039         // memory.
1040
1041         // NOTE: 0xC0000000 / (64 MB) == 0x30
1042
1043     if (total_dram_64M_multiple <= 0x30)  {
1044
1045                 // <= 3 GB total RAM
1046
1047                 /* I should really adjust all of this in C after I have resources
1048          * to all of the pci devices.
1049          */
1050
1051                 // Round up to 128MB granularity
1052                 // SJM: Is "missing" 64 MB of memory a potential issue? Should this round down?
1053
1054                 uint8_t total_dram_128M_multiple = (total_dram_64M_multiple + 1) >> 1;
1055
1056                 // Convert to high 16 bits of address
1057                 uint16_t top_of_low_memory = total_dram_128M_multiple << 11;
1058
1059         pci_write_config16(PCI_DEV(0, 0, 0), TOLM, top_of_low_memory);
1060
1061         } else {
1062
1063                 // > 3 GB total RAM
1064
1065                 // Set defaults for > 4 GB DRAM, i.e. remap a 1 GB (= 0x10 * 64 MB) range of memory
1066                 uint16_t remap_base = total_dram_64M_multiple;                          // A[25:0] == 0
1067                 uint16_t remap_limit = total_dram_64M_multiple + 0x10 - 1;      // A[25:0] == 0xF
1068
1069                 // Put TOLM at 3 GB
1070
1071                 pci_write_config16(PCI_DEV(0, 0, 0), TOLM, 0xc000);
1072
1073                 // Define a remap window to make the RAM that would appear from 3 GB - 4 GB
1074                 // visible just beyond 4 GB or the end of physical memory, whichever is larger
1075                 // NOTE: 16-bit wide REMAP registers store only the highest 10 bits of a 36-bit address,
1076                 //               (i.e. a multiple of 64 MB) in the lowest 10 bits.
1077                 // NOTE: 0x100000000 / (64 MB) == 0x40
1078
1079         if (total_dram_64M_multiple < 0x40) {
1080                         remap_base = 0x40;              // 0x100000000
1081                         remap_limit = 0x40 + (total_dram_64M_multiple - 0x30) - 1;
1082                 }
1083
1084         pci_write_config16(PCI_DEV(0, 0, 0), REMAPBASE, remap_base);
1085         pci_write_config16(PCI_DEV(0, 0, 0), REMAPLIMIT, remap_limit);
1086         }
1087 }
1088
1089 //----------------------------------------------------------------------------------
1090 // Function:            initialize_ecc
1091 // Parameters:          None
1092 // Return Value:        None
1093 // Description:         If we're configured to use ECC, initialize the SDRAM and
1094 //                                      clear the E7501's ECC error flags.
1095 //
1096 static void initialize_ecc(void)
1097 {
1098         uint32_t dram_controller_mode;
1099
1100         /* Test to see if ECC support is enabled */
1101         dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
1102         dram_controller_mode >>= 20;
1103         dram_controller_mode &= 3;
1104         if (dram_controller_mode == 2)  {
1105
1106                 uint8_t byte;
1107
1108                 RAM_DEBUG_MESSAGE("Initializing ECC state...\n");
1109                 /* Initialize ECC bits , use ECC zero mode (new to 7501)*/
1110                 pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x06);
1111                 pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x07);
1112
1113                 // Wait for scrub cycle to complete
1114                 do {
1115                         byte = pci_read_config8(PCI_DEV(0, 0, 0), MCHCFGNS);
1116
1117                 } while ( (byte & 0x08 ) == 0);
1118
1119                 pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, byte & 0xfc);
1120                 RAM_DEBUG_MESSAGE("ECC state initialized.\n");
1121
1122                 /* Clear the ECC error bits */
1123                 pci_write_config8(PCI_DEV(0, 0, 1), DRAM_FERR, 0x03);
1124                 pci_write_config8(PCI_DEV(0, 0, 1), DRAM_NERR, 0x03);
1125
1126                 // Clear DRAM Interface error bits (write-one-clear)
1127                 pci_write_config32(PCI_DEV(0, 0, 1), FERR_GLOBAL, 1<<18);
1128             pci_write_config32(PCI_DEV(0, 0, 1), NERR_GLOBAL, 1<<18);
1129
1130                 // Start normal ECC scrub
1131                 pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 5);
1132         }
1133
1134 }
1135
1136 //----------------------------------------------------------------------------------
1137 // Function:            configure_e7501_dram_timing
1138 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1139 //                                              SMBus addresses of DIMM slots on the mainboard
1140 //                                      dimm_mask - bitmask of populated DIMMs on the board - see
1141 //                                                              spd_get_supported_dimms()
1142 // Return Value:        None
1143 // Description:         Program the DRAM Timing register of the E7501 (except for CAS#
1144 //                                      latency, which is assumed to have been programmed already), based
1145 //                                      on the parameters of the various installed DIMMs.
1146 //
1147 static void configure_e7501_dram_timing(const struct mem_controller *ctrl, uint8_t dimm_mask)
1148 {
1149         int i;
1150     uint32_t dram_timing;
1151     int value;
1152         uint8_t slowest_row_precharge = 0;
1153         uint8_t slowest_ras_cas_delay = 0;
1154         uint8_t slowest_active_to_precharge_delay = 0;
1155         uint32_t current_cas_latency = pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK;
1156
1157         // CAS# latency must be programmed beforehand
1158         ASSERT((current_cas_latency == DRT_CAS_2_0) || (current_cas_latency == DRT_CAS_2_5));
1159
1160         // Each timing parameter is determined by the slowest DIMM
1161
1162         for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1163
1164         uint16_t dimm_socket_address;
1165
1166                 if (!(dimm_mask & (1 << i)))
1167                         continue;               // This DIMM not present
1168
1169                 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1170                         dimm_socket_address = ctrl->channel0[i];
1171                 else
1172                         dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
1173
1174         value = spd_read_byte(dimm_socket_address, SPD_MIN_ROW_PRECHARGE_TIME);
1175         if (value < 0) goto hw_err;
1176                 if (value > slowest_row_precharge)
1177                         slowest_row_precharge = value;
1178
1179                 value = spd_read_byte(dimm_socket_address, SPD_MIN_RAS_TO_CAS_DELAY);
1180                 if(value < 0 ) goto hw_err;
1181                 if (value > slowest_ras_cas_delay)
1182                         slowest_ras_cas_delay = value;
1183
1184                 value = spd_read_byte(dimm_socket_address, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
1185                 if(value < 0 ) goto hw_err;
1186                 if (value > slowest_active_to_precharge_delay)
1187                         slowest_active_to_precharge_delay = value;
1188         }
1189
1190         // NOTE for timing parameters:
1191         //              At 133 MHz, 1 clock == 7.52 ns
1192
1193     /* Read the initial state */
1194     dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT);
1195
1196         /* Trp */
1197
1198         // E7501 supports only 2 or 3 clocks for tRP
1199         if (slowest_row_precharge > ((22<<2) | (2<<0)))
1200                 die("unsupported DIMM tRP");                    // > 22.5 ns: 4 or more clocks
1201         else if (slowest_row_precharge > (15<<2))
1202                 dram_timing &= ~(1<<0);                                 // > 15.0 ns: 3 clocks
1203         else
1204                 dram_timing |= (1<<0);                                  // <= 15.0 ns: 2 clocks
1205
1206         /*  Trcd */
1207
1208         // E7501 supports only 2 or 3 clocks for tRCD
1209         // Use the same value for both read & write
1210         dram_timing &= ~((1<<3)|(3<<1));
1211         if (slowest_ras_cas_delay > ((22<<2) | (2<<0)))
1212                 die("unsupported DIMM tRCD");                   // > 22.5 ns: 4 or more clocks
1213         else if (slowest_ras_cas_delay > (15<<2))
1214                 dram_timing |= (2<<1);                                  // > 15.0 ns: 3 clocks
1215         else
1216                 dram_timing |= ((1<<3) | (3<<1));               // <= 15.0 ns: 2 clocks
1217
1218         /* Tras */
1219
1220         // E7501 supports only 5, 6, or 7 clocks for tRAS
1221         // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns
1222         dram_timing &= ~(3<<9);
1223
1224         if (slowest_active_to_precharge_delay > 52)
1225                 die("unsupported DIMM tRAS");                                   // > 52 ns:      8 or more clocks
1226         else if (slowest_active_to_precharge_delay > 45)
1227                 dram_timing |= (0<<9);                                                  // 46-52 ns: 7 clocks
1228         else if (slowest_active_to_precharge_delay > 37)
1229                 dram_timing |= (1<<9);                                                  // 38-45 ns: 6 clocks
1230         else
1231                 dram_timing |= (2<<9);                                                  // < 38 ns:      5 clocks
1232
1233
1234         /* Trd */
1235
1236         /* Set to a 7 clock read delay. This is for 133Mhz
1237         *  with a CAS latency of 2.5  if 2.0 a 6 clock
1238         *  delay is good  */
1239
1240         dram_timing &= ~(7<<24);                // 7 clocks
1241         if (current_cas_latency == DRT_CAS_2_0)
1242                 dram_timing |= (1<<24);         // 6 clocks
1243
1244         /*
1245          * Back to Back Read-Write Turn Around
1246          */
1247         /* Set to a 5 clock back to back read to write turn around.
1248          *  4 is a good delay if the CAS latency is 2.0 */
1249
1250         dram_timing &= ~(1<<28);                // 5 clocks
1251         if (current_cas_latency == DRT_CAS_2_0)
1252                 dram_timing |= (1<<28);         // 4 clocks
1253
1254         pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing);
1255
1256         return;
1257
1258 hw_err:
1259         die(SPD_ERROR);
1260 }
1261
1262 //----------------------------------------------------------------------------------
1263 // Function:            configure_e7501_cas_latency
1264 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1265 //                                              SMBus addresses of DIMM slots on the mainboard
1266 //                                      dimm_mask - bitmask of populated DIMMs on the board - see
1267 //                                                              spd_get_supported_dimms()
1268 // Return Value:        None
1269 // Description:         Determine the shortest CAS# latency that the E7501 and all DIMMs
1270 //                                      have in common, and program the E7501 to use it.
1271 //
1272 static void configure_e7501_cas_latency(const struct mem_controller *ctrl, uint8_t dimm_mask)
1273 {
1274         int i;
1275         int value;
1276         uint32_t dram_timing;
1277         uint16_t maybe_dram_read_timing;
1278         uint32_t dword;
1279
1280         // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format
1281         // NOTE: E7501 supports only 2.0 and 2.5
1282         uint32_t system_compatible_cas_latencies = SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5;
1283         uint32_t current_cas_latency;
1284         uint32_t dimm_compatible_cas_latencies;
1285
1286         for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1287
1288         uint16_t dimm_socket_address;
1289
1290                 if (!(dimm_mask & (1 << i)))
1291                         continue;               // This DIMM not usable
1292
1293                 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1294                         dimm_socket_address = ctrl->channel0[i];
1295                 else
1296                         dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
1297
1298                 value = spd_read_byte(dimm_socket_address, SPD_ACCEPTABLE_CAS_LATENCIES);
1299                 if (value < 0) goto hw_err;
1300
1301         dimm_compatible_cas_latencies = value & 0x7f;                                           // Start with all supported by DIMM
1302                 current_cas_latency = 1 << log2(dimm_compatible_cas_latencies);         // Max supported by DIMM
1303
1304                 // Can we support the highest CAS# latency?
1305
1306                 value = spd_read_byte(dimm_socket_address, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
1307                 if (value < 0) goto hw_err;
1308
1309                 // NOTE: At 133 MHz, 1 clock == 7.52 ns
1310                 if (value > 0x75) {
1311                         // Our bus is too fast for this CAS# latency
1312                         // Remove it from the bitmask of those supported by the DIMM that are compatible
1313                         dimm_compatible_cas_latencies &= ~current_cas_latency;
1314                 }
1315
1316                 // Can we support the next-highest CAS# latency (max - 0.5)?
1317
1318                 current_cas_latency >>= 1;
1319                 if (current_cas_latency != 0) {
1320                         value = spd_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_2ND);
1321                         if(value < 0 ) goto hw_err;
1322                         if(value > 0x75)
1323                                 dimm_compatible_cas_latencies &= ~current_cas_latency;
1324                 }
1325
1326                 // Can we support the next-highest CAS# latency (max - 1.0)?
1327                 current_cas_latency >>= 1;
1328                 if (current_cas_latency != 0) {
1329                         value = spd_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_3RD);
1330             if(value < 0 ) goto hw_err;
1331             if(value > 0x75)
1332                 dimm_compatible_cas_latencies &= ~current_cas_latency;
1333                 }
1334
1335                 // Restrict the system to CAS# latencies compatible with this DIMM
1336                 system_compatible_cas_latencies &= dimm_compatible_cas_latencies;
1337
1338         /* go to the next DIMM */
1339         }
1340
1341         /* After all of the arduous calculation setup with the fastest
1342          * cas latency I can use.
1343          */
1344
1345         dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT);
1346         dram_timing &= ~(DRT_CAS_MASK);
1347
1348         maybe_dram_read_timing = pci_read_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL);
1349         maybe_dram_read_timing &= 0xF00C;
1350
1351         if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) {
1352                 dram_timing |= DRT_CAS_2_0;
1353                 maybe_dram_read_timing |= 0xBB1;
1354         }
1355         else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
1356
1357                 uint32_t dram_row_attributes = pci_read_config32(PCI_DEV(0, 0, 0), DRA);
1358
1359                 dram_timing |= DRT_CAS_2_5;
1360
1361                 // At CAS# 2.5, DRAM Read Timing (if that's what it its) appears to need a slightly
1362                 // different value if all DIMM slots are populated
1363
1364                 if ((dram_row_attributes & 0xff)         && (dram_row_attributes & 0xff00) &&
1365                         (dram_row_attributes & 0xff0000) && (dram_row_attributes & 0xff000000)) {
1366
1367                         // All slots populated
1368                         maybe_dram_read_timing |= 0x0882;
1369                 }
1370                 else {
1371                         // Some unpopulated slots
1372                         maybe_dram_read_timing |= 0x0662;
1373                 }
1374         }
1375         else
1376                 die("No CAS# latencies compatible with all DIMMs!!\n");
1377
1378         pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing);
1379
1380         /* set master DLL reset */
1381         dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88);
1382         dword |= (1<<26);
1383         pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
1384
1385         dword &= 0x0c0007ff;    /* patch try register 88 is undocumented tnz */
1386         dword |= 0xd2109800;
1387
1388         pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
1389
1390
1391         pci_write_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL, maybe_dram_read_timing);
1392
1393         dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88);      /* reset master DLL reset */
1394         dword &= ~(1<<26);
1395         pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
1396
1397         return;
1398
1399 hw_err:
1400         die(SPD_ERROR);
1401 }
1402
1403 //----------------------------------------------------------------------------------
1404 // Function:            configure_e7501_dram_controller_mode
1405 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1406 //                                              SMBus addresses of DIMM slots on the mainboard
1407 //                                      dimm_mask - bitmask of populated DIMMs on the board - see
1408 //                                                              spd_get_supported_dimms()
1409 // Return Value:        None
1410 // Description:         Configure the refresh interval so that we refresh no more often
1411 //                                      than required by the "most needy" DIMM. Also disable ECC if any
1412 //                                      of the DIMMs don't support it.
1413 //
1414 static void configure_e7501_dram_controller_mode(const struct mem_controller *ctrl,
1415                                                                                                  uint8_t dimm_mask)
1416 {
1417         int i;
1418
1419         // Initial settings
1420     uint32_t controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
1421         uint32_t system_refresh_mode = (controller_mode >> 8) & 7;
1422
1423         // Code below assumes that most aggressive settings are in
1424         // force when we are called, either via E7501 reset defaults
1425         // or by sdram_set_registers():
1426         //      - ECC enabled
1427         //      - No refresh
1428
1429         ASSERT((controller_mode & (3<<20)) == (2<<20));         // ECC
1430         ASSERT(!(controller_mode & (7 << 8)));          // Refresh
1431
1432     /* Walk through _all_ dimms and find the least-common denominator for:
1433          *      - ECC support
1434      *  - refresh rates
1435      */
1436
1437         for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1438
1439                 uint32_t dimm_refresh_mode;
1440             int value;
1441         uint16_t dimm_socket_address;
1442
1443                 if (!(dimm_mask & (1 << i))) {
1444                         continue;               // This DIMM not usable
1445         }
1446
1447                 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1448                         dimm_socket_address = ctrl->channel0[i];
1449                 else
1450                         dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
1451
1452                 // Disable ECC mode if any one of the DIMMs does not support ECC
1453                 // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported.
1454
1455                 value = spd_read_byte(dimm_socket_address, SPD_DIMM_CONFIG_TYPE);
1456         die_on_spd_error(value);
1457                 if (value != ERROR_SCHEME_ECC) {
1458                         controller_mode &= ~(3 << 20);
1459                 }
1460
1461                 value = spd_read_byte(dimm_socket_address, SPD_REFRESH);
1462                 die_on_spd_error(value);
1463                 value &= 0x7f;          // Mask off self-refresh bit
1464                 if(value > MAX_SPD_REFRESH_RATE) {
1465                         print_err("unsupported refresh rate\n");
1466                         continue;
1467                 }
1468
1469                 // Get the appropriate E7501 refresh mode for this DIMM
1470                 dimm_refresh_mode = refresh_rate_map[value];
1471                 if (dimm_refresh_mode > 7) {
1472                         print_err("unsupported refresh rate\n");
1473                         continue;
1474                 }
1475
1476                 // If this DIMM requires more frequent refresh than others,
1477                 // update the system setting
1478                 if (refresh_frequency[dimm_refresh_mode] > refresh_frequency[system_refresh_mode])
1479                         system_refresh_mode = dimm_refresh_mode;
1480
1481 #ifdef SUSPICIOUS_LOOKING_CODE
1482 // SJM NOTE: This code doesn't look right. SPD values are an order of magnitude smaller
1483 //                       than the clock period of the memory controller. Also, no other northbridge
1484 //                       looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME.
1485
1486                 // Switch to 2 clocks for address/command if required by any one of the DIMMs
1487                 // NOTE: At 133 MHz, 1 clock == 7.52 ns
1488                 value = spd_read_byte(dimm_socket_address, SPD_CMD_SIGNAL_INPUT_HOLD_TIME);
1489                 die_on_spd_error(value);
1490                 if(value >= 0xa0) {             /* At 133MHz this constant should be 0x75 */
1491                         controller_mode &= ~(1<<16);    /* Use two clock cyles instead of one */
1492                 }
1493 #endif
1494
1495         /* go to the next DIMM */
1496         }
1497
1498         controller_mode |= (system_refresh_mode << 8);
1499
1500         // Configure the E7501
1501         pci_write_config32(PCI_DEV(0, 0, 0), DRC, controller_mode);
1502 }
1503
1504 //----------------------------------------------------------------------------------
1505 // Function:            configure_e7501_row_attributes
1506 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1507 //                                              SMBus addresses of DIMM slots on the mainboard
1508 //                                      dimm_mask - bitmask of populated DIMMs on the board - see
1509 //                                                              spd_get_supported_dimms()
1510 // Return Value:        None
1511 // Description:         Configure the E7501's DRAM Row Attributes (DRA) registers
1512 //                                      based on DIMM parameters read via SPD. This tells the controller
1513 //                                      the width of the SDRAM chips on each DIMM side (x4 or x8) and
1514 //                                      the page size of each DIMM side (4, 8, 16, or 32 KB).
1515 //
1516 static void configure_e7501_row_attributes(const struct mem_controller *ctrl,
1517                                                                                    uint8_t dimm_mask)
1518 {
1519         int i;
1520         uint32_t row_attributes = 0;
1521
1522     for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1523
1524         uint16_t dimm_socket_address = ctrl->channel0[i];
1525                 struct dimm_size        page_size;
1526                 struct dimm_size        sdram_width;
1527
1528                 if (!(dimm_mask & (1 << i)))
1529                         continue;               // This DIMM not usable
1530
1531                 // Get the relevant parameters via SPD
1532                 page_size       = sdram_spd_get_page_size(dimm_socket_address);
1533                 sdram_width = sdram_spd_get_width(dimm_socket_address);
1534
1535                 // Update the DRAM Row Attributes.
1536                 // Page size is encoded as log2(page size in bits) - log2(8 Kb)
1537                 // NOTE: 8 Kb = 2^13
1538                 row_attributes |= (page_size.side1 - 13) << (i<<3);                     // Side 1 of each DIMM is an EVEN row
1539
1540                 if (sdram_width.side2 > 0)
1541                         row_attributes |= (page_size.side2 - 13) << ((i<<3) + 4);       // Side 2 is ODD
1542
1543                 // Set x4 flags if appropriate
1544                 if (sdram_width.side1 == 4) {
1545                         row_attributes |= 0x08 << (i<<3);
1546                 }
1547
1548                 if (sdram_width.side2 == 4) {
1549                         row_attributes |= 0x08 << ((i<<3) + 4);
1550         }
1551
1552         /* go to the next DIMM */
1553         }
1554
1555         /* Write the new row attributes register */
1556         pci_write_config32(PCI_DEV(0, 0, 0), DRA, row_attributes);
1557 }
1558
1559 //----------------------------------------------------------------------------------
1560 // Function:            enable_e7501_clocks
1561 // Parameters:          dimm_mask - bitmask of populated DIMMs on the board - see
1562 //                                                              spd_get_supported_dimms()
1563 // Return Value:        None
1564 // Description:         Enable clock signals for populated DIMM sockets and disable them
1565 //                                      for unpopulated sockets (to reduce EMI).
1566 //
1567 static void enable_e7501_clocks(uint8_t dimm_mask)
1568 {
1569         int i;
1570         uint8_t clock_disable = pci_read_config8(PCI_DEV(0, 0, 0), CKDIS);
1571
1572         for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1573
1574                 uint8_t socket_mask = 1 << i;
1575
1576                 if (dimm_mask & socket_mask)
1577                         clock_disable &= ~socket_mask;  // DIMM present, enable clock
1578                 else
1579                         clock_disable |= socket_mask;   // DIMM absent, disable clock
1580         }
1581
1582         pci_write_config8(PCI_DEV(0, 0, 0), CKDIS, clock_disable);
1583 }
1584
1585
1586 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
1587 /*                                              DIMM-DEDEPENDENT CONFIGURATION FUNCTIONS                                  */
1588 /**********************************************************************************/
1589
1590 //----------------------------------------------------------------------------------
1591 // Function:            RAM_RESET_DDR_PTR
1592 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1593 //                                              SMBus addresses of DIMM slots on the mainboard
1594 // Return Value:        None
1595 // Description:         DDR Receive FIFO RE-Sync (?)
1596 //
1597 static void RAM_RESET_DDR_PTR(void)
1598 {
1599         uint8_t byte;
1600         byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88);
1601         byte |= (1 << 4);
1602         pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte);
1603
1604         byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88);
1605         byte &= ~(1 << 4);
1606         pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte);
1607 }
1608
1609 //----------------------------------------------------------------------------------
1610 // Function:            ram_set_d0f0_regs
1611 // Parameters:          None
1612 // Return Value:        None
1613 // Description:         Set E7501 registers that are either independent of DIMM specifics,
1614 //                                      or establish default settings that will be overridden when we
1615 //                                      learn the specifics.
1616 //                                      This sets PCI configuration registers to known good values based
1617 //                                      on the table 'constant_register_values', which are a triple of
1618 //                                      configuration register offset, mask, and bits to set.
1619 //
1620 static void ram_set_d0f0_regs(void)
1621 {
1622         int i;
1623         int num_values = ARRAY_SIZE(constant_register_values);
1624
1625         ASSERT((num_values % 3) == 0);          // Bad table?
1626
1627     for(i = 0; i < num_values; i += 3) {
1628
1629                 uint32_t register_offset = constant_register_values[i];
1630                 uint32_t bits_to_mask = constant_register_values[i+1];
1631                 uint32_t bits_to_set = constant_register_values[i+2];
1632                 uint32_t register_value;
1633
1634                 // It's theoretically possible to set values for something other than D0:F0,
1635                 // but it's not typically done here
1636                 ASSERT(!(register_offset & 0xFFFFFF00));
1637
1638                 // bits_to_mask and bits_to_set should not reference the same bits
1639                 // Again, not strictly an error, but flagged as a potential bug
1640                 ASSERT((bits_to_mask & bits_to_set) == 0);
1641
1642                 register_value = pci_read_config32(PCI_DEV(0, 0, 0), register_offset);
1643         register_value &= bits_to_mask;
1644         register_value |= bits_to_set;
1645
1646         pci_write_config32(PCI_DEV(0, 0, 0), register_offset, register_value);
1647     }
1648 }
1649
1650 //----------------------------------------------------------------------------------
1651 // Function:            write_8dwords
1652 // Parameters:          src_addr
1653 //                                      dst_addr
1654 // Return Value:        None
1655 // Description:         Copy 64 bytes from one location to another.
1656 //
1657 static void write_8dwords(uint32_t* src_addr, uint32_t dst_addr)
1658 {
1659         int i;
1660         for (i=0; i<8; i++) {
1661                 write32(dst_addr, *src_addr);
1662                 src_addr++;
1663                 dst_addr += sizeof(uint32_t);
1664         }
1665 }
1666
1667 //----------------------------------------------------------------------------------
1668 // Function:            ram_set_rcomp_regs
1669 // Parameters:          None
1670 // Return Value:        None
1671 // Description:         Set the E7501's (undocumented) RCOMP registers.
1672 //                                      Per the 855PM datasheet and IXP2800 HW Initialization Reference
1673 //                                      Manual, RCOMP registers appear to affect drive strength,
1674 //                                      pullup/pulldown offset, and slew rate of various signal groups.
1675 //                                      Comments below are conjecture based on apparent similarity
1676 //                                      between the E7501 and these two chips.
1677 //
1678 static void ram_set_rcomp_regs(void)
1679 {
1680         uint32_t dword;
1681         uint8_t maybe_strength_control;
1682
1683         RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
1684
1685         /*enable access to the rcomp bar*/
1686         dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
1687     dword |= (1<<22);
1688     pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword);
1689
1690
1691         // Set the RCOMP MMIO base address
1692     pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO);
1693
1694         // Block RCOMP updates while we configure the registers
1695         dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
1696         dword |= (1<<9);
1697         write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1698
1699
1700         /* Begin to write the RCOMP registers */
1701
1702         // Set CMD and DQ/DQS strength to 2x (?)
1703         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0x88;
1704         maybe_strength_control |= 0x44;
1705         write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control);
1706
1707         write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x80);
1708         write16(RCOMP_MMIO + 0x42, 0);
1709
1710         write_8dwords(maybe_1x_slew_table, RCOMP_MMIO + 0x60);
1711
1712         // NOTE: some factory BIOS set 0x9088 here. Seems to work either way.
1713         write16(RCOMP_MMIO + 0x40, 0);
1714
1715
1716         // Set RCVEnOut# strength to 2x (?)
1717         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_RCVENSTR) & 0xF8;
1718         maybe_strength_control |= 4;
1719         write8(RCOMP_MMIO + MAYBE_RCVENSTR, maybe_strength_control);
1720
1721         write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x1c0);
1722         write16(RCOMP_MMIO + 0x50, 0);
1723
1724         // Set CS# strength for x4 SDRAM to 2x (?)
1725         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0xF8;
1726         maybe_strength_control |= 4;
1727         write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control);
1728
1729         write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x140);
1730         write16(RCOMP_MMIO + 0x48, 0);
1731
1732         // Set CKE strength for x4 SDRAM to 2x (?)
1733         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0xF8;
1734         maybe_strength_control |= 4;
1735         write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control);
1736
1737         write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xa0);
1738         write16(RCOMP_MMIO + 0x44, 0);
1739
1740         // Set CK strength for x4 SDRAM to 1x (?)
1741         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0xF8;
1742         maybe_strength_control |= 1;
1743         write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control);
1744
1745         write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x180);
1746         write16(RCOMP_MMIO + 0x4c, 0);
1747
1748         write8(RCOMP_MMIO + 0x2c, 0xff);
1749
1750
1751         // Set the digital filter length to 8 (?)
1752         dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
1753
1754         // NOTE: Some factory BIOS don't do this.
1755         //               Doesn't seem to matter either way.
1756         dword &= ~2;
1757
1758         dword |= 1;
1759         write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1760
1761         /* Wait 40 usec */
1762         SLOW_DOWN_IO;
1763
1764         /* unblock updates */
1765         dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
1766         dword &= ~(1<<9);
1767         write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1768
1769         // Force a RCOMP measurement cycle?
1770         dword |= (1<<8);
1771         write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1772         dword &= ~(1<<8);
1773         write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1774
1775         /* Wait 40 usec */
1776         SLOW_DOWN_IO;
1777
1778         /*disable access to the rcomp bar */
1779         dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST);
1780         dword &= ~(1<<22);
1781         pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword);
1782
1783 }
1784
1785 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
1786 /*                                      DIMM-INDEPENDENT CONFIGURATION FUNCTIONS                                          */
1787 /**********************************************************************************/
1788
1789 //----------------------------------------------------------------------------------
1790 // Function:            sdram_enable
1791 // Parameters:          controllers - not used
1792 //                                      ctrl - PCI addresses of memory controller functions, and
1793 //                                              SMBus addresses of DIMM slots on the mainboard
1794 // Return Value:        None
1795 // Description:         Go through the JEDEC initialization sequence for all DIMMs,
1796 //                                      then enable refresh and initialize ECC and memory to zero.
1797 //                                      Upon exit, SDRAM is up and running.
1798 //
1799 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
1800 {
1801         uint8_t dimm_mask = pci_read_config16(PCI_DEV(0, 0, 0), SKPD);
1802         uint32_t dram_controller_mode;
1803
1804         if (dimm_mask == 0)
1805                 return;
1806
1807         /* 1 & 2 Power up and start clocks */
1808         RAM_DEBUG_MESSAGE("Ram Enable 1\n");
1809         RAM_DEBUG_MESSAGE("Ram Enable 2\n");
1810
1811         /* A 200us delay is needed */
1812
1813         DO_DELAY
1814         EXTRA_DELAY
1815
1816         /* 3. Apply NOP */
1817         RAM_DEBUG_MESSAGE("Ram Enable 3\n");
1818         do_ram_command(RAM_COMMAND_NOP, 0);
1819         EXTRA_DELAY
1820
1821         /* 4 Precharge all */
1822         RAM_DEBUG_MESSAGE("Ram Enable 4\n");
1823         do_ram_command(RAM_COMMAND_PRECHARGE, 0);
1824         EXTRA_DELAY
1825
1826         /* wait until the all banks idle state... */
1827         /* 5. Issue EMRS to enable DLL */
1828         RAM_DEBUG_MESSAGE("Ram Enable 5\n");
1829         do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL);
1830         EXTRA_DELAY
1831
1832         /* 6. Reset DLL */
1833         RAM_DEBUG_MESSAGE("Ram Enable 6\n");
1834         set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET);
1835         EXTRA_DELAY
1836
1837         /* Ensure a 200us delay between the DLL reset in step 6 and the final
1838          * mode register set in step 9.
1839          * Infineon needs this before any other command is sent to the ram.
1840          */
1841         DO_DELAY
1842         EXTRA_DELAY
1843
1844         /* 7 Precharge all */
1845         RAM_DEBUG_MESSAGE("Ram Enable 7\n");
1846         do_ram_command(RAM_COMMAND_PRECHARGE, 0);
1847         EXTRA_DELAY
1848
1849         /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
1850         RAM_DEBUG_MESSAGE("Ram Enable 8\n");
1851         do_ram_command(RAM_COMMAND_CBR, 0);
1852         EXTRA_DELAY
1853         do_ram_command(RAM_COMMAND_CBR, 0);
1854         EXTRA_DELAY
1855         /* And for good luck 6 more CBRs */
1856         do_ram_command(RAM_COMMAND_CBR, 0);
1857         EXTRA_DELAY
1858         do_ram_command(RAM_COMMAND_CBR, 0);
1859         EXTRA_DELAY
1860         do_ram_command(RAM_COMMAND_CBR, 0);
1861         EXTRA_DELAY
1862         do_ram_command(RAM_COMMAND_CBR, 0);
1863         EXTRA_DELAY
1864         do_ram_command(RAM_COMMAND_CBR, 0);
1865         EXTRA_DELAY
1866         do_ram_command(RAM_COMMAND_CBR, 0);
1867         EXTRA_DELAY
1868
1869         /* 9 mode register set */
1870         RAM_DEBUG_MESSAGE("Ram Enable 9\n");
1871         set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL);
1872         EXTRA_DELAY
1873
1874         /* 10 DDR Receive FIFO RE-Sync */
1875         RAM_DEBUG_MESSAGE("Ram Enable 10\n");
1876         RAM_RESET_DDR_PTR();
1877         EXTRA_DELAY
1878
1879         /* 11 normal operation */
1880         RAM_DEBUG_MESSAGE("Ram Enable 11\n");
1881         do_ram_command(RAM_COMMAND_NORMAL, 0);
1882         EXTRA_DELAY
1883
1884         // Reconfigure the row boundaries and Top of Low Memory
1885         // to match the true size of the DIMMs
1886         configure_e7501_ram_addresses(ctrl, dimm_mask);
1887
1888     /* Finally enable refresh */
1889         dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
1890         dram_controller_mode |= (1 << 29);
1891         pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
1892         EXTRA_DELAY
1893
1894         initialize_ecc();
1895
1896         dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); /* FCS_EN */
1897         dram_controller_mode |= (1<<17);                // NOTE: undocumented reserved bit
1898         pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
1899
1900         RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n");
1901         DUMPNORTH();
1902
1903 //      verify_ram();
1904 }
1905
1906 //----------------------------------------------------------------------------------
1907 // Function:            sdram_set_spd_registers
1908 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1909 //                                              SMBus addresses of DIMM slots on the mainboard
1910 // Return Value:        None
1911 // Description:         Configure SDRAM controller parameters that depend on
1912 //                                      characteristics of the DIMMs installed in the system. These
1913 //                                      characteristics are read from the DIMMs via the standard Serial
1914 //                                      Presence Detect (SPD) interface.
1915 //
1916 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
1917 {
1918         uint8_t dimm_mask;
1919
1920         RAM_DEBUG_MESSAGE("Reading SPD data...\n");
1921
1922    //activate_spd_rom(ctrl);    Not necessary for this chipset
1923
1924     dimm_mask = spd_get_supported_dimms(ctrl);
1925
1926         if (dimm_mask == 0) {
1927                 print_debug("No usable memory for this controller\n");
1928     } else {
1929
1930                 enable_e7501_clocks(dimm_mask);
1931
1932                 RAM_DEBUG_MESSAGE("setting based on SPD data...\n");
1933
1934                 configure_e7501_row_attributes(ctrl, dimm_mask);
1935                 configure_e7501_dram_controller_mode(ctrl, dimm_mask);
1936                 configure_e7501_cas_latency(ctrl, dimm_mask);
1937                 RAM_RESET_DDR_PTR();
1938
1939                 configure_e7501_dram_timing(ctrl, dimm_mask);
1940                 DO_DELAY
1941                 RAM_DEBUG_MESSAGE("done\n");
1942         }
1943
1944         // NOTE: configure_e7501_ram_addresses() is NOT called here.
1945         //               We want to keep the default 64 MB/row mapping until sdram_enable() is called,
1946         //               even though the default mapping is almost certainly incorrect.
1947         //               The default mapping makes it easy to initialize all of the DIMMs
1948         //               even if the total system memory is > 4 GB.
1949         //
1950         //               Save the dimm_mask for when sdram_enable is called, so it can call
1951         //               configure_e7501_ram_addresses() without having to regenerate the bitmask
1952         //               of usable DIMMs.
1953         pci_write_config16(PCI_DEV(0, 0, 0), SKPD, dimm_mask);
1954 }
1955
1956 //----------------------------------------------------------------------------------
1957 // Function:            sdram_set_registers
1958 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1959 //                                              SMBus addresses of DIMM slots on the mainboard
1960 // Return Value:        None
1961 // Description:         Do basic ram setup that does NOT depend on serial presence detect
1962 //                                      information (i.e. independent of DIMM specifics).
1963 //
1964 static void sdram_set_registers(const struct mem_controller *ctrl)
1965 {
1966         RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n");
1967         DUMPNORTH();
1968
1969         ram_set_rcomp_regs();
1970     ram_set_d0f0_regs();
1971 }
1972
1973 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
1974 /*                                                                      PUBLIC INTERFACE                                                          */
1975 /**********************************************************************************/