src/northbridge/intel/e7501/raminit.c

   1 /* This was originally for the e7500, modified for e7501
   2  * The primary differences are that 7501 apparently can
   3  * support single channel RAM (i haven't tested),
   4  * CAS1.5 is no longer supported, The ECC scrubber
   5  * now supports a mode to zero RAM and init ECC in one step
   6  * and the undocumented registers at 0x80 require new
   7  * (undocumented) values determined by guesswork and
   8  * comparison w/ OEM BIOS values.
   9  * Steven James 02/06/2003
  10  */
  11
  12 /* converted to C 6/2004 yhlu */
  13
  14 #include <assert.h>
  15 #include <spd.h>
  16 #include <sdram_mode.h>
  17 #include <stdlib.h>
  18 #include "e7501.h"
  19
  20 // Uncomment this to enable run-time checking of DIMM parameters
  21 // for dual-channel operation
  22 // Unfortunately the code seems to chew up several K of space.
  23 //#define VALIDATE_DIMM_COMPATIBILITY
  24
  25 // Uncomment this to enable local debugging messages
  26 //#define DEBUG_RAM_CONFIG
  27
  28 #if defined(DEBUG_RAM_CONFIG)
  29 #define RAM_DEBUG_MESSAGE(x)    print_debug(x)
  30 #define RAM_DEBUG_HEX32(x)              print_debug_hex32(x)
  31 #define RAM_DEBUG_HEX8(x)               print_debug_hex8(x)
  32 #define DUMPNORTH()                             dump_pci_device(PCI_DEV(0, 0, 0))
  33 #else
  34 #define RAM_DEBUG_MESSAGE(x)
  35 #define RAM_DEBUG_HEX32(x)
  36 #define RAM_DEBUG_HEX8(x)
  37 #define DUMPNORTH()
  38 #endif
  39
  40 #define E7501_SDRAM_MODE        (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4)
  41 #define SPD_ERROR                       "Error reading SPD info\r\n"
  42
  43 // NOTE: This used to be 0x100000.
  44 //               That doesn't work on systems where A20M# is asserted, because
  45 //               attempts to access 0x1000NN end up accessing 0x0000NN.
  46 #define RCOMP_MMIO 0x200000
  47
  48 struct dimm_size {
  49         unsigned long side1;
  50         unsigned long side2;
  51 };
  52
  53 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
  54 /*                                                                      DEFINITIONS                                                                       */
  55 /**********************************************************************************/
  56
  57 static const uint32_t refresh_frequency[]= {
  58         /* Relative frequency (array value) of each E7501 Refresh Mode Select
  59          * (RMS) value (array index)
  60          * 0 == least frequent refresh (longest interval between refreshes)
  61          * [0] disabled  -> 0
  62          * [1] 15.6 usec -> 2
  63          * [2]  7.8 usec -> 3
  64          * [3] 64   usec -> 1
  65          * [4] reserved  -> 0
  66          * [5] reserved  -> 0
  67          * [6] reserved  -> 0
  68          * [7] 64 clocks -> 4
  69          */
  70         0, 2, 3, 1, 0, 0, 0, 4 };
  71
  72 static const uint32_t refresh_rate_map[] = {
  73         /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode
  74          * Select values (array value)
  75          * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0
  76          * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and
  77          * 64 clock (481 ns) (7) refresh.
  78          * [0] ==  15.625 us -> 15.6 us
  79          * [1] ==   3.9   us -> 481  ns
  80          * [2] ==   7.8   us ->  7.8 us
  81          * [3] ==  31.3   us -> 15.6 us
  82          * [4] ==  62.5   us -> 15.6 us
  83          * [5] == 125     us -> 64   us
  84          */
  85         1, 7, 2, 1, 1, 3
  86 };
  87 #define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1)
  88
  89
  90 // SPD parameters that must match for dual-channel operation
  91 static const uint8_t dual_channel_parameters[] = {
  92         SPD_MEMORY_TYPE,
  93         SPD_MODULE_VOLTAGE,
  94         SPD_NUM_COLUMNS,
  95         SPD_NUM_ROWS,
  96         SPD_NUM_DIMM_BANKS,
  97         SPD_PRIMARY_SDRAM_WIDTH,
  98         SPD_NUM_BANKS_PER_SDRAM
  99 };
 100
 101         /*
 102          * Table:       constant_register_values
 103          */
 104 static const long constant_register_values[] = {
 105         /* SVID - Subsystem Vendor Identification Register
 106          * 0x2c - 0x2d
 107          * [15:00] Subsytem Vendor ID (Indicates system board vendor)
 108          */
 109         /* SID - Subsystem Identification Register
 110          * 0x2e - 0x2f
 111          * [15:00] Subsystem ID
 112          */
 113          // Not everyone wants to be Super Micro Computer, Inc.
 114          // The mainboard should set this if desired.
 115          // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16),
 116
 117         /* Undocumented
 118          * (DRAM Read Timing Control, if similar to 855PM?)
 119          * 0x80 - 0x81
 120          * This register has something to do with CAS latencies,
 121          * possibily this is the real chipset control.
 122          * At 0x00 CAS latency 1.5 works.
 123          * At 0x06 CAS latency 2.5 works.
 124          * At 0x01 CAS latency 2.0 works.
 125          */
 126         /* This is still undocumented in e7501, but with different values
 127          * CAS 2.0 values taken from Intel BIOS settings, others are a guess
 128          * and may be terribly wrong. Old values preserved as comments until I
 129          * figure this out for sure.
 130          * e7501 docs claim that CAS1.5 is unsupported, so it may or may not
 131          * work at all.
 132          * Steven James 02/06/2003
 133          */
 134     /* NOTE: values now configured in configure_e7501_cas_latency() based
 135          *       on SPD info and total number of DIMMs (per Intel)
 136          */
 137
 138         /* FDHC - Fixed DRAM Hole Control
 139          * 0x58
 140          * [7:7] Hole_Enable
 141          *       0 == No memory Hole
 142          *       1 == Memory Hole from 15MB to 16MB
 143          * [6:0] Reserved
 144          *
 145          * PAM - Programmable Attribute Map
 146          * 0x59 [1:0] Reserved
 147          * 0x59 [5:4] 0xF0000 - 0xFFFFF
 148          * 0x5A [1:0] 0xC0000 - 0xC3FFF
 149          * 0x5A [5:4] 0xC4000 - 0xC7FFF
 150          * 0x5B [1:0] 0xC8000 - 0xCBFFF
 151          * 0x5B [5:4] 0xCC000 - 0xCFFFF
 152          * 0x5C [1:0] 0xD0000 - 0xD3FFF
 153          * 0x5C [5:4] 0xD4000 - 0xD7FFF
 154          * 0x5D [1:0] 0xD8000 - 0xDBFFF
 155          * 0x5D [5:4] 0xDC000 - 0xDFFFF
 156          * 0x5E [1:0] 0xE0000 - 0xE3FFF
 157          * 0x5E [5:4] 0xE4000 - 0xE7FFF
 158          * 0x5F [1:0] 0xE8000 - 0xEBFFF
 159          * 0x5F [5:4] 0xEC000 - 0xEFFFF
 160          *       00 == DRAM Disabled (All Access go to memory mapped I/O space)
 161          *       01 == Read Only (Reads to DRAM, Writes to memory mapped I/O space)
 162          *       10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space)
 163          *       11 == Normal (All Access go to DRAM)
 164          */
 165
 166         // Map all legacy ranges to DRAM
 167         0x58, 0xcccccf7f, (0x00 << 0) | (0x30 << 8) | (0x33 << 16) | (0x33 << 24),
 168         0x5C, 0xcccccccc, (0x33 << 0) | (0x33 << 8) | (0x33 << 16) | (0x33 << 24),
 169
 170         /* DRB - DRAM Row Boundary Registers
 171          * 0x60 - 0x6F
 172          *     An array of 8 byte registers, which hold the ending
 173          *     memory address assigned  to each pair of DIMMS, in 64MB
 174          *     granularity.
 175          */
 176         // Conservatively say each row has 64MB of ram, we will fix this up later
 177         // NOTE: These defaults allow us to prime all of the DIMMs on the board
 178         //               without jumping through 36-bit adddressing hoops, even if the
 179         //               total memory is > 4 GB. Changing these values may break do_ram_command()!
 180         0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24),
 181         0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24),
 182
 183         /* DRA - DRAM Row Attribute Register
 184          * 0x70 Row 0,1
 185          * 0x71 Row 2,3
 186          * 0x72 Row 4,5
 187          * 0x73 Row 6,7
 188          * [7:7] Device width for Odd numbered rows
 189          *       0 == 8 bits wide x8
 190          *       1 == 4 bits wide x4
 191          * [6:4] Row Attributes for Odd numbered rows
 192          *       010 == 8KB (for dual-channel)
 193          *       011 == 16KB (for dual-channel)
 194          *       100 == 32KB (for dual-channel)
 195          *       101 == 64KB (for dual-channel)
 196          *       Others == Reserved
 197          * [3:3] Device width for Even numbered rows
 198          *       0 == 8 bits wide x8
 199          *       1 == 4 bits wide x4
 200          * [2:0] Row Attributes for Even numbered rows
 201          *       010 == 8KB (for dual-channel)
 202          *       011 == 16KB (for dual-channel)
 203          *       100 == 32KB (for dual-channel)
 204          *       101 == 64KB (This page size appears broken)
 205          *       Others == Reserved
 206          */
 207          // NOTE: overridden by configure_e7501_row_attributes(), later
 208         0x70, 0x00000000, 0,
 209
 210         /* DRT - DRAM Timing Register
 211          * 0x78
 212          * [31:30] Reserved
 213          * [29:29] Back to Back Write-Read Turn Around
 214          *         0 == 3 clocks between WR-RD commands
 215          *         1 == 2 clocks between WR-RD commands
 216          * [28:28] Back to Back Read-Write Turn Around
 217          *         0 == 5 clocks between RD-WR commands
 218          *         1 == 4 clocks between RD-WR commands
 219          * [27:27] Back to Back Read Turn Around
 220          *         0 == 4 clocks between RD commands
 221          *         1 == 3 clocks between RD commands
 222          * [26:24] Read Delay (tRD)
 223          *         000 == 7 clocks
 224          *         001 == 6 clocks
 225          *         010 == 5 clocks
 226          *         Others == Reserved
 227          * [23:19] Reserved
 228          * [18:16] DRAM idle timer
 229          *      000 == infinite
 230          *      011 == 16 dram clocks
 231          *      001 == 0 clocks
 232          * [15:11] Reserved
 233          * [10:09] Active to Precharge (tRAS)
 234          *         00 == 7 clocks
 235          *         01 == 6 clocks
 236          *         10 == 5 clocks
 237          *         11 == Reserved
 238          * [08:06] Reserved
 239          * [05:04] Cas Latency (tCL)
 240          *         00 == 2.5 Clocks
 241          *         01 == 2.0 Clocks
 242          *         10 == Reserved (was 1.5 Clocks for E7500)
 243          *         11 == Reserved
 244          * [03:03] Write Ras# to Cas# Delay (tRCD)
 245          *         0 == 3 DRAM Clocks
 246          *         1 == 2 DRAM Clocks
 247          * [02:01] Read RAS# to CAS# Delay (tRCD)
 248          *         00 == reserved
 249          *         01 == reserved
 250          *         10 == 3 DRAM Clocks
 251          *         11 == 2 DRAM Clocks
 252          * [00:00] DRAM RAS# to Precharge (tRP)
 253          *         0 == 3 DRAM Clocks
 254          *         1 == 2 DRAM Clocks
 255          */
 256
 257          // Some earlier settings:
 258         /* Most aggressive settings possible */
 259 //      0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|CAS_LATENCY|(1<<3)|(1<<1)|(1<<0),
 260 //      0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0),
 261 //      0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0),
 262
 263         // The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and
 264         // Back-to-Back Write-Read Turnaround. All others are configured based on SPD.
 265         0x78, 0xD7F8FFFF, (1<<29)|(1<<27)|(1<<16),
 266
 267         /* FIXME why was I attempting to set a reserved bit? */
 268         /* 0x0100040f */
 269
 270         /* DRC - DRAM Contoller Mode Register
 271          * 0x7c
 272          * [31:30] Reserved
 273          * [29:29] Initialization Complete
 274          *         0 == Not Complete
 275          *         1 == Complete
 276          * [28:23] Reserved
 277          * [22:22]         Channels
 278          *              0 == Single channel
 279          *              1 == Dual Channel
 280          * [21:20] DRAM Data Integrity Mode
 281          *         00 == Disabled, no ECC
 282          *         01 == Reserved
 283          *         10 == Error checking, using chip-kill, with correction
 284          *         11 == Reserved
 285          * [19:18] DRB Granularity (Read-Only)
 286          *         00 == 32 MB quantities (single channel mode)
 287          *                 01 == 64 MB quantities (dual-channel mode)
 288          *                 10 == Reserved
 289          *                 11 == Reserved
 290          * [17:17] (Intel Undocumented) should always be set to 1       (SJM: comment inconsistent with current setting, below)
 291          * [16:16] Command Per Clock - Address/Control Assertion Rule (CPC)
 292          *         0 == 2n Rule
 293          *         1 == 1n rule
 294          * [15:11] Reserved
 295          * [10:08] Refresh mode select
 296          *         000 == Refresh disabled
 297          *         001 == Refresh interval 15.6 usec
 298          *         010 == Refresh interval 7.8 usec
 299          *         011 == Refresh interval 64 usec
 300          *         111 == Refresh every 64 clocks (fast refresh)
 301          * [07:07] Reserved
 302          * [06:04] Mode Select (SMS)
 303          *         000 == Reserved (was Self Refresh Mode in E7500)
 304          *         001 == NOP Command
 305          *         010 == All Banks Precharge
 306          *         011 == Mode Register Set
 307          *         100 == Extended Mode Register Set
 308          *         101 == Reserved
 309          *         110 == CBR Refresh
 310          *         111 == Normal Operation
 311          * [03:00] Reserved
 312          */
 313 //      .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8),
 314 //      .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8),
 315 //      .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8),
 316
 317         // Default to dual-channel mode, ECC, 1-clock address/cmd hold
 318         // NOTE: configure_e7501_dram_controller_mode() configures further
 319         0x7c, 0xff8ef8ff, (1<<22)|(2<<20)|(1<<16)|(0<<8),
 320
 321         /* Another Intel undocumented register
 322          * 0x88 - 0x8B
 323          * [31:31]      Purpose unknown
 324          * [26:26]      Master DLL Reset?
 325          *                      0 == Normal operation?
 326          *                      1 == Reset?
 327          * [07:07]      Periodic memory recalibration?
 328          *                      0 == Disabled?
 329          *                      1 == Enabled?
 330          * [04:04]      Receive FIFO RE-Sync?
 331          *                      0 == Normal operation?
 332          *                      1 == Reset?
 333          */
 334          // NOTE: Some factory BIOSs don't do this.
 335          //               Doesn't seem to matter either way.
 336         0x88, 0xffffff00, 0x80,
 337
 338         /* CLOCK_DIS - CK/CK# Disable Register
 339          * 0x8C
 340          * [7:7] DDR Frequency
 341          *               0 == 100 MHz (200 MHz data rate)
 342          *               1 == 133 MHz (266 MHz data rate)
 343          * [6:4] Reserved
 344          * [3:3] CK3
 345          *       0 == Enable
 346          *       1 == Disable
 347          * [2:2] CK2
 348          *       0 == Enable
 349          *       1 == Disable
 350          * [1:1] CK1
 351          *       0 == Enable
 352          *       1 == Disable
 353          * [0:0] CK0
 354          *       0 == Enable
 355          *       1 == Disable
 356          */
 357         // NOTE: Disable all clocks initially; turn ones we need back on
 358         //               in enable_e7501_clocks()
 359         0x8C, 0xfffffff0, 0xf,
 360
 361         /* TOLM - Top of Low Memory Register
 362          * 0xC4 - 0xC5
 363          * [15:11] Top of low memory (TOLM)
 364          *         The address below 4GB that should be treated as RAM,
 365          *         on a 128MB granularity.
 366          * [10:00] Reserved
 367          */
 368         /* REMAPBASE - Remap Base Address Regsiter
 369          * 0xC6 - 0xC7
 370          * [15:10] Reserved
 371          * [09:00] Remap Base Address [35:26] 64M aligned
 372          *         Bits [25:0] are assumed to be 0.
 373          */
 374
 375         // NOTE: TOLM overridden by configure_e7501_ram_addresses()
 376         0xc4, 0xfc0007ff, (0x2000 << 0) | (0x3ff << 16),
 377
 378         /* REMAPLIMIT - Remap Limit Address Register
 379          * 0xC8 - 0xC9
 380          * [15:10] Reserved
 381          * [09:00] Remap Limit Address [35:26] 64M aligned
 382          * When remaplimit < remapbase the remap window is disabled.
 383          */
 384         0xc8, 0xfffffc00, 0,
 385
 386         /* DVNP - Device Not Present Register
 387          * 0xE0 - 0xE1
 388          * [15:05] Reserved
 389          * [04:04] Device 4 Function 1 Present
 390          *         0 == Present
 391          *         1 == Absent
 392          * [03:03] Device 3 Function 1 Present
 393          *         0 == Present
 394          *         1 == Absent
 395          * [02:02] Device 2 Function 1 Present
 396          *         0 == Present
 397          *         1 == Absent
 398          * [01:01] Reserved
 399          * [00:00] Device 0 Function 1 Present
 400          *         0 == Present
 401          *         1 == Absent
 402          */
 403
 404         // Enable D0:D1, disable D2:F1, D3:F1, D4:F1
 405         0xe0, 0xffffffe2, (1<<4)|(1<<3)|(1<<2)|(0<<0),
 406
 407         // Undocumented
 408         0xd8, 0xffff9fff, 0x00000000,
 409
 410         // Undocumented - this is pure conjecture based on similarity to 855PM
 411         /* MCHTST - MCH Test Register
 412          * 0xF4 - 0xF7
 413          * [31:31] Purpose unknown
 414          * [30:30] Purpose unknown
 415          * [29:23] Unknown - not used?
 416          * [22:22] System Memory MMR Enable
 417          *         0 == Disable: mem space and BAR at 0x14 are not accessible
 418          *         1 == Enable: mem space and BAR at 0x14 are accessible
 419          * [21:20] Purpose unknown
 420          * [19:02] Unknown - not used?
 421          * [01:01] D6EN (Device #6 enable)
 422          *         0 == Disable
 423          *         1 == Enable
 424          * [00:00] Unknown - not used?
 425          */
 426
 427         0xf4, 0x3f8ffffd, 0x40300002,
 428
 429 #ifdef SUSPICIOUS_LOOKING_CODE
 430         // SJM: Undocumented.
 431         //              This will access D2:F0:0x50, is this correct??
 432         0x1050, 0xffffffcf, 0x00000030,
 433 #endif
 434 };
 435
 436         /* DDR RECOMP tables */
 437
 438 // Slew table for 1x drive?
 439 static const uint32_t maybe_1x_slew_table[] = {
 440         0x44332211, 0xc9776655, 0xffffffff, 0xffffffff,
 441         0x22111111, 0x55444332, 0xfffca876, 0xffffffff,
 442 };
 443
 444 // Slew table for 2x drive?
 445 static const uint32_t maybe_2x_slew_table[] = {
 446         0x00000000, 0x76543210, 0xffffeca8, 0xffffffff,
 447         0x21000000, 0xa8765432, 0xffffffec, 0xffffffff,
 448 };
 449
 450 // Pull Up / Pull Down offset table, if analogous to IXP2800?
 451 static const uint32_t maybe_pull_updown_offset_table[] = {
 452         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 453         0x88888888, 0x88888888, 0x88888888, 0x88888888,
 454 };
 455
 456 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
 457 /*                                                                              TABLES                                                                    */
 458 /**********************************************************************************/
 459 #define SLOW_DOWN_IO inb(0x80);
 460 //#define SLOW_DOWN_IO udelay(40);
 461
 462         /* Estimate that SLOW_DOWN_IO takes about 50&76us*/
 463         /* delay for 200us */
 464
 465 #if 1
 466 static void do_delay(void)
 467 {
 468         int i;
 469         for(i = 0; i < 16; i++) { SLOW_DOWN_IO }
 470 }
 471 #define DO_DELAY do_delay();
 472 #else
 473 #define DO_DELAY \
 474         udelay(200);
 475 #endif
 476
 477 #define EXTRA_DELAY DO_DELAY
 478
 479
 480 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
 481 /*                                                                      DELAY FUNCTIONS                                                           */
 482 /**********************************************************************************/
 483
 484 static void die_on_spd_error(int spd_return_value)
 485 {
 486         if (spd_return_value < 0)
 487                 die("Error reading SPD info\r\n");
 488 }
 489
 490 //----------------------------------------------------------------------------------
 491 // Function:            sdram_spd_get_page_size
 492 // Parameters:          dimm_socket_address - SMBus address of DIMM socket to interrogate
 493 // Return Value:        struct dimm_size - log2(page size) for each side of the DIMM.
 494 // Description:         Calculate the page size for each physical bank of the DIMM:
 495 //                                              log2(page size) = (# columns) + log2(data width)
 496 //
 497 //                                      NOTE: page size is the total number of data bits in a row.
 498 //
 499 static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)
 500 {
 501         uint16_t module_data_width;
 502         int value;
 503         struct dimm_size pgsz;
 504
 505         pgsz.side1 = 0;
 506         pgsz.side2 = 0;
 507
 508         // Side 1
 509         value  = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
 510         if (value < 0) goto hw_err;
 511         pgsz.side1 = value & 0xf;                       // # columns in bank 1
 512
 513         /* Get the module data width and convert it to a power of two */
 514         value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB);
 515         if (value < 0) goto hw_err;
 516         module_data_width = (value & 0xff) << 8;
 517
 518         value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB);
 519         if (value < 0) goto hw_err;
 520         module_data_width |= (value & 0xff);
 521
 522         pgsz.side1 += log2(module_data_width);
 523
 524         /* side two */
 525         value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
 526         if (value < 0) goto hw_err;
 527         if (value > 2)
 528                 die("Bad SPD value\r\n");
 529         if (value == 2) {
 530
 531                 pgsz.side2 = pgsz.side1;                // Assume symmetric banks until we know differently
 532                 value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
 533                 if (value < 0) goto hw_err;
 534                 if ((value & 0xf0) != 0) {
 535                         // Asymmetric banks
 536                         pgsz.side2 -= value & 0xf;              /* Subtract out columns on side 1 */
 537                         pgsz.side2 += (value>>4) & 0xf; /* Add in columns on side 2 */
 538                 }
 539         }
 540
 541         return pgsz;
 542
 543 hw_err:
 544         die(SPD_ERROR);
 545         return pgsz;    // Never reached
 546 }
 547
 548
 549 //----------------------------------------------------------------------------------
 550 // Function:            sdram_spd_get_width
 551 // Parameters:          dimm_socket_address - SMBus address of DIMM socket to interrogate
 552 // Return Value:        dimm_size - width in bits of each DIMM side's DRAMs.
 553 // Description:         Read the width in bits of each DIMM side's DRAMs via SPD.
 554 //                                      (i.e. 4, 8, 16)
 555 //
 556 static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address)
 557 {
 558         int value;
 559         struct dimm_size width;
 560
 561         width.side1 = 0;
 562         width.side2 = 0;
 563
 564         value = spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH);
 565         die_on_spd_error(value);
 566
 567         width.side1 = value & 0x7f;                     // Mask off bank 2 flag
 568
 569         if (value & 0x80) {
 570                 width.side2 = width.side1 << 1; // Bank 2 exists and is double-width
 571         } else {
 572                 // If bank 2 exists, it's the same width as bank 1
 573                 value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
 574                 die_on_spd_error(value);
 575
 576 #ifdef ROMCC_IF_BUG_FIXED
 577                 if (value == 2)
 578                         width.side2 = width.side1;
 579 #else
 580                 switch (value) {
 581                 case 2:
 582                         width.side2 = width.side1;
 583                         break;
 584
 585                 default:
 586                         break;
 587                 }
 588 #endif
 589         }
 590
 591         return width;
 592 }
 593
 594 //----------------------------------------------------------------------------------
 595 // Function:            spd_get_dimm_size
 596 // Parameters:          dimm_socket_address - SMBus address of DIMM socket to interrogate
 597 // Return Value:        dimm_size - log2(number of bits) for each side of the DIMM
 598 // Description:         Calculate the log base 2 size in bits of both DIMM sides.
 599 //                                              log2(# bits) = (# columns) + log2(data width) +
 600 //                                                                         (# rows) + log2(banks per SDRAM)
 601 //
 602 //                                      Note that it might be easier to use SPD byte 31 here, it has the
 603 //                                      DIMM size as a multiple of 4MB.  The way we do it now we can size
 604 //                                      both sides of an asymmetric dimm.
 605 //
 606 static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address)
 607 {
 608    int value;
 609
 610         // Start with log2(page size)
 611     struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address);
 612
 613         if (sz.side1 > 0) {
 614
 615                 value = spd_read_byte(dimm_socket_address, SPD_NUM_ROWS);
 616                 die_on_spd_error(value);
 617
 618         sz.side1 += value & 0xf;
 619
 620                 if (sz.side2 > 0) {
 621
 622                         // Double-sided DIMM
 623                         if (value & 0xF0)
 624                                 sz.side2 += value >> 4;         // Asymmetric
 625                         else
 626                                 sz.side2 += value;                      // Symmetric
 627                 }
 628
 629         value = spd_read_byte(dimm_socket_address, SPD_NUM_BANKS_PER_SDRAM);
 630         die_on_spd_error(value);
 631
 632                 value = log2(value);
 633         sz.side1 += value;
 634                 if (sz.side2 > 0)
 635                 sz.side2 += value;
 636         }
 637
 638         return sz;
 639 }
 640
 641 //----------------------------------------------------------------------------------
 642 // Function:            are_spd_values_equal
 643 // Parameters:          spd_byte_number -
 644 //                                      dimmN_address - SMBus addresses of DIMM sockets to interrogate
 645 // Return Value:        1 if both DIMM sockets report the same value for the specified
 646 //                                              SPD parameter; 0 if the values differed or an error occurred.
 647 // Description:         Determine whether two DIMMs have the same value for a SPD parameter.
 648 //
 649 static uint8_t are_spd_values_equal(uint8_t spd_byte_number, uint16_t dimm0_address,
 650                                                                         uint16_t dimm1_address)
 651 {
 652         uint8_t bEqual = 0;
 653
 654         int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number);
 655         int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number);
 656
 657         if ((dimm0_value >= 0) && (dimm1_value >= 0) && (dimm0_value == dimm1_value))
 658                 bEqual = 1;
 659
 660         return bEqual;
 661 }
 662
 663 //----------------------------------------------------------------------------------
 664 // Function:            spd_get_supported_dimms
 665 // Parameters:          ctrl - PCI addresses of memory controller functions, and
 666 //                                              SMBus addresses of DIMM slots on the mainboard
 667 // Return Value:        uint8_t - a bitmask indicating which of the possible sockets
 668 //                                              for each channel was found to contain a compatible DIMM.
 669 //                                              Bit 0 corresponds to the closest socket for channel 0,
 670 //                                              Bit 1 to the next socket for channel 0,
 671 //                                              ...
 672 //                                              Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0,
 673 //                                              Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1,
 674 //                                              ...
 675 //                                              Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1
 676 // Description:         Scan for compatible DIMMs.
 677 //                                      The code in this module only supports dual-channel operation,
 678 //                                      so we test that compatible DIMMs are paired.
 679 //
 680 static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
 681 {
 682         int i;
 683         uint8_t dimm_mask = 0;
 684
 685         // Have to increase size of dimm_mask if this assertion is violated
 686         ASSERT(MAX_DIMM_SOCKETS_PER_CHANNEL <= 4);
 687
 688         // Find DIMMs we can support on channel 0.
 689         // Then see if the corresponding channel 1 DIMM has the same parameters,
 690         // since we only support dual-channel.
 691
 692     for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
 693
 694         uint16_t channel0_dimm = ctrl->channel0[i];
 695                 uint16_t channel1_dimm = ctrl->channel1[i];
 696                 uint8_t bDualChannel = 1;
 697                 struct dimm_size        page_size;
 698                 struct dimm_size        sdram_width;
 699                 int spd_value;
 700                 int j;
 701
 702                 if (channel0_dimm == 0)
 703                         continue;               // No such socket on this mainboard
 704
 705         if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR)
 706                         continue;
 707
 708 #ifdef VALIDATE_DIMM_COMPATIBILITY
 709                 if (spd_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) != SPD_VOLTAGE_SSTL2)
 710                         continue;               // Unsupported voltage
 711
 712                 // E7501 does not support unregistered DIMMs
 713                 spd_value = spd_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES);
 714                 if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0))
 715                         continue;
 716
 717         // Must support burst = 4 for dual-channel operation on E7501
 718                 // NOTE: for single-channel, burst = 8 is required
 719                 spd_value = spd_read_byte(channel0_dimm, SPD_SUPPORTED_BURST_LENGTHS);
 720                 if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
 721                         continue;
 722
 723         page_size       = sdram_spd_get_page_size(channel0_dimm);
 724                 sdram_width = sdram_spd_get_width(channel0_dimm);
 725
 726                 // Validate DIMM page size
 727                 // The E7501 only supports page sizes of 4, 8, 16, or 32 KB per channel
 728                 // NOTE: 4 KB =  32 Kb = 2^15
 729                 //              32 KB = 262 Kb = 2^18
 730
 731                 if ((page_size.side1 < 15) || (page_size.side1 > 18))
 732                         continue;
 733
 734                 // If DIMM is double-sided, verify side2 page size
 735         if (page_size.side2 != 0) {
 736             if ((page_size.side2 < 15) || (page_size.side2 > 18))
 737                                 continue;
 738                 }
 739
 740                 // Validate SDRAM width
 741                 // The E7501 only supports x4 and x8 devices
 742
 743                 if ((sdram_width.side1 != 4) && (sdram_width.side1 != 8))
 744                         continue;
 745
 746                 // If DIMM is double-sided, verify side2 width
 747         if (sdram_width.side2 != 0) {
 748                         if ((sdram_width.side2 != 4) && (sdram_width.side2 != 8))
 749                                 continue;
 750                 }
 751 #endif
 752                 // Channel 0 DIMM looks compatible.
 753                 // Now see if it is paired with the proper DIMM on channel 1.
 754
 755                 ASSERT(channel1_dimm != 0);             // No such socket on this mainboard??
 756
 757                 // NOTE: unpopulated DIMMs cause read to fail
 758                 spd_value = spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
 759                 if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
 760
 761                         print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
 762                         continue;
 763                 }
 764
 765 #ifdef VALIDATE_DIMM_COMPATIBILITY
 766                 spd_value = spd_read_byte(channel1_dimm, SPD_SUPPORTED_BURST_LENGTHS);
 767                 if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
 768                         continue;
 769
 770                 for (j=0; j<sizeof(dual_channel_parameters); ++j) {
 771                         if (!are_spd_values_equal(dual_channel_parameters[j], channel0_dimm, channel1_dimm)) {
 772
 773                                 bDualChannel = 0;
 774                                 break;
 775                         }
 776                 }
 777 #endif
 778
 779                 // Code around ROMCC bug in optimization of "if" statements
 780 #ifdef ROMCC_IF_BUG_FIXED
 781                 if (bDualChannel) {
 782                         // Made it through all the checks, this DIMM pair is usable
 783                         dimm_mask |= ((1<<i) | (1<<(MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
 784                 }
 785                 else
 786                         print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
 787 #else
 788                 switch (bDualChannel) {
 789                 case 0:
 790                         print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
 791                         break;
 792
 793                 default:
 794                         // Made it through all the checks, this DIMM pair is usable
 795                         dimm_mask |= (1<<i) | (1<<(MAX_DIMM_SOCKETS_PER_CHANNEL + i));
 796                         break;
 797                 }
 798 #endif
 799         }
 800
 801         return dimm_mask;
 802 }
 803
 804 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
 805 /*                                              SPD (SERIAL PRESENCE DETECT) FUNCTIONS                                    */
 806 /**********************************************************************************/
 807
 808 //----------------------------------------------------------------------------------
 809 // Function:            do_ram_command
 810 // Parameters:          ctrl - PCI addresses of memory controller functions, and
 811 //                                              SMBus addresses of DIMM slots on the mainboard
 812 //                                      command - specifies the command to be sent to the DIMMs:
 813 //                                              RAM_COMMAND_NOP                 - No Operation
 814 //                                              RAM_COMMAND_PRECHARGE   - Precharge all banks
 815 //                                              RAM_COMMAND_MRS                 - Load Mode Register
 816 //                                              RAM_COMMAND_EMRS                - Load Extended Mode Register
 817 //                                              RAM_COMMAND_CBR                 - Auto Refresh ("CAS-before-RAS")
 818 //                                              RAM_COMMAND_NORMAL              - Normal operation
 819 //                                      jedec_mode_bits - for mode register set & extended mode register set
 820 //                                              commands, bits 0-12 contain the register value in JEDEC format.
 821 // Return Value:        None
 822 // Description:         Send the specified command to all DIMMs.
 823 //
 824 static void do_ram_command(const struct mem_controller *ctrl, uint8_t command,
 825                                                    uint16_t jedec_mode_bits)
 826 {
 827     int i;
 828         uint32_t dram_controller_mode;
 829         uint8_t dimm_start_64M_multiple = 0;
 830         uint16_t e7501_mode_bits = jedec_mode_bits;
 831
 832         // Configure the RAM command
 833     dram_controller_mode = pci_read_config32(ctrl->d0, DRC);
 834     dram_controller_mode &= 0xFFFFFF8F;
 835     dram_controller_mode |= command;
 836     pci_write_config32(ctrl->d0, DRC, dram_controller_mode);
 837
 838         // RAM_COMMAND_NORMAL is an exception.
 839         // It affects only the memory controller and does not need to be "sent" to the DIMMs.
 840
 841         if (command != RAM_COMMAND_NORMAL) {
 842
 843                 // Send the command to all DIMMs by accessing a memory location within each
 844                 // NOTE: for mode select commands, some of the location address bits
 845                 //               are part of the command
 846
 847                 // Map JEDEC mode bits to E7501
 848                 if (command == RAM_COMMAND_MRS) {
 849                         // Host address lines [15:5] map to DIMM address lines [12:11, 9:1]
 850                         // The E7501 hard-sets DIMM address lines 10 & 0 to zero
 851
 852                         ASSERT(!(jedec_mode_bits & 0x0401));
 853
 854                         e7501_mode_bits = ((jedec_mode_bits & 0x1800) << (15-12)) |             // JEDEC bits 11-12 move to bits 14-15
 855                                                           ((jedec_mode_bits & 0x03FE) << (13-9));               // JEDEC bits 1-9 move to bits 5-13
 856
 857                 } else if (command == RAM_COMMAND_EMRS) {
 858                         // Host address lines [15:3] map to DIMM address lines [12:0]
 859                         e7501_mode_bits = jedec_mode_bits <<= 3;
 860                 } else
 861                         ASSERT(jedec_mode_bits == 0);
 862
 863
 864                 dimm_start_64M_multiple = 0;
 865
 866                 for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
 867
 868                         uint8_t dimm_end_64M_multiple = pci_read_config8(ctrl->d0, DRB_ROW_0 + i);
 869                         if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
 870
 871                                 // This code assumes DRAM row boundaries are all set below 4 GB
 872                                 // NOTE: 0x40 * 64 MB == 4 GB
 873                                 ASSERT(dimm_start_64M_multiple < 0x40);
 874
 875                                 // NOTE: 2^26 == 64 MB
 876
 877                                 uint32_t dimm_start_address = dimm_start_64M_multiple << 26;
 878
 879                                 RAM_DEBUG_MESSAGE("    Sending RAM command to 0x");
 880                                 RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits);
 881                                 RAM_DEBUG_MESSAGE("\r\n");
 882                                 read32(dimm_start_address + e7501_mode_bits);
 883
 884                                 // Set the start of the next DIMM
 885                                 dimm_start_64M_multiple = dimm_end_64M_multiple;
 886                         }
 887                 }
 888         }
 889 }
 890
 891 //----------------------------------------------------------------------------------
 892 // Function:            set_ram_mode
 893 // Parameters:          ctrl - PCI addresses of memory controller functions, and
 894 //                                              SMBus addresses of DIMM slots on the mainboard
 895 //                                      jedec_mode_bits - for mode register set & extended mode register set
 896 //                                              commands, bits 0-12 contain the register value in JEDEC format.
 897 // Return Value:        None
 898 // Description:         Set the mode register of all DIMMs. The proper CAS# latency
 899 //                                      setting is added to the mode bits specified by the caller.
 900 //
 901 static void set_ram_mode(const struct mem_controller *ctrl, uint16_t jedec_mode_bits)
 902 {
 903         ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK));
 904
 905         uint32_t dram_cas_latency = pci_read_config32(ctrl->d0, DRT) & DRT_CAS_MASK;
 906
 907         switch (dram_cas_latency) {
 908         case DRT_CAS_2_5:
 909                 jedec_mode_bits |= SDRAM_CAS_2_5;
 910                 break;
 911
 912         case DRT_CAS_2_0:
 913                 jedec_mode_bits |= SDRAM_CAS_2_0;
 914                 break;
 915
 916         default:
 917                 BUG();
 918                 break;
 919         }
 920
 921         do_ram_command(ctrl, RAM_COMMAND_MRS, jedec_mode_bits);
 922 }
 923
 924 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
 925 /*                                                      SDRAM CONFIGURATION FUNCTIONS                                             */
 926 /**********************************************************************************/
 927
 928 //----------------------------------------------------------------------------------
 929 // Function:            configure_dimm_row_boundaries
 930 // Parameters:          ctrl - PCI addresses of memory controller functions, and
 931 //                                              SMBus addresses of DIMM slots on the mainboard
 932 //                                      dimm_log2_num_bits - log2(number of bits) for each side of the DIMM
 933 //                                      total_dram_64M_multiple - total DRAM in the system (as a
 934 //                                              multiple of 64 MB) for DIMMs < dimm_index
 935 //                                      dimm_index - which DIMM pair is being processed
 936 //                                                               (0..MAX_DIMM_SOCKETS_PER_CHANNEL)
 937 // Return Value:        New multiple of 64 MB total DRAM in the system
 938 // Description:         Configure the E7501's DRAM Row Boundary registers for the memory
 939 //                                      present in the specified DIMM.
 940 //
 941 static uint8_t configure_dimm_row_boundaries(const struct mem_controller *ctrl,
 942                                                                                          struct dimm_size dimm_log2_num_bits,
 943                                                                                          uint8_t total_dram_64M_multiple,
 944                                                                                          unsigned dimm_index)
 945 {
 946         int i;
 947
 948         ASSERT(dimm_index < MAX_DIMM_SOCKETS_PER_CHANNEL);
 949
 950         // DIMM sides must be at least 32 MB
 951         ASSERT(dimm_log2_num_bits.side1 >= 28);
 952         ASSERT((dimm_log2_num_bits.side2 == 0) || (dimm_log2_num_bits.side2 >= 28));
 953
 954         // In dual-channel mode, we are called only once for each pair of DIMMs.
 955         // Each time we process twice the capacity of a single DIMM.
 956
 957         // Convert single DIMM capacity to paired DIMM capacity
 958         // (multiply by two ==> add 1 to log2)
 959         dimm_log2_num_bits.side1++;
 960         if (dimm_log2_num_bits.side2 > 0)
 961                 dimm_log2_num_bits.side2++;
 962
 963         // Add the capacity of side 1 this DIMM pair (as a multiple of 64 MB)
 964         // to the total capacity of the system
 965         // NOTE: 64 MB == 512 Mb, and log2(512 Mb) == 29
 966
 967         total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29));
 968
 969         // Configure the boundary address for the row on side 1
 970         pci_write_config8(ctrl->d0, DRB_ROW_0+(dimm_index<<1), total_dram_64M_multiple);
 971
 972         // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair
 973         // (as a multiple of 64 MB) to the total capacity of the system
 974     if (dimm_log2_num_bits.side2 >= 29)
 975                 total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side2 - 29));
 976
 977         // Configure the boundary address for the row (if any) on side 2
 978     pci_write_config8(ctrl->d0, DRB_ROW_1+(dimm_index<<1), total_dram_64M_multiple);
 979
 980         // Update boundaries for rows subsequent to these.
 981         // These settings will be overridden by a subsequent call if a populated physical slot exists
 982
 983     for(i=dimm_index+1; i<MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
 984                 pci_write_config8(ctrl->d0, DRB_ROW_0+(i<<1), total_dram_64M_multiple);
 985         pci_write_config8(ctrl->d0, DRB_ROW_1+(i<<1), total_dram_64M_multiple);
 986         }
 987
 988     return total_dram_64M_multiple;
 989 }
 990
 991 //----------------------------------------------------------------------------------
 992 // Function:            configure_e7501_ram_addresses
 993 // Parameters:          ctrl - PCI addresses of memory controller functions, and
 994 //                                              SMBus addresses of DIMM slots on the mainboard
 995 //                                      dimm_mask - bitmask of populated DIMMs on the board - see
 996 //                                                              spd_get_supported_dimms()
 997 // Return Value:        None
 998 // Description:         Program the E7501's DRAM row boundary addresses and its Top Of
 999 //                                      Low Memory (TOLM). If necessary, set up a remap window so we
1000 //                                      don't waste DRAM that ordinarily would lie behind addresses
1001 //                                      reserved for memory-mapped I/O.
1002 //
1003 static void configure_e7501_ram_addresses(const struct mem_controller *ctrl,
1004                                                                                   uint8_t dimm_mask)
1005 {
1006         int i;
1007     uint8_t total_dram_64M_multiple = 0;
1008
1009         // Configure the E7501's DRAM row boundaries
1010         // Start by zeroing out the temporary initial configuration
1011         pci_write_config32(ctrl->d0, DRB_ROW_0, 0);
1012         pci_write_config32(ctrl->d0, DRB_ROW_4, 0);
1013
1014         for(i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1015
1016         uint16_t dimm_socket_address = ctrl->channel0[i];
1017                 struct dimm_size sz;
1018
1019         if (!(dimm_mask & (1 << i)))
1020                         continue;               // This DIMM not present
1021
1022         sz = spd_get_dimm_size(dimm_socket_address);
1023
1024         RAM_DEBUG_MESSAGE("dimm size =");
1025         RAM_DEBUG_HEX32(sz.side1);
1026         RAM_DEBUG_MESSAGE(" ");
1027         RAM_DEBUG_HEX32(sz.side2);
1028         RAM_DEBUG_MESSAGE("\r\n");
1029
1030                 if (sz.side1 == 0)
1031                         die("Bad SPD value\r\n");
1032
1033                 total_dram_64M_multiple = configure_dimm_row_boundaries(ctrl, sz, total_dram_64M_multiple, i);
1034         }
1035
1036         // Configure the Top Of Low Memory (TOLM) in the E7501
1037         // This address must be a multiple of 128 MB that is less than 4 GB.
1038         // NOTE: 16-bit wide TOLM register stores only the highest 5 bits of a 32-bit address
1039         //               in the highest 5 bits.
1040
1041         // We set TOLM to the smaller of 0xC0000000 (3 GB) or the total DRAM in the system.
1042         // This reserves addresses from 0xC0000000 - 0xFFFFFFFF for non-DRAM purposes
1043         // such as flash and memory-mapped I/O.
1044
1045         // If there is more than 3 GB of DRAM, we define a remap window which
1046         // makes the DRAM "behind" the reserved region available above the top of physical
1047         // memory.
1048
1049         // NOTE: 0xC0000000 / (64 MB) == 0x30
1050
1051     if (total_dram_64M_multiple <= 0x30)  {
1052
1053                 // <= 3 GB total RAM
1054
1055                 /* I should really adjust all of this in C after I have resources
1056          * to all of the pci devices.
1057          */
1058
1059                 // Round up to 128MB granularity
1060                 // SJM: Is "missing" 64 MB of memory a potential issue? Should this round down?
1061
1062                 uint8_t total_dram_128M_multiple = (total_dram_64M_multiple + 1) >> 1;
1063
1064                 // Convert to high 16 bits of address
1065                 uint16_t top_of_low_memory = total_dram_128M_multiple << 11;
1066
1067         pci_write_config16(ctrl->d0, TOLM, top_of_low_memory);
1068
1069         } else {
1070
1071                 // > 3 GB total RAM
1072
1073                 // Set defaults for > 4 GB DRAM, i.e. remap a 1 GB (= 0x10 * 64 MB) range of memory
1074                 uint16_t remap_base = total_dram_64M_multiple;                          // A[25:0] == 0
1075                 uint16_t remap_limit = total_dram_64M_multiple + 0x10 - 1;      // A[25:0] == 0xF
1076
1077                 // Put TOLM at 3 GB
1078
1079                 pci_write_config16(ctrl->d0, TOLM, 0xc000);
1080
1081                 // Define a remap window to make the RAM that would appear from 3 GB - 4 GB
1082                 // visible just beyond 4 GB or the end of physical memory, whichever is larger
1083                 // NOTE: 16-bit wide REMAP registers store only the highest 10 bits of a 36-bit address,
1084                 //               (i.e. a multiple of 64 MB) in the lowest 10 bits.
1085                 // NOTE: 0x100000000 / (64 MB) == 0x40
1086
1087         if (total_dram_64M_multiple < 0x40) {
1088                         remap_base = 0x40;              // 0x100000000
1089                         remap_limit = 0x40 + (total_dram_64M_multiple - 0x30) - 1;
1090                 }
1091
1092         pci_write_config16(ctrl->d0, REMAPBASE, remap_base);
1093         pci_write_config16(ctrl->d0, REMAPLIMIT, remap_limit);
1094         }
1095 }
1096
1097 //----------------------------------------------------------------------------------
1098 // Function:            initialize_ecc
1099 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1100 //                                              SMBus addresses of DIMM slots on the mainboard
1101 // Return Value:        None
1102 // Description:         If we're configured to use ECC, initialize the SDRAM and
1103 //                                      clear the E7501's ECC error flags.
1104 //
1105 static void initialize_ecc(const struct mem_controller *ctrl)
1106 {
1107         uint32_t dram_controller_mode;
1108
1109         /* Test to see if ECC support is enabled */
1110         dram_controller_mode = pci_read_config32(ctrl->d0, DRC);
1111         dram_controller_mode >>= 20;
1112         dram_controller_mode &= 3;
1113         if (dram_controller_mode == 2)  {
1114
1115                 uint8_t byte;
1116
1117                 RAM_DEBUG_MESSAGE("Initializing ECC state...\r\n");
1118                 /* Initialize ECC bits , use ECC zero mode (new to 7501)*/
1119                 pci_write_config8(ctrl->d0, MCHCFGNS, 0x06);
1120                 pci_write_config8(ctrl->d0, MCHCFGNS, 0x07);
1121
1122                 // Wait for scrub cycle to complete
1123                 do {
1124                         byte = pci_read_config8(ctrl->d0, MCHCFGNS);
1125
1126                 } while ( (byte & 0x08 ) == 0);
1127
1128                 pci_write_config8(ctrl->d0, MCHCFGNS, byte & 0xfc);
1129                 RAM_DEBUG_MESSAGE("ECC state initialized.\r\n");
1130
1131                 /* Clear the ECC error bits */
1132                 pci_write_config8(ctrl->d0f1, DRAM_FERR, 0x03);
1133                 pci_write_config8(ctrl->d0f1, DRAM_NERR, 0x03);
1134
1135                 // Clear DRAM Interface error bits (write-one-clear)
1136                 pci_write_config32(ctrl->d0f1, FERR_GLOBAL, 1<<18);
1137             pci_write_config32(ctrl->d0f1, NERR_GLOBAL, 1<<18);
1138
1139                 // Start normal ECC scrub
1140                 pci_write_config8(ctrl->d0, MCHCFGNS, 5);
1141         }
1142
1143 }
1144
1145 //----------------------------------------------------------------------------------
1146 // Function:            configure_e7501_dram_timing
1147 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1148 //                                              SMBus addresses of DIMM slots on the mainboard
1149 //                                      dimm_mask - bitmask of populated DIMMs on the board - see
1150 //                                                              spd_get_supported_dimms()
1151 // Return Value:        None
1152 // Description:         Program the DRAM Timing register of the E7501 (except for CAS#
1153 //                                      latency, which is assumed to have been programmed already), based
1154 //                                      on the parameters of the various installed DIMMs.
1155 //
1156 static void configure_e7501_dram_timing(const struct mem_controller *ctrl, uint8_t dimm_mask)
1157 {
1158         int i;
1159     uint32_t dram_timing;
1160     int value;
1161         uint8_t slowest_row_precharge = 0;
1162         uint8_t slowest_ras_cas_delay = 0;
1163         uint8_t slowest_active_to_precharge_delay = 0;
1164         uint32_t current_cas_latency = pci_read_config32(ctrl->d0, DRT) & DRT_CAS_MASK;
1165
1166         // CAS# latency must be programmed beforehand
1167         ASSERT((current_cas_latency == DRT_CAS_2_0) || (current_cas_latency == DRT_CAS_2_5));
1168
1169         // Each timing parameter is determined by the slowest DIMM
1170
1171         for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1172
1173         uint16_t dimm_socket_address;
1174
1175                 if (!(dimm_mask & (1 << i)))
1176                         continue;               // This DIMM not present
1177
1178                 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1179                         dimm_socket_address = ctrl->channel0[i];
1180                 else
1181                         dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
1182
1183         value = spd_read_byte(dimm_socket_address, SPD_MIN_ROW_PRECHARGE_TIME);
1184         if (value < 0) goto hw_err;
1185                 if (value > slowest_row_precharge)
1186                         slowest_row_precharge = value;
1187
1188                 value = spd_read_byte(dimm_socket_address, SPD_MIN_RAS_TO_CAS_DELAY);
1189                 if(value < 0 ) goto hw_err;
1190                 if (value > slowest_ras_cas_delay)
1191                         slowest_ras_cas_delay = value;
1192
1193                 value = spd_read_byte(dimm_socket_address, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
1194                 if(value < 0 ) goto hw_err;
1195                 if (value > slowest_active_to_precharge_delay)
1196                         slowest_active_to_precharge_delay = value;
1197         }
1198
1199         // NOTE for timing parameters:
1200         //              At 133 MHz, 1 clock == 7.52 ns
1201
1202     /* Read the initial state */
1203     dram_timing = pci_read_config32(ctrl->d0, DRT);
1204
1205         /* Trp */
1206
1207         // E7501 supports only 2 or 3 clocks for tRP
1208         if (slowest_row_precharge > ((22<<2) | (2<<0)))
1209                 die("unsupported DIMM tRP");                    // > 22.5 ns: 4 or more clocks
1210         else if (slowest_row_precharge > (15<<2))
1211                 dram_timing &= ~(1<<0);                                 // > 15.0 ns: 3 clocks
1212         else
1213                 dram_timing |= (1<<0);                                  // <= 15.0 ns: 2 clocks
1214
1215         /*  Trcd */
1216
1217         // E7501 supports only 2 or 3 clocks for tRCD
1218         // Use the same value for both read & write
1219         dram_timing &= ~((1<<3)|(3<<1));
1220         if (slowest_ras_cas_delay > ((22<<2) | (2<<0)))
1221                 die("unsupported DIMM tRCD");                   // > 22.5 ns: 4 or more clocks
1222         else if (slowest_ras_cas_delay > (15<<2))
1223                 dram_timing |= (2<<1);                                  // > 15.0 ns: 3 clocks
1224         else
1225                 dram_timing |= ((1<<3) | (3<<1));               // <= 15.0 ns: 2 clocks
1226
1227         /* Tras */
1228
1229         // E7501 supports only 5, 6, or 7 clocks for tRAS
1230         // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns
1231         dram_timing &= ~(3<<9);
1232
1233         if (slowest_active_to_precharge_delay > 52)
1234                 die("unsupported DIMM tRAS");                                   // > 52 ns:      8 or more clocks
1235         else if (slowest_active_to_precharge_delay > 45)
1236                 dram_timing |= (0<<9);                                                  // 46-52 ns: 7 clocks
1237         else if (slowest_active_to_precharge_delay > 37)
1238                 dram_timing |= (1<<9);                                                  // 38-45 ns: 6 clocks
1239         else
1240                 dram_timing |= (2<<9);                                                  // < 38 ns:      5 clocks
1241
1242
1243         /* Trd */
1244
1245         /* Set to a 7 clock read delay. This is for 133Mhz
1246         *  with a CAS latency of 2.5  if 2.0 a 6 clock
1247         *  delay is good  */
1248
1249         dram_timing &= ~(7<<24);                // 7 clocks
1250         if (current_cas_latency == DRT_CAS_2_0)
1251                 dram_timing |= (1<<24);         // 6 clocks
1252
1253         /*
1254          * Back to Back Read-Write Turn Around
1255          */
1256         /* Set to a 5 clock back to back read to write turn around.
1257          *  4 is a good delay if the CAS latency is 2.0 */
1258
1259         dram_timing &= ~(1<<28);                // 5 clocks
1260         if (current_cas_latency == DRT_CAS_2_0)
1261                 dram_timing |= (1<<28);         // 4 clocks
1262
1263         pci_write_config32(ctrl->d0, DRT, dram_timing);
1264
1265         return;
1266
1267 hw_err:
1268         die(SPD_ERROR);
1269 }
1270
1271 //----------------------------------------------------------------------------------
1272 // Function:            configure_e7501_cas_latency
1273 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1274 //                                              SMBus addresses of DIMM slots on the mainboard
1275 //                                      dimm_mask - bitmask of populated DIMMs on the board - see
1276 //                                                              spd_get_supported_dimms()
1277 // Return Value:        None
1278 // Description:         Determine the shortest CAS# latency that the E7501 and all DIMMs
1279 //                                      have in common, and program the E7501 to use it.
1280 //
1281 static void configure_e7501_cas_latency(const struct mem_controller *ctrl, uint8_t dimm_mask)
1282 {
1283         int i;
1284         int value;
1285         uint32_t dram_timing;
1286         uint16_t maybe_dram_read_timing;
1287         uint32_t dword;
1288
1289         // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format
1290         // NOTE: E7501 supports only 2.0 and 2.5
1291         uint32_t system_compatible_cas_latencies = SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5;
1292         uint32_t current_cas_latency;
1293         uint32_t dimm_compatible_cas_latencies;
1294
1295         for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1296
1297         uint16_t dimm_socket_address;
1298
1299                 if (!(dimm_mask & (1 << i)))
1300                         continue;               // This DIMM not usable
1301
1302                 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1303                         dimm_socket_address = ctrl->channel0[i];
1304                 else
1305                         dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
1306
1307                 value = spd_read_byte(dimm_socket_address, SPD_ACCEPTABLE_CAS_LATENCIES);
1308                 if (value < 0) goto hw_err;
1309
1310         dimm_compatible_cas_latencies = value & 0x7f;                                           // Start with all supported by DIMM
1311                 current_cas_latency = 1 << log2(dimm_compatible_cas_latencies);         // Max supported by DIMM
1312
1313                 // Can we support the highest CAS# latency?
1314
1315                 value = spd_read_byte(dimm_socket_address, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
1316                 if (value < 0) goto hw_err;
1317
1318                 // NOTE: At 133 MHz, 1 clock == 7.52 ns
1319                 if (value > 0x75) {
1320                         // Our bus is too fast for this CAS# latency
1321                         // Remove it from the bitmask of those supported by the DIMM that are compatible
1322                         dimm_compatible_cas_latencies &= ~current_cas_latency;
1323                 }
1324
1325                 // Can we support the next-highest CAS# latency (max - 0.5)?
1326
1327                 current_cas_latency >>= 1;
1328                 if (current_cas_latency != 0) {
1329                         value = spd_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_2ND);
1330                         if(value < 0 ) goto hw_err;
1331                         if(value > 0x75)
1332                                 dimm_compatible_cas_latencies &= ~current_cas_latency;
1333                 }
1334
1335                 // Can we support the next-highest CAS# latency (max - 1.0)?
1336                 current_cas_latency >>= 1;
1337                 if (current_cas_latency != 0) {
1338                         value = spd_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_3RD);
1339             if(value < 0 ) goto hw_err;
1340             if(value > 0x75)
1341                 dimm_compatible_cas_latencies &= ~current_cas_latency;
1342                 }
1343
1344                 // Restrict the system to CAS# latencies compatible with this DIMM
1345                 system_compatible_cas_latencies &= dimm_compatible_cas_latencies;
1346
1347         /* go to the next DIMM */
1348         }
1349
1350         /* After all of the arduous calculation setup with the fastest
1351          * cas latency I can use.
1352          */
1353
1354         dram_timing = pci_read_config32(ctrl->d0, DRT);
1355         dram_timing &= ~(DRT_CAS_MASK);
1356
1357         maybe_dram_read_timing = pci_read_config16(ctrl->d0, MAYBE_DRDCTL);
1358         maybe_dram_read_timing &= 0xF00C;
1359
1360         if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) {
1361                 dram_timing |= DRT_CAS_2_0;
1362                 maybe_dram_read_timing |= 0xBB1;
1363         }
1364         else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
1365
1366                 uint32_t dram_row_attributes = pci_read_config32(ctrl->d0, DRA);
1367
1368                 dram_timing |= DRT_CAS_2_5;
1369
1370                 // At CAS# 2.5, DRAM Read Timing (if that's what it its) appears to need a slightly
1371                 // different value if all DIMM slots are populated
1372
1373                 if ((dram_row_attributes & 0xff)         && (dram_row_attributes & 0xff00) &&
1374                         (dram_row_attributes & 0xff0000) && (dram_row_attributes & 0xff000000)) {
1375
1376                         // All slots populated
1377                         maybe_dram_read_timing |= 0x0882;
1378                 }
1379                 else {
1380                         // Some unpopulated slots
1381                         maybe_dram_read_timing |= 0x0662;
1382                 }
1383         }
1384         else
1385                 die("No CAS# latencies compatible with all DIMMs!!\r\n");
1386
1387         pci_write_config32(ctrl->d0, DRT, dram_timing);
1388
1389         /* set master DLL reset */
1390         dword = pci_read_config32(ctrl->d0, 0x88);
1391         dword |= (1<<26);
1392         pci_write_config32(ctrl->d0, 0x88, dword);
1393
1394         dword &= 0x0c0007ff;    /* patch try register 88 is undocumented tnz */
1395         dword |= 0xd2109800;
1396
1397         pci_write_config32(ctrl->d0, 0x88, dword);
1398
1399
1400         pci_write_config16(ctrl->d0, MAYBE_DRDCTL, maybe_dram_read_timing);
1401
1402         dword = pci_read_config32(ctrl->d0, 0x88);      /* reset master DLL reset */
1403         dword &= ~(1<<26);
1404         pci_write_config32(ctrl->d0, 0x88, dword);
1405
1406         return;
1407
1408 hw_err:
1409         die(SPD_ERROR);
1410 }
1411
1412 //----------------------------------------------------------------------------------
1413 // Function:            configure_e7501_dram_controller_mode
1414 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1415 //                                              SMBus addresses of DIMM slots on the mainboard
1416 //                                      dimm_mask - bitmask of populated DIMMs on the board - see
1417 //                                                              spd_get_supported_dimms()
1418 // Return Value:        None
1419 // Description:         Configure the refresh interval so that we refresh no more often
1420 //                                      than required by the "most needy" DIMM. Also disable ECC if any
1421 //                                      of the DIMMs don't support it.
1422 //
1423 static void configure_e7501_dram_controller_mode(const struct mem_controller *ctrl,
1424                                                                                                  uint8_t dimm_mask)
1425 {
1426         int i;
1427
1428         // Initial settings
1429     uint32_t controller_mode = pci_read_config32(ctrl->d0, DRC);
1430         uint32_t system_refresh_mode = (controller_mode >> 8) & 7;
1431
1432         // Code below assumes that most aggressive settings are in
1433         // force when we are called, either via E7501 reset defaults
1434         // or by sdram_set_registers():
1435         //      - ECC enabled
1436         //      - No refresh
1437
1438         ASSERT((controller_mode & (3<<20)) == (2<<20));         // ECC
1439         ASSERT(!(controller_mode & (7 << 8)));          // Refresh
1440
1441     /* Walk through _all_ dimms and find the least-common denominator for:
1442          *      - ECC support
1443      *  - refresh rates
1444      */
1445
1446         for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
1447
1448                 uint32_t dimm_refresh_mode;
1449             int value;
1450         uint16_t dimm_socket_address;
1451
1452                 if (!(dimm_mask & (1 << i))) {
1453                         continue;               // This DIMM not usable
1454         }
1455
1456                 if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
1457                         dimm_socket_address = ctrl->channel0[i];
1458                 else
1459                         dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
1460
1461                 // Disable ECC mode if any one of the DIMMs does not support ECC
1462                 // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported.
1463
1464                 value = spd_read_byte(dimm_socket_address, SPD_DIMM_CONFIG_TYPE);
1465         die_on_spd_error(value);
1466                 if (value != ERROR_SCHEME_ECC) {
1467                         controller_mode &= ~(3 << 20);
1468                 }
1469
1470                 value = spd_read_byte(dimm_socket_address, SPD_REFRESH);
1471                 die_on_spd_error(value);
1472                 value &= 0x7f;          // Mask off self-refresh bit
1473                 if(value > MAX_SPD_REFRESH_RATE) {
1474                         print_err("unsupported refresh rate\r\n");
1475                         continue;
1476                 }
1477
1478                 // Get the appropriate E7501 refresh mode for this DIMM
1479                 dimm_refresh_mode = refresh_rate_map[value];
1480                 if (dimm_refresh_mode > 7) {
1481                         print_err("unsupported refresh rate\r\n");
1482                         continue;
1483                 }
1484
1485                 // If this DIMM requires more frequent refresh than others,
1486                 // update the system setting
1487                 if (refresh_frequency[dimm_refresh_mode] > refresh_frequency[system_refresh_mode])
1488                         system_refresh_mode = dimm_refresh_mode;
1489
1490 #ifdef SUSPICIOUS_LOOKING_CODE
1491 // SJM NOTE: This code doesn't look right. SPD values are an order of magnitude smaller
1492 //                       than the clock period of the memory controller. Also, no other northbridge
1493 //                       looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME.
1494
1495                 // Switch to 2 clocks for address/command if required by any one of the DIMMs
1496                 // NOTE: At 133 MHz, 1 clock == 7.52 ns
1497                 value = spd_read_byte(dimm_socket_address, SPD_CMD_SIGNAL_INPUT_HOLD_TIME);
1498                 die_on_spd_error(value);
1499                 if(value >= 0xa0) {             /* At 133MHz this constant should be 0x75 */
1500                         controller_mode &= ~(1<<16);    /* Use two clock cyles instead of one */
1501                 }
1502 #endif
1503
1504         /* go to the next DIMM */
1505         }
1506
1507         controller_mode |= (system_refresh_mode << 8);
1508
1509         // Configure the E7501
1510         pci_write_config32(ctrl->d0, DRC, controller_mode);
1511 }
1512
1513 //----------------------------------------------------------------------------------
1514 // Function:            configure_e7501_row_attributes
1515 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1516 //                                              SMBus addresses of DIMM slots on the mainboard
1517 //                                      dimm_mask - bitmask of populated DIMMs on the board - see
1518 //                                                              spd_get_supported_dimms()
1519 // Return Value:        None
1520 // Description:         Configure the E7501's DRAM Row Attributes (DRA) registers
1521 //                                      based on DIMM parameters read via SPD. This tells the controller
1522 //                                      the width of the SDRAM chips on each DIMM side (x4 or x8) and
1523 //                                      the page size of each DIMM side (4, 8, 16, or 32 KB).
1524 //
1525 static void configure_e7501_row_attributes(const struct mem_controller *ctrl,
1526                                                                                    uint8_t dimm_mask)
1527 {
1528         int i;
1529         uint32_t row_attributes = 0;
1530
1531     for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1532
1533         uint16_t dimm_socket_address = ctrl->channel0[i];
1534                 struct dimm_size        page_size;
1535                 struct dimm_size        sdram_width;
1536
1537                 if (!(dimm_mask & (1 << i)))
1538                         continue;               // This DIMM not usable
1539
1540                 // Get the relevant parameters via SPD
1541                 page_size       = sdram_spd_get_page_size(dimm_socket_address);
1542                 sdram_width = sdram_spd_get_width(dimm_socket_address);
1543
1544                 // Update the DRAM Row Attributes.
1545                 // Page size is encoded as log2(page size in bits) - log2(8 Kb)
1546                 // NOTE: 8 Kb = 2^13
1547                 row_attributes |= (page_size.side1 - 13) << (i<<3);                     // Side 1 of each DIMM is an EVEN row
1548
1549                 if (sdram_width.side2 > 0)
1550                         row_attributes |= (page_size.side2 - 13) << ((i<<3) + 4);       // Side 2 is ODD
1551
1552                 // Set x4 flags if appropriate
1553                 if (sdram_width.side1 == 4) {
1554                         row_attributes |= 0x08 << (i<<3);
1555                 }
1556
1557                 if (sdram_width.side2 == 4) {
1558                         row_attributes |= 0x08 << ((i<<3) + 4);
1559         }
1560
1561         /* go to the next DIMM */
1562         }
1563
1564         /* Write the new row attributes register */
1565         pci_write_config32(ctrl->d0, DRA, row_attributes);
1566 }
1567
1568 //----------------------------------------------------------------------------------
1569 // Function:            enable_e7501_clocks
1570 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1571 //                                              SMBus addresses of DIMM slots on the mainboard
1572 //                                      dimm_mask - bitmask of populated DIMMs on the board - see
1573 //                                                              spd_get_supported_dimms()
1574 // Return Value:        None
1575 // Description:         Enable clock signals for populated DIMM sockets and disable them
1576 //                                      for unpopulated sockets (to reduce EMI).
1577 //
1578 static void enable_e7501_clocks(const struct mem_controller *ctrl, uint8_t dimm_mask)
1579 {
1580         int i;
1581         uint8_t clock_disable = pci_read_config8(ctrl->d0, CKDIS);
1582
1583         for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
1584
1585                 uint8_t socket_mask = 1 << i;
1586
1587                 if (dimm_mask & socket_mask)
1588                         clock_disable &= ~socket_mask;  // DIMM present, enable clock
1589                 else
1590                         clock_disable |= socket_mask;   // DIMM absent, disable clock
1591         }
1592
1593         pci_write_config8(ctrl->d0, CKDIS, clock_disable);
1594 }
1595
1596
1597 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
1598 /*                                              DIMM-DEDEPENDENT CONFIGURATION FUNCTIONS                                  */
1599 /**********************************************************************************/
1600
1601 //----------------------------------------------------------------------------------
1602 // Function:            RAM_RESET_DDR_PTR
1603 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1604 //                                              SMBus addresses of DIMM slots on the mainboard
1605 // Return Value:        None
1606 // Description:         DDR Receive FIFO RE-Sync (?)
1607 //
1608 static void RAM_RESET_DDR_PTR(const struct mem_controller *ctrl)
1609 {
1610         uint8_t byte;
1611         byte = pci_read_config8(ctrl->d0, 0x88);
1612         byte |= (1 << 4);
1613         pci_write_config8(ctrl->d0, 0x88, byte);
1614
1615         byte = pci_read_config8(ctrl->d0, 0x88);
1616         byte &= ~(1 << 4);
1617         pci_write_config8(ctrl->d0, 0x88, byte);
1618 }
1619
1620 //----------------------------------------------------------------------------------
1621 // Function:            ram_set_d0f0_regs
1622 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1623 //                                              SMBus addresses of DIMM slots on the mainboard
1624 // Return Value:        None
1625 // Description:         Set E7501 registers that are either independent of DIMM specifics,
1626 //                                      or establish default settings that will be overridden when we
1627 //                                      learn the specifics.
1628 //                                      This sets PCI configuration registers to known good values based
1629 //                                      on the table 'constant_register_values', which are a triple of
1630 //                                      configuration register offset, mask, and bits to set.
1631 //
1632 static void ram_set_d0f0_regs(const struct mem_controller *ctrl)
1633 {
1634         int i;
1635         int num_values = ARRAY_SIZE(constant_register_values);
1636
1637         ASSERT((num_values % 3) == 0);          // Bad table?
1638
1639     for(i = 0; i < num_values; i += 3) {
1640
1641                 uint32_t register_offset = constant_register_values[i];
1642                 uint32_t bits_to_mask = constant_register_values[i+1];
1643                 uint32_t bits_to_set = constant_register_values[i+2];
1644                 uint32_t register_value;
1645
1646                 // It's theoretically possible to set values for something other than D0:F0,
1647                 // but it's not typically done here
1648                 ASSERT(!(register_offset & 0xFFFFFF00));
1649
1650                 // bits_to_mask and bits_to_set should not reference the same bits
1651                 // Again, not strictly an error, but flagged as a potential bug
1652                 ASSERT((bits_to_mask & bits_to_set) == 0);
1653
1654                 register_value = pci_read_config32(ctrl->d0, register_offset);
1655         register_value &= bits_to_mask;
1656         register_value |= bits_to_set;
1657
1658         pci_write_config32(ctrl->d0, register_offset, register_value);
1659     }
1660 }
1661
1662 //----------------------------------------------------------------------------------
1663 // Function:            write_8dwords
1664 // Parameters:          src_addr
1665 //                                      dst_addr
1666 // Return Value:        None
1667 // Description:         Copy 64 bytes from one location to another.
1668 //
1669 static void write_8dwords(uint32_t* src_addr, uint32_t dst_addr)
1670 {
1671         int i;
1672         for (i=0; i<8; i++) {
1673                 write32(dst_addr, *src_addr);
1674                 src_addr++;
1675                 dst_addr += sizeof(uint32_t);
1676         }
1677 }
1678
1679 //----------------------------------------------------------------------------------
1680 // Function:            ram_set_rcomp_regs
1681 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1682 //                                              SMBus addresses of DIMM slots on the mainboard
1683 // Return Value:        None
1684 // Description:         Set the E7501's (undocumented) RCOMP registers.
1685 //                                      Per the 855PM datasheet and IXP2800 HW Initialization Reference
1686 //                                      Manual, RCOMP registers appear to affect drive strength,
1687 //                                      pullup/pulldown offset, and slew rate of various signal groups.
1688 //                                      Comments below are conjecture based on apparent similarity
1689 //                                      between the E7501 and these two chips.
1690 //
1691 static void ram_set_rcomp_regs(const struct mem_controller *ctrl)
1692 {
1693         uint32_t dword;
1694         uint8_t maybe_strength_control;
1695
1696         RAM_DEBUG_MESSAGE("Setting RCOMP registers.\r\n");
1697
1698         /*enable access to the rcomp bar*/
1699         dword = pci_read_config32(ctrl->d0, MAYBE_MCHTST);
1700     dword |= (1<<22);
1701     pci_write_config32(ctrl->d0, MAYBE_MCHTST, dword);
1702
1703
1704         // Set the RCOMP MMIO base address
1705     pci_write_config32(ctrl->d0, MAYBE_SMRBASE, RCOMP_MMIO);
1706
1707         // Block RCOMP updates while we configure the registers
1708         dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
1709         dword |= (1<<9);
1710         write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1711
1712
1713         /* Begin to write the RCOMP registers */
1714
1715         // Set CMD and DQ/DQS strength to 2x (?)
1716         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0x88;
1717         maybe_strength_control |= 0x44;
1718         write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control);
1719
1720         write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x80);
1721         write16(RCOMP_MMIO + 0x42, 0);
1722
1723         write_8dwords(maybe_1x_slew_table, RCOMP_MMIO + 0x60);
1724
1725         // NOTE: some factory BIOS set 0x9088 here. Seems to work either way.
1726         write16(RCOMP_MMIO + 0x40, 0);
1727
1728
1729         // Set RCVEnOut# strength to 2x (?)
1730         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_RCVENSTR) & 0xF8;
1731         maybe_strength_control |= 4;
1732         write8(RCOMP_MMIO + MAYBE_RCVENSTR, maybe_strength_control);
1733
1734         write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x1c0);
1735         write16(RCOMP_MMIO + 0x50, 0);
1736
1737         // Set CS# strength for x4 SDRAM to 2x (?)
1738         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0xF8;
1739         maybe_strength_control |= 4;
1740         write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control);
1741
1742         write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x140);
1743         write16(RCOMP_MMIO + 0x48, 0);
1744
1745         // Set CKE strength for x4 SDRAM to 2x (?)
1746         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0xF8;
1747         maybe_strength_control |= 4;
1748         write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control);
1749
1750         write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xa0);
1751         write16(RCOMP_MMIO + 0x44, 0);
1752
1753         // Set CK strength for x4 SDRAM to 1x (?)
1754         maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0xF8;
1755         maybe_strength_control |= 1;
1756         write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control);
1757
1758         write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x180);
1759         write16(RCOMP_MMIO + 0x4c, 0);
1760
1761         write8(RCOMP_MMIO + 0x2c, 0xff);
1762
1763
1764         // Set the digital filter length to 8 (?)
1765         dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
1766
1767         // NOTE: Some factory BIOS don't do this.
1768         //               Doesn't seem to matter either way.
1769         dword &= ~2;
1770
1771         dword |= 1;
1772         write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1773
1774         /* Wait 40 usec */
1775         SLOW_DOWN_IO;
1776
1777         /* unblock updates */
1778         dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
1779         dword &= ~(1<<9);
1780         write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1781
1782         // Force a RCOMP measurement cycle?
1783         dword |= (1<<8);
1784         write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1785         dword &= ~(1<<8);
1786         write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
1787
1788         /* Wait 40 usec */
1789         SLOW_DOWN_IO;
1790
1791         /*disable access to the rcomp bar */
1792         dword = pci_read_config32(ctrl->d0, MAYBE_MCHTST);
1793         dword &= ~(1<<22);
1794         pci_write_config32(ctrl->d0, MAYBE_MCHTST, dword);
1795
1796 }
1797
1798 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
1799 /*                                      DIMM-INDEPENDENT CONFIGURATION FUNCTIONS                                          */
1800 /**********************************************************************************/
1801
1802 //----------------------------------------------------------------------------------
1803 // Function:            sdram_enable
1804 // Parameters:          controllers - not used
1805 //                                      ctrl - PCI addresses of memory controller functions, and
1806 //                                              SMBus addresses of DIMM slots on the mainboard
1807 // Return Value:        None
1808 // Description:         Go through the JEDEC initialization sequence for all DIMMs,
1809 //                                      then enable refresh and initialize ECC and memory to zero.
1810 //                                      Upon exit, SDRAM is up and running.
1811 //
1812 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
1813 {
1814         uint8_t dimm_mask = pci_read_config16(ctrl->d0, SKPD);
1815         uint32_t dram_controller_mode;
1816
1817         if (dimm_mask == 0)
1818                 return;
1819
1820         /* 1 & 2 Power up and start clocks */
1821         RAM_DEBUG_MESSAGE("Ram Enable 1\r\n");
1822         RAM_DEBUG_MESSAGE("Ram Enable 2\r\n");
1823
1824         /* A 200us delay is needed */
1825
1826         DO_DELAY
1827         EXTRA_DELAY
1828
1829         /* 3. Apply NOP */
1830         RAM_DEBUG_MESSAGE("Ram Enable 3\r\n");
1831         do_ram_command(ctrl, RAM_COMMAND_NOP, 0);
1832         EXTRA_DELAY
1833
1834         /* 4 Precharge all */
1835         RAM_DEBUG_MESSAGE("Ram Enable 4\r\n");
1836         do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0);
1837         EXTRA_DELAY
1838
1839         /* wait until the all banks idle state... */
1840         /* 5. Issue EMRS to enable DLL */
1841         RAM_DEBUG_MESSAGE("Ram Enable 5\r\n");
1842         do_ram_command(ctrl, RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL);
1843         EXTRA_DELAY
1844
1845         /* 6. Reset DLL */
1846         RAM_DEBUG_MESSAGE("Ram Enable 6\r\n");
1847         set_ram_mode(ctrl, E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET);
1848         EXTRA_DELAY
1849
1850         /* Ensure a 200us delay between the DLL reset in step 6 and the final
1851          * mode register set in step 9.
1852          * Infineon needs this before any other command is sent to the ram.
1853          */
1854         DO_DELAY
1855         EXTRA_DELAY
1856
1857         /* 7 Precharge all */
1858         RAM_DEBUG_MESSAGE("Ram Enable 7\r\n");
1859         do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0);
1860         EXTRA_DELAY
1861
1862         /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
1863         RAM_DEBUG_MESSAGE("Ram Enable 8\r\n");
1864         do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
1865         EXTRA_DELAY
1866         do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
1867         EXTRA_DELAY
1868         /* And for good luck 6 more CBRs */
1869         do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
1870         EXTRA_DELAY
1871         do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
1872         EXTRA_DELAY
1873         do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
1874         EXTRA_DELAY
1875         do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
1876         EXTRA_DELAY
1877         do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
1878         EXTRA_DELAY
1879         do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
1880         EXTRA_DELAY
1881
1882         /* 9 mode register set */
1883         RAM_DEBUG_MESSAGE("Ram Enable 9\r\n");
1884         set_ram_mode(ctrl, E7501_SDRAM_MODE | SDRAM_MODE_NORMAL);
1885         EXTRA_DELAY
1886
1887         /* 10 DDR Receive FIFO RE-Sync */
1888         RAM_DEBUG_MESSAGE("Ram Enable 10\r\n");
1889         RAM_RESET_DDR_PTR(ctrl);
1890         EXTRA_DELAY
1891
1892         /* 11 normal operation */
1893         RAM_DEBUG_MESSAGE("Ram Enable 11\r\n");
1894         do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0);
1895         EXTRA_DELAY
1896
1897         // Reconfigure the row boundaries and Top of Low Memory
1898         // to match the true size of the DIMMs
1899         configure_e7501_ram_addresses(ctrl, dimm_mask);
1900
1901     /* Finally enable refresh */
1902         dram_controller_mode = pci_read_config32(ctrl->d0, DRC);
1903         dram_controller_mode |= (1 << 29);
1904         pci_write_config32(ctrl->d0, DRC, dram_controller_mode);
1905         EXTRA_DELAY
1906
1907         initialize_ecc(ctrl);
1908
1909         dram_controller_mode = pci_read_config32(ctrl->d0, DRC); /* FCS_EN */
1910         dram_controller_mode |= (1<<17);                // NOTE: undocumented reserved bit
1911         pci_write_config32(ctrl->d0, DRC, dram_controller_mode);
1912
1913         RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\r\n");
1914         DUMPNORTH();
1915
1916 //      verify_ram();
1917 }
1918
1919 //----------------------------------------------------------------------------------
1920 // Function:            sdram_set_spd_registers
1921 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1922 //                                              SMBus addresses of DIMM slots on the mainboard
1923 // Return Value:        None
1924 // Description:         Configure SDRAM controller parameters that depend on
1925 //                                      characteristics of the DIMMs installed in the system. These
1926 //                                      characteristics are read from the DIMMs via the standard Serial
1927 //                                      Presence Detect (SPD) interface.
1928 //
1929 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
1930 {
1931         uint8_t dimm_mask;
1932
1933         RAM_DEBUG_MESSAGE("Reading SPD data...\r\n");
1934
1935    //activate_spd_rom(ctrl);    Not necessary for this chipset
1936
1937     dimm_mask = spd_get_supported_dimms(ctrl);
1938
1939         if (dimm_mask == 0) {
1940                 print_debug("No usable memory for this controller\r\n");
1941     } else {
1942
1943                 enable_e7501_clocks(ctrl, dimm_mask);
1944
1945                 RAM_DEBUG_MESSAGE("setting based on SPD data...\r\n");
1946
1947                 configure_e7501_row_attributes(ctrl, dimm_mask);
1948                 configure_e7501_dram_controller_mode(ctrl, dimm_mask);
1949                 configure_e7501_cas_latency(ctrl, dimm_mask);
1950                 RAM_RESET_DDR_PTR(ctrl);
1951
1952                 configure_e7501_dram_timing(ctrl, dimm_mask);
1953                 DO_DELAY
1954                 RAM_DEBUG_MESSAGE("done\r\n");
1955         }
1956
1957         // NOTE: configure_e7501_ram_addresses() is NOT called here.
1958         //               We want to keep the default 64 MB/row mapping until sdram_enable() is called,
1959         //               even though the default mapping is almost certainly incorrect.
1960         //               The default mapping makes it easy to initialize all of the DIMMs
1961         //               even if the total system memory is > 4 GB.
1962         //
1963         //               Save the dimm_mask for when sdram_enable is called, so it can call
1964         //               configure_e7501_ram_addresses() without having to regenerate the bitmask
1965         //               of usable DIMMs.
1966         pci_write_config16(ctrl->d0, SKPD, dimm_mask);
1967 }
1968
1969 //----------------------------------------------------------------------------------
1970 // Function:            sdram_set_registers
1971 // Parameters:          ctrl - PCI addresses of memory controller functions, and
1972 //                                              SMBus addresses of DIMM slots on the mainboard
1973 // Return Value:        None
1974 // Description:         Do basic ram setup that does NOT depend on serial presence detect
1975 //                                      information (i.e. independent of DIMM specifics).
1976 //
1977 static void sdram_set_registers(const struct mem_controller *ctrl)
1978 {
1979         RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\r\n");
1980         DUMPNORTH();
1981
1982         ram_set_rcomp_regs(ctrl);
1983     ram_set_d0f0_regs(ctrl);
1984 }
1985
1986 /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
1987 /*                                                                      PUBLIC INTERFACE                                                          */
1988 /**********************************************************************************/