2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <cpu/amd/lxdef.h>
23 #include "southbridge/amd/cs5536/cs5536.h"
25 static const unsigned char NumColAddr[] = {
26 0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,
27 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F
30 static void banner(const char *s)
32 /* This is so ugly. */
33 print_debug("===========================");
35 print_debug("======================================\n");
41 /* this guarantees we flush the UART fifos (if any) and also
42 * ensures that things, in general, keep going so no debug output
49 static void auto_size_dimm(unsigned int dimm)
51 uint32_t dimm_setting;
58 banner("Check present");
59 /* Check that we have a dimm */
60 if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) {
65 /* Field: Module Banks per DIMM */
66 /* EEPROM byte usage: (5) Number of DIMM Banks */
67 spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
68 if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {
69 print_emerg("Number of module banks not compatible\n");
70 post_code(ERROR_BANK_SET);
73 dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
76 /* Field: Banks per SDRAM device */
77 /* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
78 spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
79 if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {
80 print_emerg("Number of device banks not compatible\n");
81 post_code(ERROR_BANK_SET);
84 dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
88 *; EEPROM byte usage: (3) Number of Row Addresses
89 *; (4) Number of Column Addresses
90 *; (5) Number of DIMM Banks
91 *; (31) Module Bank Density
92 *; Size = Module Density * Module Banks
94 if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
95 || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
96 print_emerg("Assymetirc DIMM not compatible\n");
97 post_code(ERROR_UNSUPPORTED_DIMM);
100 banner("SPDBANKDENSITY");
102 dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);
104 dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
105 dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
107 /* Module Density * Module Banks */
108 dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
109 banner("BEFORT CTZ");
110 dimm_size = __builtin_ctz(dimm_size);
111 banner("TEST DIMM SIZE>8");
112 if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */
113 print_emerg("Only support up to 1 GB per DIMM\n");
114 post_code(ERROR_DENSITY_DIMM);
117 dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
121 *; EEPROM byte usage: (4) Number of Column Addresses
122 *; PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM)
124 *; But this really works by magic.
125 *;If ma[12:0] is the memory address pins, and pa[12:0] is the physical column address
126 *;that MC generates, here is how the MC assigns the pa onto the ma pins:
128 *;ma 12 11 10 09 08 07 06 05 04 03 02 01 00
129 *;-------------------------------------------
130 *;pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size)
131 *;pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size)
132 *;pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size)
133 *;pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size)
134 *;pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size)
135 *;pa 14 13 AP 12 11 10 09 08 07 06 05 04 03 (12 col addr bits = 32K page size)
136 *; *AP=autoprecharge bit
138 *;Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
139 *;so lower 3 address bits are dont_cares.So from the table above,
140 *;it's easier to see what the old code is doing: if for example,#col_addr_bits=7(06h),
141 *;it adds 3 to get 10, then does 2^10=1K. Get it?*/
143 spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
144 banner("MAXCOLADDR");
145 if (spd_byte > MAX_COL_ADDR) {
146 print_emerg("DIMM page size not compatible\n");
147 post_code(ERROR_SET_PAGE);
150 banner(">12address test");
152 if (spd_byte > 5) { /* if the value is above 6 it means >12 address lines */
153 spd_byte = 7; /* which means >32k so set to disabled */
155 dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */
157 banner("RDMSR CF07");
158 msr = rdmsr(MC_CF07_DATA);
159 banner("WRMSR CF07");
161 msr.hi &= 0xFFFF0000;
162 msr.hi |= dimm_setting;
164 msr.hi &= 0x0000FFFF;
165 msr.hi |= dimm_setting << 16;
167 wrmsr(MC_CF07_DATA, msr);
171 static void checkDDRMax(void)
173 uint8_t spd_byte0, spd_byte1;
176 /* PC133 identifier */
177 spd_byte0 = spd_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
178 if (spd_byte0 == 0xFF) {
181 spd_byte1 = spd_read_byte(DIMM1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
182 if (spd_byte1 == 0xFF) {
186 /* I don't think you need this check.
187 if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0){
188 print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
189 post_code(POST_PLL_MEM_FAIL);
193 /* Use the slowest DIMM */
194 if (spd_byte0 < spd_byte1) {
195 spd_byte0 = spd_byte1;
198 /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
199 speed = 20000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F));
201 /* current speed > max speed? */
202 if (GeodeLinkSpeed() > speed) {
203 print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
204 post_code(POST_PLL_MEM_FAIL);
209 const uint16_t REF_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */
211 static void set_refresh_rate(void)
213 uint8_t spd_byte0, spd_byte1;
214 uint16_t rate0, rate1;
217 spd_byte0 = spd_read_byte(DIMM0, SPD_REFRESH);
222 rate0 = REF_RATE[spd_byte0];
224 spd_byte1 = spd_read_byte(DIMM1, SPD_REFRESH);
229 rate1 = REF_RATE[spd_byte1];
231 /* Use the faster rate (lowest number) */
236 msr = rdmsr(MC_CF07_DATA);
237 msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16)
238 << CF07_LOWER_REF_INT_SHIFT;
239 wrmsr(MC_CF07_DATA, msr);
242 const uint8_t CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */
244 static void setCAS(void)
246 /*;*****************************************************************************
249 ;* EEPROM byte usage: (18) SDRAM device attributes - CAS latency
250 ;* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5
251 ;* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1
253 ;* The CAS setting is based on the information provided in each DIMMs SPD.
254 ;* The speed at which a DIMM can run is described relative to the slowest
255 ;* CAS the DIMM supports. Each speed for the relative CAS settings is
256 ;* checked that it is within the GeodeLink speed. If it isn't within the GeodeLink
257 ;* speed, the CAS setting is removed from the list of good settings for
258 ;* the DIMM. This is done for both DIMMs and the lists are compared to
259 ;* find the lowest common CAS latency setting. If there are no CAS settings
260 ;* in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.
263 ;* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.
264 ;* Destroys: We really use everything !
265 ;*****************************************************************************/
266 uint16_t glspeed, dimm_speed;
267 uint8_t spd_byte, casmap0, casmap1, casmap_shift;
270 glspeed = GeodeLinkSpeed();
272 /************************** DIMM0 **********************************/
273 casmap0 = spd_read_byte(DIMM0, SPD_ACCEPTABLE_CAS_LATENCIES);
274 if (casmap0 != 0xFF) {
275 /* IF -.5 timing is supported, check -.5 timing > GeodeLink */
276 spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND);
278 /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
279 dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
280 if (dimm_speed >= glspeed) {
281 casmap_shift = 1; /* -.5 is a shift of 1 */
282 /* IF -1 timing is supported, check -1 timing > GeodeLink */
283 spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD);
285 /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
286 dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
287 if (dimm_speed >= glspeed) {
288 casmap_shift = 2; /* -1 is a shift of 2 */
290 } /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */
294 } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */
295 /* set the casmap based on the shift to limit possible CAS settings */
296 spd_byte = 31 - __builtin_clz((uint32_t) casmap0);
297 /* just want bits in the lower byte since we have to cast to a 32 */
298 casmap0 &= 0xFF << (spd_byte - casmap_shift);
299 } else { /* No DIMM */
303 /************************** DIMM1 **********************************/
304 casmap1 = spd_read_byte(DIMM1, SPD_ACCEPTABLE_CAS_LATENCIES);
305 if (casmap1 != 0xFF) {
306 /* IF -.5 timing is supported, check -.5 timing > GeodeLink */
307 spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_2ND);
309 /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
310 dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
311 if (dimm_speed >= glspeed) {
312 casmap_shift = 1; /* -.5 is a shift of 1 */
313 /* IF -1 timing is supported, check -1 timing > GeodeLink */
314 spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_3RD);
316 /* Turn SPD ns time into MHZ. Check what the asm does to this math. */
317 dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
318 if (dimm_speed >= glspeed) {
319 casmap_shift = 2; /* -1 is a shift of 2 */
321 /* note that the -1 result doesn't need to change the available CAS map */
322 } /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */
326 } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */
327 /* set the casmap based on the shift to limit possible CAS settings */
328 spd_byte = 31 - __builtin_clz((uint32_t) casmap1);
329 /* just want bits in the lower byte since we have to cast to a 32 */
330 casmap1 &= 0xFF << (spd_byte - casmap_shift);
331 } else { /* No DIMM */
335 /********************* CAS_LAT MAP COMPARE ***************************/
337 spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap1)];
338 } else if (casmap1 == 0) {
339 spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)];
340 } else if ((casmap0 &= casmap1)) {
341 spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)];
343 print_emerg("DIMM CAS Latencies not compatible\n");
344 post_code(ERROR_DIFF_DIMMS);
348 msr = rdmsr(MC_CF8F_DATA);
349 msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
350 msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;
351 wrmsr(MC_CF8F_DATA, msr);
354 static void set_latencies(void)
356 uint32_t memspeed, dimm_setting;
357 uint8_t spd_byte0, spd_byte1;
360 memspeed = GeodeLinkSpeed() / 2;
365 spd_byte0 = spd_read_byte(DIMM0, SPD_tRAS);
366 if (spd_byte0 == 0xFF) {
369 spd_byte1 = spd_read_byte(DIMM1, SPD_tRAS);
370 if (spd_byte1 == 0xFF) {
373 if (spd_byte0 < spd_byte1) {
374 spd_byte0 = spd_byte1;
377 /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
378 spd_byte1 = (spd_byte0 * memspeed) / 1000;
379 if (((spd_byte0 * memspeed) % 1000)) {
382 dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT;
385 spd_byte0 = spd_read_byte(DIMM0, SPD_tRP);
386 if (spd_byte0 == 0xFF) {
389 spd_byte1 = spd_read_byte(DIMM1, SPD_tRP);
390 if (spd_byte1 == 0xFF) {
393 if (spd_byte0 < spd_byte1) {
394 spd_byte0 = spd_byte1;
397 /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
398 spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
399 if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
402 dimm_setting |= spd_byte1 << CF8F_LOWER_PRE2ACT_SHIFT;
405 spd_byte0 = spd_read_byte(DIMM0, SPD_tRCD);
406 if (spd_byte0 == 0xFF) {
409 spd_byte1 = spd_read_byte(DIMM1, SPD_tRCD);
410 if (spd_byte1 == 0xFF) {
413 if (spd_byte0 < spd_byte1) {
414 spd_byte0 = spd_byte1;
417 /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
418 spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
419 if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
422 dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2CMD_SHIFT;
425 spd_byte0 = spd_read_byte(DIMM0, SPD_tRRD);
426 if (spd_byte0 == 0xFF) {
429 spd_byte1 = spd_read_byte(DIMM1, SPD_tRRD);
430 if (spd_byte1 == 0xFF) {
433 if (spd_byte0 < spd_byte1) {
434 spd_byte0 = spd_byte1;
437 /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
438 spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
439 if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
442 dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2ACT_SHIFT;
444 /* tRC = tRP + tRAS */
445 dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) +
446 ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))
447 << CF8F_LOWER_ACT2ACTREF_SHIFT;
449 msr = rdmsr(MC_CF8F_DATA);
450 msr.lo &= 0xF00000FF;
451 msr.lo |= dimm_setting;
452 msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
453 wrmsr(MC_CF8F_DATA, msr);
455 /* MC_CF1017 setup */
457 spd_byte0 = spd_read_byte(DIMM0, SPD_tRFC);
458 if (spd_byte0 == 0xFF) {
461 spd_byte1 = spd_read_byte(DIMM1, SPD_tRFC);
462 if (spd_byte1 == 0xFF) {
465 if (spd_byte0 < spd_byte1) {
466 spd_byte0 = spd_byte1;
470 /* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
471 spd_byte1 = (spd_byte0 * memspeed) / 1000;
472 if (((spd_byte0 * memspeed) % 1000)) {
475 } else { /* Not all SPDs have tRFC setting. Use this formula tRFC = tRC + 1 clk */
476 spd_byte1 = ((dimm_setting >> CF8F_LOWER_ACT2ACTREF_SHIFT) & 0x0F) + 1;
478 dimm_setting = spd_byte1 << CF1017_LOWER_REF2ACT_SHIFT; /* note this clears the cf8f dimm setting */
479 msr = rdmsr(MC_CF1017_DATA);
480 msr.lo &= ~(0x1F << CF1017_LOWER_REF2ACT_SHIFT);
481 msr.lo |= dimm_setting;
482 wrmsr(MC_CF1017_DATA, msr);
484 /* tWTR: Set tWTR to 2 for 400MHz and above GLBUS (200Mhz mem) other wise it stay default(1) */
485 if (memspeed > 198) {
486 msr = rdmsr(MC_CF1017_DATA);
487 msr.lo &= ~(0x7 << CF1017_LOWER_WR_TO_RD_SHIFT);
488 msr.lo |= 2 << CF1017_LOWER_WR_TO_RD_SHIFT;
489 wrmsr(MC_CF1017_DATA, msr);
493 static void set_extended_mode_registers(void)
495 uint8_t spd_byte0, spd_byte1;
497 spd_byte0 = spd_read_byte(DIMM0, SPD_DEVICE_ATTRIBUTES_GENERAL);
498 if (spd_byte0 == 0xFF) {
501 spd_byte1 = spd_read_byte(DIMM1, SPD_DEVICE_ATTRIBUTES_GENERAL);
502 if (spd_byte1 == 0xFF) {
505 spd_byte1 &= spd_byte0;
507 msr = rdmsr(MC_CF07_DATA);
508 if (spd_byte1 & 1) { /* Drive Strength Control */
509 msr.lo |= CF07_LOWER_EMR_DRV_SET;
511 if (spd_byte1 & 2) { /* FET Control */
512 msr.lo |= CF07_LOWER_EMR_QFC_SET;
514 wrmsr(MC_CF07_DATA, msr);
517 static void EnableMTest(void)
521 msr = rdmsr(GLCP_DELAY_CONTROLS);
522 msr.hi &= ~(7 << 20); /* clear bits 54:52 */
523 if (GeodeLinkSpeed() < 200) {
526 wrmsr(GLCP_DELAY_CONTROLS, msr);
528 msr = rdmsr(MC_CFCLK_DBUG);
530 CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET |
531 CFCLK_UPPER_MTST_RBEX_EN_SET;
532 msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET;
533 wrmsr(MC_CFCLK_DBUG, msr);
535 print_info("Enabled MTest for TLA debug\n");
538 static void sdram_set_registers(const struct mem_controller *ctrl)
543 /* Set Timing Control */
544 msrnum = MC_CF1017_DATA;
546 msr.lo &= ~(7 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
547 if (GeodeLinkSpeed() < 334) {
548 msr.lo |= (3 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
550 msr.lo |= (4 << CF1017_LOWER_RD_TMG_CTL_SHIFT);
554 /* Set Refresh Staggering */
555 msrnum = MC_CF07_DATA;
558 msr.lo |= 0x40; /* set refresh to 4SDRAM clocks */
561 /* Memory Interleave: Set HOI here otherwise default is LOI */
562 /* msrnum = MC_CF8F_DATA;
564 msr.hi |= CF8F_UPPER_HOI_LOI_SET;
565 wrmsr(msrnum, msr); */
568 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
572 banner("sdram_set_spd_register\n");
573 post_code(POST_MEM_SETUP); // post_70h
575 spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
576 banner("Check DIMM 0");
577 /* Check DIMM is not Register and not Buffered DIMMs. */
578 if ((spd_byte != 0xFF) && (spd_byte & 3)) {
579 print_emerg("DIMM0 NOT COMPATIBLE\n");
580 post_code(ERROR_UNSUPPORTED_DIMM);
583 banner("Check DIMM 1");
584 spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
585 if ((spd_byte != 0xFF) && (spd_byte & 3)) {
586 print_emerg("DIMM1 NOT COMPATIBLE\n");
587 post_code(ERROR_UNSUPPORTED_DIMM);
591 post_code(POST_MEM_SETUP2); // post_72h
592 banner("Check DDR MAX");
594 /* Check that the memory is not overclocked. */
598 post_code(POST_MEM_SETUP3); // post_73h
599 banner("AUTOSIZE DIMM 0");
600 auto_size_dimm(DIMM0);
601 post_code(POST_MEM_SETUP4); // post_74h
602 banner("AUTOSIZE DIMM 1");
603 auto_size_dimm(DIMM1);
605 /* Set CAS latency */
606 banner("set cas latency");
607 post_code(POST_MEM_SETUP5); // post_75h
610 /* Set all the other latencies here (tRAS, tRP....) */
611 banner("set all latency");
614 /* Set Extended Mode Registers */
616 set_extended_mode_registers();
618 banner("set ref rate");
619 /* Set Memory Refresh Rate */
624 /* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
625 * Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
626 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
631 /*********************************************************************
632 ;* Turn on MC/DIMM interface per JEDEC
633 ;* 1) Clock stabilizes > 200us
635 ;* 3) Precharge All to put all banks into an idles state
636 ;* 4) EMRS to enable DLL
637 ;* 6) MRS w/ memory config & reset DLL set
638 ;* 7) Wait 200 clocks (2us)
639 ;* 8) Precharge All and 2 Auto refresh
640 ;* 9) MRS w/ memory config & reset DLL clear
641 ;* 8) DDR SDRAM ready for normal operation
642 ;********************************************************************/
643 post_code(POST_MEM_ENABLE); // post_76h
645 /* Only enable MTest for TLA memory debug */
648 /* If both Page Size = "Not Installed" we have a problems and should halt. */
649 msr = rdmsr(MC_CF07_DATA);
650 if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) ==
651 ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
652 print_emerg("No memory in the system\n");
653 post_code(ERROR_NO_DIMMS);
658 msrnum = MC_CFCLK_DBUG;
660 msr.lo &= ~(CFCLK_LOWER_MASK_CKE_SET0 | CFCLK_LOWER_MASK_CKE_SET1);
663 /* Force Precharge All on next command, EMRS */
664 msrnum = MC_CFCLK_DBUG;
666 msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;
669 /* EMRS to enable DLL (pre-setup done in setExtendedModeRegisters) */
670 msrnum = MC_CF07_DATA;
672 msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET;
674 msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DDR_SET);
677 /* Clear Force Precharge All */
678 msrnum = MC_CFCLK_DBUG;
680 msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;
683 /* MRS Reset DLL - set */
684 msrnum = MC_CF07_DATA;
686 msr.lo |= CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET;
688 msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET);
691 /* 2us delay (200 clocks @ 200Mhz). We probably really don't need this but.... better safe. */
692 /* Wait 2 PORT61 ticks. between 15us and 30us */
693 /* This would be endless if the timer is stuck. */
694 while ((inb(0x61))) ; /* find the first edge */
695 while (!(~inb(0x61))) ;
697 /* Force Precharge All on the next command, auto-refresh */
698 msrnum = MC_CFCLK_DBUG;
700 msr.lo |= CFCLK_LOWER_FORCE_PRE_SET;
703 /* Manually AUTO refresh #1 */
704 /* If auto refresh was not enabled above we would need to do 8 refreshes to prime the pump before these 2. */
705 msrnum = MC_CF07_DATA;
707 msr.lo |= CF07_LOWER_REF_TEST_SET;
709 msr.lo &= ~CF07_LOWER_REF_TEST_SET;
712 /* Clear Force Precharge All */
713 msrnum = MC_CFCLK_DBUG;
715 msr.lo &= ~CFCLK_LOWER_FORCE_PRE_SET;
718 /* Manually AUTO refresh */
719 /* The MC should insert the right delay between the refreshes */
720 msrnum = MC_CF07_DATA;
722 msr.lo |= CF07_LOWER_REF_TEST_SET;
724 msr.lo &= ~CF07_LOWER_REF_TEST_SET;
727 /* MRS Reset DLL - clear */
728 msrnum = MC_CF07_DATA;
730 msr.lo |= CF07_LOWER_PROG_DRAM_SET;
732 msr.lo &= ~CF07_LOWER_PROG_DRAM_SET;
735 /* Allow MC to tristate during idle cycles with MTEST OFF */
736 msrnum = MC_CFCLK_DBUG;
738 msr.lo &= ~CFCLK_LOWER_TRISTATE_DIS_SET;
741 /* Disable SDCLK DIMM1 slot if no DIMM installed to save power. */
742 msr = rdmsr(MC_CF07_DATA);
743 if ((msr.hi & (7 << CF07_UPPER_D1_PSZ_SHIFT)) ==
744 (7 << CF07_UPPER_D1_PSZ_SHIFT)) {
745 msrnum = GLCP_DELAY_CONTROLS;
747 msr.hi |= (1 << 23); /* SDCLK bit for 2.0 */
751 /* Set PMode0 Sensitivity Counter */
752 msr.lo = 0; /* pmode 0=0 most aggressive */
753 msr.hi = 0x200; /* pmode 1=200h */
754 wrmsr(MC_CF_PMCTR, msr);
756 /* Set PMode1 Up delay enable */
757 msrnum = MC_CF1017_DATA;
759 msr.lo |= (209 << 8); /* bits[15:8] = 209 */
762 print_emerg("DRAM controller init done.\n");
763 post_code(POST_MEM_SETUP_GOOD); //0x7E
765 /* make sure there is nothing stale in the cache */
766 /* CAR stack is in the cache __asm__ __volatile__("wbinvd\n"); */
768 /* The RAM dll needs a write to lock on so generate a few dummy writes */
769 /* Note: The descriptor needs to be enabled to point at memory */
770 volatile unsigned long *ptr;
771 for (i = 0; i < 5; i++) {
773 *ptr = (unsigned long)i;
775 /* SWAPSiF for PBZ 4112 (Errata 34) */
776 /* check for failed DLL settings now that we have done a memory write. */
777 msrnum = GLCP_DELAY_CONTROLS;
779 if ((msr.lo & 0x7FF) == 0x104) {
781 /* If you had it you would need to clear out the fail boot count flag */
782 /* (depending on where it counts from etc). */
784 /* The reset we are about to perform clears the PM_SSC register in the */
785 /* 5536 so will need to store the S3 resume flag in NVRAM otherwise */
786 /* it would do a normal boot */
788 /* Reset the system */
789 msrnum = MDD_SOFT_RESET;
794 print_info("RAM DLL lock\n");