1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
11 #include "northbridge.h"
12 #include <cpu/amd/gx2def.h>
13 #include <cpu/x86/msr.h>
14 #include <cpu/x86/cache.h>
15 #include <cpu/amd/vr.h>
17 #include "../../../southbridge/amd/cs5536/cs5536.h"
20 extern void graphics_init(void);
22 #define NORTHBRIDGE_FILE "northbridge.c"
24 /* todo: add a resource record. We don't do this here because this may be called when
25 * very little of the platform is actually working.
34 msr = rdmsr(0x20000018);
35 printk_debug("sizeram: %08x:%08x\n", msr.hi, msr.lo);
41 sizem = (1 << ((dimm >> 12)-1)) * 8;
48 sizem += (1 << ((dimm >> 12)-1)) * 8;
50 printk_debug("sizeram: sizem 0x%x\n", sizem);
55 /* here is programming for the various MSRs.*/
56 #define IM_QWAIT 0x100000
58 #define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */
59 #define DMCF_SERIAL_LOAD_MISSES (2) /* enabled */
61 /* these are the 8-bit attributes for controlling RCONF registers */
62 #define CACHE_DISABLE (1<<0)
63 #define WRITE_ALLOCATE (1<<1)
64 #define WRITE_PROTECT (1<<2)
65 #define WRITE_THROUGH (1<<3)
66 #define WRITE_COMBINE (1<<4)
67 #define WRITE_SERIALIZE (1<<5)
69 /* ram has none of this stuff */
70 #define RAM_PROPERTIES (0)
71 #define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE)
72 #define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE)
73 #define MSR_WS_CD_DEFAULT (0x21212121)
75 /* 1810-1817 give you 8 registers with which to program protection regions */
76 /* the are region configuration range registers, or RRCF */
77 /* in msr terms, the are a straight base, top address assign, since they are 4k aligned. */
78 /* so no left-shift needed for top or base */
79 #define RRCF_LOW(base,properties) (base|(1<<8)|properties)
80 #define RRCF_LOW_CD(base) RRCF_LOW(base, CACHE_DISABLE)
82 /* build initializer for P2D MSR */
83 #define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}}
84 #define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}}
85 #define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}}
86 #define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}}
87 #define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}}
88 #define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
89 #define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
97 {0x1700, {.hi = 0, .lo = IM_QWAIT}},
98 {0x1800, {.hi = DMCF_WRITE_SERIALIZE_REQUEST, .lo = DMCF_SERIAL_LOAD_MISSES}},
99 /* 1808 will be done down below, so we have to do 180a->1817 (well, 1813 really) */
100 /* for 180a, for now, we assume VSM will configure it */
101 /* 180b is left at reset value,a0000-bffff is non-cacheable */
102 /* 180c, c0000-dffff is set to write serialize and non-cachable */
103 /* oops, 180c will be set by cpu bug handling in cpubug.c */
104 //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}},
105 /* 180d is left at default, e0000-fffff is non-cached */
107 /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */
108 /* we will not set 0x180f, the DMM,yet */
109 //{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
110 //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},
111 //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},
112 //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},
113 /* now for GLPCI routing */
115 P2D_BM(0x10000020, 0x1, 0x0, 0x0, 0xfff80),
116 P2D_BM(0x10000021, 0x1, 0x0, 0x80000, 0xfffe0),
117 P2D_SC(0x1000002c, 0x1, 0x0, 0x0, 0xff03, 0xC0000),
119 P2D_BM(0x40000020, 0x1, 0x0, 0x0, 0xfff80),
120 P2D_BM(0x40000021, 0x1, 0x0, 0x80000, 0xfffe0),
121 P2D_SC(0x4000002d, 0x1, 0x0, 0x0, 0xff03, 0xC0000),
125 /* note that dev is NOT used -- yet */
126 static void irq_init_steering(struct device *dev, uint16_t irq_map) {
127 /* Set up IRQ steering */
128 uint32_t pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
130 printk_debug("%s(%08X [%08X], %04X)\n", __func__, dev, pciAddr, irq_map);
132 /* The IRQ steering values (in hex) are effectively dcba, where:
133 * <a> represents the IRQ for INTA,
134 * <b> represents the IRQ for INTB,
135 * <c> represents the IRQ for INTC, and
136 * <d> represents the IRQ for INTD.
137 * Thus, a value of irq_map = 0xAA5B translates to:
138 * INTA = IRQB (IRQ 11)
139 * INTB = IRQ5 (IRQ 5)
140 * INTC = IRQA (IRQ 10)
141 * INTD = IRQA (IRQ 10)
143 outl(pciAddr & ~3, 0xCF8);
144 outl(irq_map, 0xCFC);
151 * Returns the amount of memory (in KB) available to the system. This is the
152 * total amount of memory less the amount of memory reserved for SMM use.
156 setup_gx2_cache(void)
159 unsigned long long val;
160 int sizekbytes, sizereg;
162 sizekbytes = sizeram() * 1024;
163 printk_debug("setup_gx2_cache: enable for %d KB\n", sizekbytes);
164 /* build up the rconf word. */
165 /* the SYSTOP bits 27:8 are actually the top bits from 31:12. Book fails to say that */
167 val = ((unsigned long long) ROM_PROPERTIES) << 56;
168 /* make rom base useful for 1M roms */
169 /* Flash base address -- sized for 1M for now*/
170 val |= ((unsigned long long) 0xfff00)<<36;
171 /* set the devrp properties */
172 val |= ((unsigned long long) DEVICE_PROPERTIES) << 28;
173 /* Take our TOM, RIGHT shift 12, since it page-aligned, then LEFT-shift 8 for reg. */
174 /* yank off memory for the SMM handler */
175 sizekbytes -= SMM_SIZE;
176 sizereg = sizekbytes;
177 sizereg *= 1024; // convert to bytes
181 val |= RAM_PROPERTIES;
183 msr.hi = (val >> 32);
184 printk_debug("msr 0x%08X will be set to %08x:%08x\n", CPU_RCONF_DEFAULT, msr.hi, msr.lo);
185 wrmsr(CPU_RCONF_DEFAULT, msr);
192 /* we have to do this here. We have not found a nicer way to do it */
197 unsigned long tmp, tmp2;
199 unsigned long size_kb, membytes;
201 size_kb = setup_gx2_cache();
203 membytes = size_kb * 1024;
204 /* NOTE! setup_gx2_cache returns the SIZE OF RAM - RAMADJUST!
205 * so it is safe to use. You should NOT at this point call
206 * sizeram() directly.
209 /* we need to set 0x10000028 and 0x40000029 */
211 * These two descriptors cover the range from 1 MB (0x100000) to
212 * SYSTOP (a.k.a. TOM, or Top of Memory)
216 /* This has already been done elsewhere */
217 printk_debug("size_kb 0x%x, membytes 0x%x\n", size_kb, membytes);
218 msr.hi = 0x20000000 | membytes>>24;
219 msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
220 wrmsr(0x10000028, msr);
221 msr.hi = 0x20000000 | membytes>>24;
222 msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
223 wrmsr(0x40000029, msr);
226 msr = rdmsr(0x10000028);
227 printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
228 msr = rdmsr(0x40000029);
229 printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
232 /* fixme: SMM MSR 0x10000026 and 0x400000023 */
233 /* calculate the OFFSET field */
234 tmp = membytes - SMM_OFFSET;
238 tmp |= (SMM_OFFSET >> 24);
240 /* calculate the PBASE and PMASK fields */
241 tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20 == left 8 */
242 tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff);
243 printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
246 wrmsr(0x10000026, msr);
252 wrmsr(0x10000026, msr);
253 msr = rdmsr(0x10000026);
254 printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
261 printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
263 #if 0 // SDG - don't do this
264 /* now do the default MSR values */
265 for(i = 0; msr_defaults[i].msr_no; i++) {
267 wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr); // MSR - see table above
268 msr = rdmsr(msr_defaults[i].msr_no);
269 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
274 static void enable_shadow(device_t dev)
279 static void northbridge_init(device_t dev)
283 struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
284 printk_debug("northbridge: %s()\n", __func__);
287 irq_init_steering(dev, nb->irqmap);
289 /* HACK HACK HACK HACK */
290 /* 0x1000 is where GPIO is being assigned */
297 /* due to vsa interactions, we need not not touch the nb settings ... */
298 /* this is a test -- we are not sure it will work -- but it ought to */
299 static void set_resources(struct device *dev)
301 struct resource *resource, *last;
306 last = &dev->resource[dev->resources];
308 for(resource = &dev->resource[0]; resource < last; resource++) {
309 pci_set_resource(dev, resource);
312 for(link = 0; link < dev->links; link++) {
314 bus = &dev->link[link];
316 assign_resources(bus);
321 /* set a default latency timer */
322 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
324 /* set a default secondary latency timer */
325 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
326 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
329 /* zero the irq settings */
330 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
332 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
334 /* set the cache line size, so far 64 bytes is good for everyone */
335 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
341 static struct device_operations northbridge_operations = {
342 .read_resources = pci_dev_read_resources,
344 .set_resources = pci_dev_set_resources,
346 .set_resources = set_resources,
347 .enable_resources = pci_dev_enable_resources,
348 .init = northbridge_init,
353 static const struct pci_driver northbridge_driver __pci_driver = {
354 .ops = &northbridge_operations,
355 .vendor = PCI_VENDOR_ID_NS,
356 .device = PCI_DEVICE_ID_NS_GX2,
359 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
361 static void pci_domain_read_resources(device_t dev)
363 struct resource *resource;
365 printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
367 /* Initialize the system wide io space constraints */
368 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
369 resource->limit = 0xffffUL;
370 resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
372 /* Initialize the system wide memory resources constraints */
373 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
374 resource->limit = 0xffffffffULL;
375 resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
378 static void ram_resource(device_t dev, unsigned long index,
379 unsigned long basek, unsigned long sizek)
381 struct resource *resource;
386 resource = new_resource(dev, index);
387 resource->base = ((resource_t)basek) << 10;
388 resource->size = ((resource_t)sizek) << 10;
389 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
390 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
393 static void tolm_test(void *gp, struct device *dev, struct resource *new)
395 struct resource **best_p = gp;
396 struct resource *best;
398 if (!best || (best->base > new->base)) {
405 static uint32_t find_pci_tolm(struct bus *bus)
407 struct resource *min;
410 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
412 if (min && tolm > min->base) {
418 #define FRAMEBUFFERK 4096
420 static void pci_domain_set_resources(device_t dev)
426 pci_tolm = find_pci_tolm(&dev->link[0]);
427 mc_dev = dev->link[0].children;
429 unsigned int tomk, tolmk;
430 unsigned int ramreg = 0;
432 unsigned int *bcdramtop = (unsigned int *)(GX_BASE + BC_DRAM_TOP);
433 unsigned int *mcgbaseadd = (unsigned int *)(GX_BASE + MC_GBASE_ADD);
435 for(i=0; i<0x20; i+= 0x10) {
436 unsigned int *mcreg = (unsigned int *)(GX_BASE + MC_BANK_CFG);
437 unsigned int mem_config = *mcreg;
439 if (((mem_config & (DIMM_PG_SZ << i)) >> (4 + i)) == 7)
441 ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
446 /* Sort out the framebuffer size */
447 tomk -= FRAMEBUFFERK;
448 *bcdramtop = ((tomk << 10) - 1);
449 *mcgbaseadd = (tomk >> 9);
451 printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
452 printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
454 printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10));
456 /* Compute the top of Low memory */
457 tolmk = pci_tolm >> 10;
459 /* The PCI hole does does not overlap the memory.
463 /* Report the memory regions */
465 ram_resource(dev, idx++, 0, tolmk);
468 assign_resources(&dev->link[0]);
471 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
473 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
477 static struct device_operations pci_domain_ops = {
478 .read_resources = pci_domain_read_resources,
479 .set_resources = pci_domain_set_resources,
480 .enable_resources = enable_childrens_resources,
482 .scan_bus = pci_domain_scan_bus,
485 static void cpu_bus_init(device_t dev)
487 initialize_cpus(&dev->link[0]);
490 static void cpu_bus_noop(device_t dev)
494 static struct device_operations cpu_bus_ops = {
495 .read_resources = cpu_bus_noop,
496 .set_resources = cpu_bus_noop,
497 .enable_resources = cpu_bus_noop,
498 .init = cpu_bus_init,
502 void chipsetInit (void);
504 static void enable_dev(struct device *dev)
506 printk_debug("gx2 north: enable_dev\n");
507 void northbridgeinit(void);
508 void chipsetinit(struct northbridge_amd_gx2_config *nb);
509 void setup_realmode_idt(void);
510 void do_vsmbios(void);
511 /* Set the operations if it is a special bus type */
512 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
513 struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
514 extern void cpubug(void);
515 printk_debug("DEVICE_PATH_PCI_DOMAIN\n");
516 /* cpubug MUST be called before setup_gx2(), so we force the issue here */
521 /* do this here for now -- this chip really breaks our device model */
522 setup_realmode_idt();
525 dev->ops = &pci_domain_ops;
527 ram_resource(dev, 0, 0, ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE);
528 } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
529 printk_debug("DEVICE_PATH_APIC_CLUSTER\n");
530 dev->ops = &cpu_bus_ops;
532 printk_debug("gx2 north: end enable_dev\n");
535 struct chip_operations northbridge_amd_gx2_ops = {
536 CHIP_NAME("AMD GX (previously GX2) Northbridge")
537 .enable_dev = enable_dev,