1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
11 #include "northbridge.h"
12 #include <cpu/amd/gx1def.h>
13 #include <cpu/x86/cache.h>
16 #define NORTHBRIDGE_FILE "northbridge.c"
20 static void optimize_xbus(device_t dev)
22 /* Optimise X-Bus performance */
23 pci_write_config8(dev, 0x40, 0x1e);
24 pci_write_config8(dev, 0x41, 0x52);
25 pci_write_config8(dev, 0x43, 0xc1);
26 pci_write_config8(dev, 0x44, 0x00);
30 * Enables memory from 0xC0000 up to 0xFFFFF.
31 * So this region is read/write and cache able
33 * FIXME: What about PCI master access into
37 static void enable_shadow(device_t dev)
39 write32(GX_BASE+BC_XMAP_2, 0x77777777);
40 write32(GX_BASE+BC_XMAP_3, 0x77777777);
43 static void northbridge_init(device_t dev)
45 printk(BIOS_DEBUG, "northbridge: %s()\n", __func__);
49 printk(BIOS_SPEW, "Calling enable_cache()\n");
54 static struct device_operations northbridge_operations = {
55 .read_resources = pci_dev_read_resources,
56 .set_resources = pci_dev_set_resources,
57 .enable_resources = pci_dev_enable_resources,
58 .init = northbridge_init,
63 static const struct pci_driver northbridge_driver __pci_driver = {
64 .ops = &northbridge_operations,
65 .vendor = PCI_VENDOR_ID_CYRIX,
66 .device = PCI_DEVICE_ID_CYRIX_PCI_MASTER,
69 #if CONFIG_WRITE_HIGH_TABLES==1
70 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
71 extern uint64_t high_tables_base, high_tables_size;
74 static void pci_domain_set_resources(device_t dev)
79 pci_tolm = find_pci_tolm(dev->link_list);
80 mc_dev = dev->link_list->children;
82 unsigned int tomk, tolmk;
83 unsigned int ramreg = 0;
85 unsigned int *bcdramtop = (unsigned int *)(GX_BASE + BC_DRAM_TOP);
86 unsigned int *mcgbaseadd = (unsigned int *)(GX_BASE + MC_GBASE_ADD);
88 for(i=0; i<0x20; i+= 0x10) {
89 unsigned int *mcreg = (unsigned int *)(GX_BASE + MC_BANK_CFG);
90 unsigned int mem_config = *mcreg;
92 if (((mem_config & (DIMM_PG_SZ << i)) >> (4 + i)) == 7)
94 ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
99 /* Sort out the framebuffer size */
100 tomk -= CONFIG_VIDEO_MB * 1024;
101 *bcdramtop = ((tomk << 10) - 1);
102 *mcgbaseadd = (tomk >> 9);
104 printk(BIOS_DEBUG, "BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
105 printk(BIOS_DEBUG, "MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
107 printk(BIOS_DEBUG, "I would set ram size to %d Mbytes\n", (tomk >> 10));
109 /* Compute the top of Low memory */
110 tolmk = pci_tolm >> 10;
112 /* The PCI hole does does not overlap the memory.
117 #if CONFIG_WRITE_HIGH_TABLES==1
118 /* Leave some space for ACPI, PIRQ and MP tables */
119 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
120 high_tables_size = HIGH_TABLES_SIZE * 1024;
123 /* Report the memory regions */
125 ram_resource(dev, idx++, 0, tolmk);
127 assign_resources(dev->link_list);
130 static struct device_operations pci_domain_ops = {
131 .read_resources = pci_domain_read_resources,
132 .set_resources = pci_domain_set_resources,
133 .enable_resources = NULL,
135 .scan_bus = pci_domain_scan_bus,
138 static void cpu_bus_init(device_t dev)
140 printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__);
141 initialize_cpus(dev->link_list);
144 static void cpu_bus_noop(device_t dev)
148 static struct device_operations cpu_bus_ops = {
149 .read_resources = cpu_bus_noop,
150 .set_resources = cpu_bus_noop,
151 .enable_resources = cpu_bus_noop,
152 .init = cpu_bus_init,
156 static void enable_dev(struct device *dev)
158 printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__);
159 /* Set the operations if it is a special bus type */
160 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
161 printk(BIOS_SPEW, "DEVICE_PATH_PCI_DOMAIN\n");
162 dev->ops = &pci_domain_ops;
165 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
166 printk(BIOS_SPEW, "DEVICE_PATH_APIC_CLUSTER\n");
167 dev->ops = &cpu_bus_ops;
169 printk(BIOS_SPEW, "device path type %d\n",dev->path.type);
173 struct chip_operations northbridge_amd_gx1_ops = {
174 CHIP_NAME("AMD GX1 Northbridge")
175 .enable_dev = enable_dev,