1 /* coherent hypertransport initialization for AMD64
3 * written by Stefan Reinauer <stepan@openbios.org>
4 * (c) 2003-2004 by SuSE Linux AG
6 * (c) 2004 Tyan Computer
7 * 2004.12 yhlu added support to create routing table dynamically.
8 * it also support 8 ways too. (8 ways ladder or 8 ways crossbar)
10 * This code is licensed under GPL.
14 * This algorithm assumes a grid configuration as follows:
17 * org. : 1x1 2x1 2x2 2x3 2x4
66 #include <device/pci_def.h>
67 #include <device/pci_ids.h>
68 #include <device/hypertransport_def.h>
69 #include "arch/romcc_io.h"
73 #define enable_bsp_routing() enable_routing(0)
75 #define NODE_HT(x) PCI_DEV(0,24+x,0)
76 #define NODE_MP(x) PCI_DEV(0,24+x,1)
77 #define NODE_MC(x) PCI_DEV(0,24+x,3)
79 #define DEFAULT 0x00010101 /* default row entry */
84 #ifndef CROSS_BAR_47_56
85 #define CROSS_BAR_47_56 0
88 #ifndef TRY_HIGH_FIRST
89 #define TRY_HIGH_FIRST 0
92 #ifndef K8_HT_FREQ_1G_SUPPORT
93 #define K8_HT_FREQ_1G_SUPPORT 0
96 #ifndef K8_HT_CHECK_PENDING_LINK
97 #if CONFIG_MAX_PHYSICAL_CPUS >= 4
98 #define K8_HT_CHECK_PENDING_LINK 1
100 #define K8_HT_CHECK_PENDING_LINK 0
104 #ifndef CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
105 #define CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED 0
108 #ifndef ENABLE_APIC_EXT_ID
109 #define ENABLE_APIC_EXT_ID 0
113 static inline void print_linkn (const char *strval, uint8_t byteval)
117 printk_debug("%s%02x\r\n", strval, byteval);
119 print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n");
124 static void disable_probes(void)
126 /* disable read/write/fill probes for uniprocessor setup
127 * they don't make sense if only one cpu is available
130 /* Hypetransport Transaction Control Register
132 * [ 0: 0] Disable read byte probe
134 * 1 = Probes not issued
135 * [ 1: 1] Disable Read Doubleword probe
137 * 1 = Probes not issued
138 * [ 2: 2] Disable write byte probes
140 * 1 = Probes not issued
141 * [ 3: 3] Disable Write Doubleword Probes
143 * 1 = Probes not issued.
144 * [10:10] Disable Fill Probe
145 * 0 = Probes issued for cache fills
146 * 1 = Probes not issued for cache fills.
151 print_spew("Disabling read/write/fill probes for UP... ");
153 val=pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL);
154 val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C |
155 HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P |
156 HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P;
157 pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val);
159 print_spew("done.\r\n");
163 static void enable_apic_ext_id(u8 node)
165 #if ENABLE_APIC_EXT_ID==1
166 #warning "FIXME Is the right place to enable apic ext id here?"
170 val = pci_read_config32(NODE_HT(node), 0x68);
171 val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
172 pci_write_config32(NODE_HT(node), 0x68, val);
176 static void enable_routing(u8 node)
180 /* HT Initialization Control Register
182 * [ 0: 0] Routing Table Disable
183 * 0 = Packets are routed according to routing tables
184 * 1 = Packets are routed according to the default link field
185 * [ 1: 1] Request Disable (BSP should clear this)
186 * 0 = Request packets may be generated
187 * 1 = Request packets may not be generated.
188 * [ 3: 2] Default Link (Read-only)
192 * 11 = CPU on same node
194 * - Scratch bit cleared by a cold reset
195 * [ 5: 5] BIOS Reset Detect
196 * - Scratch bit cleared by a cold reset
197 * [ 6: 6] INIT Detect
198 * - Scratch bit cleared by a warm or cold reset not by an INIT
202 /* Enable routing table */
203 print_spew("Enabling routing table for node ");
204 print_spew_hex8(node);
206 val=pci_read_config32(NODE_HT(node), 0x6c);
207 val &= ~((1<<1)|(1<<0));
208 pci_write_config32(NODE_HT(node), 0x6c, val);
210 print_spew(" done.\r\n");
213 static void fill_row(u8 node, u8 row, u32 value)
215 pci_write_config32(NODE_HT(node), 0x40+(row<<2), value);
218 #if CONFIG_MAX_PHYSICAL_CPUS > 1
219 static u8 link_to_register(int ldt)
222 * [ 0: 3] Request Route
223 * [0] Route to this node
224 * [1] Route to Link 0
225 * [2] Route to Link 1
226 * [3] Route to Link 2
229 if (ldt&0x08) return 0x40;
230 if (ldt&0x04) return 0x20;
231 if (ldt&0x02) return 0x00;
233 /* we should never get here */
234 print_spew("Unknown Link\n");
238 static u32 get_row(u8 node, u8 row)
240 return pci_read_config32(NODE_HT(node), 0x40+(row<<2));
243 static int link_connection(u8 src, u8 dest)
245 return get_row(src, dest) & 0x0f;
248 static void rename_temp_node(u8 node)
252 print_spew("Renaming current temporary node to ");
253 print_spew_hex8(node);
255 val=pci_read_config32(NODE_HT(7), 0x60);
256 val &= (~7); /* clear low bits. */
257 val |= node; /* new node */
258 pci_write_config32(NODE_HT(7), 0x60, val);
260 print_spew(" done.\r\n");
263 static int verify_connection(u8 dest)
265 /* See if we have a valid connection to dest */
268 /* Verify that the coherent hypertransport link is
269 * established and actually working by reading the
270 * remode node's vendor/device id
272 val = pci_read_config32(NODE_HT(dest),0);
273 if(val != 0x11001022)
279 static uint16_t read_freq_cap(device_t dev, uint8_t pos)
281 /* Handle bugs in valid hypertransport frequency reporting */
285 freq_cap = pci_read_config16(dev, pos);
286 freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
288 #if K8_HT_FREQ_1G_SUPPORT == 1
289 if (!is_cpu_pre_e0())
295 id = pci_read_config32(dev, 0);
297 /* AMD K8 Unsupported 1Ghz? */
298 if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
299 freq_cap &= ~(1 << HT_FREQ_1000Mhz);
305 static int optimize_connection(device_t node1, uint8_t link1, device_t node2, uint8_t link2)
307 static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
308 static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
309 uint16_t freq_cap1, freq_cap2;
310 uint8_t width_cap1, width_cap2, width, old_width, ln_width1, ln_width2;
311 uint8_t freq, old_freq;
313 /* Set link width and frequency */
315 /* Initially assume everything is already optimized and I don't need a reset */
318 /* Get the frequency capabilities */
319 freq_cap1 = read_freq_cap(node1, link1 + PCI_HT_CAP_HOST_FREQ_CAP);
320 freq_cap2 = read_freq_cap(node2, link2 + PCI_HT_CAP_HOST_FREQ_CAP);
322 /* Calculate the highest possible frequency */
323 freq = log2(freq_cap1 & freq_cap2);
325 /* See if I am changing the link freqency */
326 old_freq = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_FREQ);
328 needs_reset |= old_freq != freq;
329 old_freq = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_FREQ);
331 needs_reset |= old_freq != freq;
333 /* Set the Calulcated link frequency */
334 pci_write_config8(node1, link1 + PCI_HT_CAP_HOST_FREQ, freq);
335 pci_write_config8(node2, link2 + PCI_HT_CAP_HOST_FREQ, freq);
337 /* Get the width capabilities */
338 width_cap1 = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH);
339 width_cap2 = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH);
341 /* Calculate node1's input width */
342 ln_width1 = link_width_to_pow2[width_cap1 & 7];
343 ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7];
344 if (ln_width1 > ln_width2) {
345 ln_width1 = ln_width2;
347 width = pow2_to_link_width[ln_width1];
348 /* Calculate node1's output width */
349 ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7];
350 ln_width2 = link_width_to_pow2[width_cap2 & 7];
351 if (ln_width1 > ln_width2) {
352 ln_width1 = ln_width2;
354 width |= pow2_to_link_width[ln_width1] << 4;
356 /* See if I am changing node1's width */
357 old_width = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1);
359 needs_reset |= old_width != width;
361 /* Set node1's widths */
362 pci_write_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1, width);
364 // * Calculate node2's width */
365 width = ((width & 0x70) >> 4) | ((width & 0x7) << 4);
367 /* See if I am changing node2's width */
368 old_width = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1);
370 needs_reset |= old_width != width;
372 /* Set node2's widths */
373 pci_write_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1, width);
378 static uint8_t get_linkn_first(uint8_t byte)
380 if(byte & 0x02) { byte = 0; }
381 else if(byte & 0x04) { byte = 1; }
382 else if(byte & 0x08) { byte = 2; }
386 static uint8_t get_linkn_last(uint8_t byte)
388 if(byte & 0x02) { byte &= 0x0f; byte |= 0x00; }
389 if(byte & 0x04) { byte &= 0x0f; byte |= 0x10; }
390 if(byte & 0x08) { byte &= 0x0f; byte |= 0x20; }
394 static uint8_t get_linkn_last_count(uint8_t byte)
397 if(byte & 0x02) { byte &= 0xcf; byte |= 0x00; byte+=0x40; }
398 if(byte & 0x04) { byte &= 0xcf; byte |= 0x10; byte+=0x40; }
399 if(byte & 0x08) { byte &= 0xcf; byte |= 0x20; byte+=0x40; }
403 static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is for temp use*/
408 for(linkn = 0; linkn<3; linkn++) {
411 regpos = 0x98 + 0x20 * linkn;
412 reg = pci_read_config32(NODE_HT(source), regpos);
413 if ((reg & 0x17) != 3) continue; /* it is not conherent or not connected*/
418 fill_row(source,row, val);
421 static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn)
426 val |= 1<<(linkn+1+8); /*for direct connect response route should equal to request table*/
428 if(((source &1)!=(dest &1))
430 && ( (source<4)||(source>5) ) //(6,7) (7,6) should still be here
431 //(6,5) (7,4) should be here
436 /*for CROSS_BAR_47_56 47, 56, should be here too
437 and for 47, 56, 57, 75, 46, 64 we need to substract another link to
440 val_s = get_row(temp, source);
441 val |= ((val_s>>16) - (1<<(linkn+1)))<<16;
444 fill_row(temp,dest, val );
448 static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) {
450 val = get_row(source, dest);
451 val -= link_connection(source, kickout)<<16;
452 fill_row(source, dest, val);
455 static void opt_broadcast_rt_group(const u8 *conn, int num) {
458 for(i=0; i<num; i+=3) {
459 opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]);
462 static void opt_broadcast_rt_plus(u8 source, u8 dest, u8 kickout) {
464 val = get_row(source, dest);
465 val += link_connection(source, kickout)<<16;
466 fill_row(source, dest, val);
469 static void opt_broadcast_rt_plus_group(const u8 *conn, int num) {
472 for(i=0; i<num; i+=3) {
473 opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]);
478 static void setup_row_direct(u8 source, u8 dest, u8 linkn){
479 setup_row_direct_x(source, source, dest, linkn);
482 static void setup_remote_row_direct(u8 source, u8 dest, u8 linkn){
483 setup_row_direct_x(7, source, dest, linkn);
486 static void setup_temp_row(u8 source, u8 dest)
488 /* copy val from (source, dest) to (source,7) */
489 fill_row(source,7,get_row(source,dest));
492 static void clear_temp_row(u8 source)
494 fill_row(source, 7, DEFAULT);
497 static void setup_remote_node(u8 node)
499 static const uint8_t pci_reg[] = {
500 0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c,
501 0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78,
502 0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc,
503 0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8,
504 0xc4, 0xcc, 0xd4, 0xdc,
505 0xc0, 0xc8, 0xd0, 0xd8,
506 0xe0, 0xe4, 0xe8, 0xec,
510 print_spew("setup_remote_node: ");
512 /* copy the default resource map from node 0 */
513 for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) {
517 value = pci_read_config32(NODE_MP(0), reg);
518 pci_write_config32(NODE_MP(7), reg, value);
521 print_spew("done\r\n");
524 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1*/
527 #if CONFIG_MAX_PHYSICAL_CPUS > 2
529 static void setup_row_indirect_x(u8 temp, u8 source, u8 dest)
531 static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 diff)
534 /*for indirect connection, we need to compute the val from val_s(source, source), and val_g(source, gateway) */
541 gateway = source + 2;
543 gateway = source - 2;
546 val_s = get_row(temp, source);
547 val = get_row(temp, gateway);
554 diff = ((source&1)!=(dest &1));
557 if(diff && (val_s!=(val&0xff)) ) { /* use another connect as response*/
559 #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
561 /* Some node have two links left
562 * don't worry we only have (2, (3 as source need to handle
565 byte = get_linkn_last_count(byte);
566 if((byte>>2)>1) { /* make sure not the corner*/
568 val_s-=link_connection(temp, source-2); /* -down*/
573 val_s-=link_connection(temp, 6); // for 7,2 via 5
574 } else if (source==6){
575 val_s-=link_connection(temp, 7); // for 6,3 via 4
578 if (source < gateway) { // for 5, 4 via 7
579 val_s-=link_connection(temp, source-2);
582 val_s-=link_connection(temp, source+2); /* -up*/
590 if(diff) { /* cross rung?*/
594 val_s = get_row(temp, source);
595 val |= ((val_s>>16) - link_connection(temp, gateway))<<16;
598 fill_row(temp, dest, val);
603 static void setup_row_indirect(u8 source, u8 dest)
605 setup_row_indirect_x(source, source, dest);
608 static void setup_row_indirect(u8 source, u8 dest, u8 gateway, u8 diff)
610 setup_row_indirect_x(source, source, dest, gateway, diff);
614 static void setup_row_indirect_group(const u8 *conn, int num)
619 for(i=0; i<num; i+=2) {
620 setup_row_indirect(conn[i], conn[i+1]);
622 for(i=0; i<num; i+=4) {
623 setup_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]);
630 static void setup_remote_row_indirect(u8 source, u8 dest)
632 setup_row_indirect_x(7, source, dest);
635 static void setup_remote_row_indirect(u8 source, u8 dest, u8 gateway, u8 diff)
637 setup_row_indirect_x(7, source, dest, gateway, diff);
641 static void setup_remote_row_indirect_group(const u8 *conn, int num)
646 for(i=0; i<num; i+=2) {
647 setup_remote_row_indirect(conn[i], conn[i+1]);
649 for(i=0; i<num; i+=4) {
650 setup_remote_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]);
655 #endif /*CONFIG_MAX_PHYSICAL_CPUS > 2*/
658 static void setup_uniprocessor(void)
660 print_spew("Enabling UP settings\r\n");
661 #if CONFIG_LOGICAL_CPUS==1
662 unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;
668 #if CONFIG_MAX_PHYSICAL_CPUS > 2
669 static int optimize_connection_group(const u8 *opt_conn, int num) {
672 for(i=0; i<num; i+=2) {
673 needs_reset = optimize_connection(
674 NODE_HT(opt_conn[i]), 0x80 + link_to_register(link_connection(opt_conn[i],opt_conn[i+1])),
675 NODE_HT(opt_conn[i+1]), 0x80 + link_to_register(link_connection(opt_conn[i+1],opt_conn[i])) );
681 #if CONFIG_MAX_PHYSICAL_CPUS > 1
682 static unsigned setup_smp2(void)
689 setup_row_local(0, 0); /* it will update the broadcast RT*/
692 byte = (val>>16) & 0xfe;
693 if(byte<0x2) { /* no coherent connection so get out.*/
698 /* Setup and check a temporary connection to node 1 */
699 #if TRY_HIGH_FIRST == 1
700 byte = get_linkn_last(byte); /* Max Link to node1 */
702 byte = get_linkn_first(byte); /*Min Link to node1 --- according to AMD*/
704 print_linkn("(0,1) link=", byte);
705 setup_row_direct(0,1, byte);
706 setup_temp_row(0, 1);
708 verify_connection(7);
710 /* We found 2 nodes so far */
711 val = pci_read_config32(NODE_HT(7), 0x6c);
712 byte = (val>>2) & 0x3; /*get default link on node7 to node0*/
713 print_linkn("(1,0) link=", byte);
714 setup_row_local(7,1);
715 setup_remote_row_direct(1, 0, byte);
717 #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
719 byte = (val>>16) & 0xfe;
720 byte = get_linkn_last_count(byte);
721 if((byte>>2)==3) { /* Oh! we need to treat it as node2. So use another link*/
723 byte = (val>>16) & 0xfe;
724 #if TRY_HIGH_FIRST == 1
725 byte = get_linkn_first(byte); /* Min link to Node1 */
727 byte = get_linkn_last(byte); /* Max link to Node1*/
729 print_linkn("\t-->(0,1) link=", byte);
730 setup_row_direct(0,1, byte);
731 setup_temp_row(0, 1);
733 verify_connection(7);
735 /* We found 2 nodes so far */
736 val = pci_read_config32(NODE_HT(7), 0x6c);
737 byte = (val>>2) & 0x3; /* get default link on node7 to node0*/
738 print_linkn("\t-->(1,0) link=", byte);
739 setup_row_local(7,1);
740 setup_remote_row_direct(1, 0, byte);
744 setup_remote_node(1); /* Setup the regs on the remote node */
745 rename_temp_node(1); /* Rename Node 7 to Node 1 */
746 enable_routing(1); /* Enable routing on Node 1 */
748 /*don't need and it is done by clear_dead_links */
754 #endif /*CONFIG_MAX_PHYSICAL_CPUS > 1 */
756 #if CONFIG_MAX_PHYSICAL_CPUS > 2
758 static unsigned setup_smp4(void)
766 /* Setup and check temporary connection from Node 0 to Node 2 */
768 byte = ((val>>16) & 0xfe) - link_connection(0,1);
769 byte = get_linkn_last_count(byte);
771 if((byte>>2)==0) { /* We should have two coherent for 4p and above*/
776 byte &= 3; /* bit [3,2] is count-1*/
777 print_linkn("(0,2) link=", byte);
778 setup_row_direct(0, 2, byte); /*(0,2) direct link done*/
780 /* We found 3 nodes so far. Now setup a temporary
781 * connection from node 0 to node 3 via node 1
783 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
784 /* here should setup_row_direct(1,3) at first, before that we should find the link in node 1 to 3*/
786 byte = ((val>>16) & 0xfe) - link_connection(1,0);
787 byte = get_linkn_first(byte);
788 print_linkn("(1,3) link=", byte);
789 setup_row_direct(1,3,byte); /* (1, 3) direct link done*/
791 /* We found 4 nodes so far. Now setup all nodes for 4p */
792 // We need to make sure 0,2 and 1,3 link is set already
794 static const u8 conn4_1[] = {
799 static const u8 conn4_1[] = {
805 setup_row_indirect_group(conn4_1, sizeof(conn4_1)/sizeof(conn4_1[0]));
808 verify_connection(7);
809 val = pci_read_config32(NODE_HT(7), 0x6c);
810 byte = (val>>2) & 0x3; /* get default link on 7 to 0*/
811 print_linkn("(2,0) link=", byte);
813 setup_row_local(7,2);
814 setup_remote_row_direct(2, 0, byte); /* node 2 to node 0 direct link done */
815 setup_remote_node(2); /* Setup the regs on the remote node */
817 rename_temp_node(2); /* Rename Node 7 to Node 2 */
818 enable_routing(2); /* Enable routing on Node 2 */
822 verify_connection(7);
824 val = pci_read_config32(NODE_HT(7), 0x6c);
825 byte = (val>>2) & 0x3; /* get default link on 7 to 1*/
826 print_linkn("(3,1) link=", byte);
828 setup_row_local(7,3);
829 setup_remote_row_direct(3, 1, byte); /* node 3 to node 1 direct link done */
830 setup_remote_node(3); /* Setup the regs on the remote node */
832 /* We need to init link between 2, and 3 direct link */
834 byte = ((val>>16) & 0xfe) - link_connection(2,0);
835 byte = get_linkn_last_count(byte);
836 print_linkn("(2,3) link=", byte & 3);
838 setup_row_direct(2,3, byte & 0x3);
841 verify_connection(7); /* to 3*/
843 #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
844 /* We need to find out which link is to node3 */
845 if((byte>>2)==2) { /* one to node3, one to node0, one to node4*/
847 if((val>>16) == 1) { /* that link is to node4, because via node1 it has been set, recompute it*/
849 byte = ((val>>16) & 0xfe) - link_connection(2,0);
850 byte = get_linkn_first(byte);
851 print_linkn("\t-->(2,3) link=", byte);
852 setup_row_direct(2,3,byte);
854 verify_connection(7); /* to 3*/
859 val = pci_read_config32(NODE_HT(7), 0x6c);
860 byte = (val>>2) & 0x3; /* get default link on 7 to 2*/
861 print_linkn("(3,2) link=", byte);
862 setup_remote_row_direct(3,2, byte);
864 #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || (CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED == 1)
865 /* set link from 3 to 5 before enable it*/
867 byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1);
868 byte = get_linkn_last_count(byte);
869 if((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/
870 byte &= 3; /*bit [3,2] is count-2*/
871 print_linkn("(3,5) link=", byte);
872 setup_remote_row_direct(3, 5, byte);
876 byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
877 byte = get_linkn_last_count(byte);
879 if((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/
880 byte &= 3; /* bit [3,2] is count-2*/
881 print_linkn("(2,4) link=", byte);
882 setup_row_direct(2, 4, byte);
886 //Beside 3, 1 is set, We need to make sure 3, 5 is set already in case has three link in 3
888 static const u8 conn4_3[] = {
892 static const u8 conn4_3[] = {
896 setup_remote_row_indirect_group(conn4_3, sizeof(conn4_3)/sizeof(conn4_3[0]));
898 /* ready to enable RT for Node 3 */
900 enable_routing(3); /* enable routing on node 3 (temp.) */
902 // beside 2, 0 is set, We need to make sure 2, 4 link is set already in case has three link in 2
904 static const u8 conn4_2[] = {
908 static const u8 conn4_2[] = {
912 setup_row_indirect_group(conn4_2, sizeof(conn4_2)/sizeof(conn4_2[0]));
915 /*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */
916 /* it will be done by clear_dead_links */
925 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 2 */
927 #if CONFIG_MAX_PHYSICAL_CPUS > 4
929 static unsigned setup_smp6(void)
937 /* Setup and check temporary connection from Node 0 to Node 4 through 2*/
939 byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
940 byte = get_linkn_last_count(byte);
942 if((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/
947 /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3*/
948 /* set link from 3 to 5 before enable it*/
950 byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1);
951 byte = get_linkn_last_count(byte);
952 if((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/
957 /* We found 6 nodes so far. Now setup all nodes for 6p */
958 #warning "FIXME we need to find out the correct gateway for 6p"
959 static const u8 conn6_1[] = {
977 setup_row_indirect_group(conn6_1, sizeof(conn6_1)/sizeof(conn6_1[0]));
979 for(byte=0; byte<4; byte+=2) {
980 setup_temp_row(byte,byte+2);
982 verify_connection(7);
983 val = pci_read_config32(NODE_HT(7), 0x6c);
984 byte = (val>>2) & 0x3; /*get default link on 7 to 2*/
985 print_linkn("(4,2) link=", byte);
987 setup_row_local(7,4);
988 setup_remote_row_direct(4, 2, byte);
989 setup_remote_node(4); /* Setup the regs on the remote node */
991 /* Set indirect connection to 0, to 3 */
992 //we only need to set 4,0 here
993 static const u8 conn6_2[] = {
1001 setup_remote_row_indirect_group(conn6_2, sizeof(conn6_2)/sizeof(conn6_2[0]));
1003 rename_temp_node(4);
1006 setup_temp_row(0,1);
1007 for(byte=0; byte<4; byte+=2) {
1008 setup_temp_row(byte+1,byte+3);
1010 verify_connection(7);
1012 val = pci_read_config32(NODE_HT(7), 0x6c);
1013 byte = (val>>2) & 0x3; /* get default link on 7 to 3*/
1014 print_linkn("(5,3) link=", byte);
1015 setup_row_local(7,5);
1016 setup_remote_row_direct(5, 3, byte);
1017 setup_remote_node(5); /* Setup the regs on the remote node */
1019 #if !CROSS_BAR_47_56
1020 /* We need to init link between 4, and 5 direct link */
1022 byte = ((val>>16) & 0xfe) - link_connection(4,2);
1023 byte = get_linkn_last_count(byte);
1024 print_linkn("(4,5) link=", byte & 3);
1026 setup_row_direct(4,5, byte & 0x3);
1027 setup_temp_row(0,2);
1028 setup_temp_row(2,4);
1029 setup_temp_row(4,5);
1030 verify_connection(7); /* to 5*/
1032 #if CONFIG_MAX_PHYSICAL_CPUS > 6
1033 /* We need to find out which link is to node5 */
1035 if((byte>>2)==2) { /* one to node5, one to node2, one to node6*/
1037 if((val>>16) == 1) { /* that link is to node6, because via node 3 node 5 has been set*/
1039 byte = ((val>>16) & 0xfe) - link_connection(4,2);
1040 byte = get_linkn_first(byte);
1041 print_linkn("\t-->(4,5) link=", byte);
1042 setup_row_direct(4,5,byte);
1043 setup_temp_row(4,5);
1044 verify_connection(7); /* to 5*/
1049 val = pci_read_config32(NODE_HT(7), 0x6c);
1050 byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
1051 print_linkn("(5,4) link=", byte);
1052 setup_remote_row_direct(5,4, byte);
1056 byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3);
1057 byte = get_linkn_last_count(byte);
1058 if((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/
1059 byte &= 3; /*bit [3,2] is count-2*/
1060 print_linkn("(5,7) link=", byte);
1061 setup_remote_row_direct(5, 7, byte);
1066 byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
1067 byte = get_linkn_last_count(byte);
1069 if((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/
1070 byte &= 3; /* bit [3,2] is count-2*/
1071 print_linkn("(4,6) link=", byte);
1072 setup_row_direct(4, 6, byte);
1077 //We need to set 5,0 here only, We need to set up 5, 7 to make 5,0
1078 /* Set indirect connection to 0, to 3 for indirect we will use clockwise routing */
1079 static const u8 conn6_3[] = {
1080 #if !CROSS_BAR_47_56
1087 setup_remote_row_indirect_group(conn6_3, sizeof(conn6_3)/sizeof(conn6_3[0]));
1089 /* ready to enable RT for 5 */
1090 rename_temp_node(5);
1091 enable_routing(5); /* enable routing on node 5 (temp.) */
1093 static const u8 conn6_4[] = {
1094 #if !CROSS_BAR_47_56
1113 setup_row_indirect_group(conn6_4, sizeof(conn6_4)/sizeof(conn6_4[0]));
1116 /* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5)
1117 * It will be done by clear_dead_links
1119 for(byte=0; byte<4; byte++) {
1120 clear_temp_row(byte);
1128 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 4 */
1130 #if CONFIG_MAX_PHYSICAL_CPUS > 6
1132 static unsigned setup_smp8(void)
1140 /* Setup and check temporary connection from Node 0 to Node 6 via 2 and 4 to 7 */
1143 byte = ((val>>16) & 0xfe) - link_connection(4,2);
1145 byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
1146 byte = get_linkn_last_count(byte); /* Max link to 6*/
1147 if((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/
1154 byte = get_linkn_last_count(byte); /* Max link to 6*/
1155 if((byte>>2)<2) { /* We should have two or three coherent links on node 4 for 8p*/
1159 #if TRY_HIGH_FIRST == 1
1160 byte = ((val>>16) & 0xfe) - link_connection(4,2);
1161 byte = get_linkn_first(byte); /*Min link to 6*/
1163 byte &= 3; /* bit [3,2] is count-1 or 2*/
1165 print_linkn("(4,6) link=", byte);
1166 setup_row_direct(4, 6, byte);
1169 #if !CROSS_BAR_47_56
1170 /* Setup and check temporary connection from Node 0 to Node 7 through 1, 3, 5*/
1172 byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3);
1173 byte = get_linkn_last_count(byte);
1174 if((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/
1180 /* We found 8 nodes so far. Now setup all nodes for 8p */
1181 static const u8 conn8_1[] = {
1182 #if !CROSS_BAR_47_56
1205 setup_row_indirect_group(conn8_1,sizeof(conn8_1)/sizeof(conn8_1[0]));
1207 for(byte=0; byte<6; byte+=2) {
1208 setup_temp_row(byte,byte+2);
1210 verify_connection(7);
1211 val = pci_read_config32(NODE_HT(7), 0x6c);
1212 byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
1213 print_linkn("(6,4) link=", byte);
1215 setup_row_local(7,6);
1216 setup_remote_row_direct(6, 4, byte);
1217 setup_remote_node(6); /* Setup the regs on the remote node */
1218 /* Set indirect connection to 0, to 3 */
1219 #warning "FIXME we need to find out the correct gateway for 8p"
1220 static const u8 conn8_2[] = {
1221 #if !CROSS_BAR_47_56
1228 setup_remote_row_indirect_group(conn8_2, sizeof(conn8_2)/sizeof(conn8_2[0]));
1232 /* here init 5, 6 */
1233 /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3, 5*/
1235 byte = ((val>>16) & 0xfe) - link_connection(5,3);
1236 #if TRY_HIGH_FIRST == 1
1237 byte = get_linkn_first(byte);
1239 byte = get_linkn_last(byte);
1241 print_linkn("(5,6) link=", byte);
1242 setup_row_direct(5, 6, byte);
1244 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
1245 for(byte=0; byte<4; byte+=2) {
1246 setup_temp_row(byte+1,byte+3);
1248 setup_temp_row(5,6);
1250 verify_connection(7);
1252 val = get_row(7,6); // to chect it if it is node6 before renaming
1253 if( (val>>16) == 1) { // it is real node 7 so swap it
1254 /* We need to recompute link to 6 */
1256 byte = ((val>>16) & 0xfe) - link_connection(5,3);
1257 #if TRY_HIGH_FIRST == 1
1258 byte = get_linkn_first(byte);
1260 byte = get_linkn_last(byte);
1262 print_linkn("\t-->(5,6) link=", byte);
1263 setup_row_direct(5, 6, byte);
1265 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
1266 for(byte=0; byte<4; byte+=2) {
1267 setup_temp_row(byte+1,byte+3);
1270 setup_temp_row(5,6);
1272 verify_connection(7);
1274 val = pci_read_config32(NODE_HT(7), 0x6c);
1275 byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
1276 print_linkn("(6,5) link=", byte);
1277 setup_remote_row_direct(6, 5, byte);
1278 /*Till now 56, 65 done */
1281 rename_temp_node(6);
1284 #if !CROSS_BAR_47_56
1285 setup_temp_row(0,1);
1286 for(byte=0; byte<6; byte+=2) {
1287 setup_temp_row(byte+1,byte+3);
1290 verify_connection(7);
1292 val = pci_read_config32(NODE_HT(7), 0x6c);
1293 byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
1294 print_linkn("(7,5) link=", byte);
1295 setup_row_local(7,7);
1296 setup_remote_row_direct(7, 5, byte);
1300 byte = ((val>>16) & 0xfe) - link_connection(4,2) - link_connection(4,6);
1301 byte = get_linkn_first(byte);
1302 print_linkn("(4,7) link=", byte);
1303 setup_row_direct(4, 7, byte);
1305 /* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/
1306 for(byte=0; byte<4; byte+=2) {
1307 setup_temp_row(byte,byte+2);
1310 verify_connection(7);
1312 val = pci_read_config32(NODE_HT(7), 0x6c);
1313 byte = (val>>2) & 0x3; /* get default link on 7 to 4*/
1314 print_linkn("(7,4) link=", byte);
1315 setup_row_local(7,7);
1316 setup_remote_row_direct(7, 4, byte);
1317 /* till now 4-7, 7-4 done. */
1319 setup_remote_node(7); /* Setup the regs on the remote node */
1322 /* here init 5, 7 */
1323 /* Setup and check temporary connection from Node 0 to Node 5 through 1, 3, 5*/
1325 byte = ((val>>16) & 0xfe) - link_connection(5,3) - link_connection(5,6);
1326 byte = get_linkn_first(byte);
1327 print_linkn("(5,7) link=", byte);
1328 setup_row_direct(5, 7, byte);
1330 setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
1331 for(byte=0; byte<4; byte+=2) {
1332 setup_temp_row(byte+1,byte+3);
1335 verify_connection(7);
1337 val = pci_read_config32(NODE_HT(7), 0x6c);
1338 byte = (val>>2) & 0x3; /* get default link on 7 to 5*/
1339 print_linkn("(7,5) link=", byte);
1340 setup_remote_row_direct(7, 5, byte);
1341 /*Till now 57, 75 done */
1345 /* We need to init link between 6, and 7 direct link */
1347 #if !CROSS_BAR_47_56
1348 byte = ((val>>16) & 0xfe) - link_connection(6,4);
1350 byte = ((val>>16) & 0xfe) - link_connection(6,4) - link_connection(6,5);
1352 byte = get_linkn_first(byte);
1353 print_linkn("(6,7) link=", byte);
1354 setup_row_direct(6,7, byte);
1357 #if !CROSS_BAR_47_56
1358 byte = ((val>>16) & 0xfe) - link_connection(7,5);
1360 byte = ((val>>16) & 0xfe) - link_connection(7,5) - link_connection(7,4);
1362 byte = get_linkn_first(byte);
1363 print_linkn("(7,6) link=", byte);
1364 setup_row_direct(7,6, byte);
1366 /* Set indirect connection to 0, to 3 for indirect we will use clockwise routing */
1367 static const u8 conn8_3[] = {
1368 #if !CROSS_BAR_47_56
1369 0, 7, /* restore it*/
1391 6, 1, 5, 0, // or 4, 1
1393 6, 3, 5, 0, // or 4, 1
1395 7, 0, 4, 0, // or 5, 1
1397 7, 2, 4, 0, // or 5, 1
1400 0, 7, 2, 0, /* restore it*/
1405 2, 5, 4, 1, /* reset it */
1408 4, 1, 2, 1, /* reset it */
1411 5, 2, 3, 1, /* reset it */
1417 setup_row_indirect_group(conn8_3, sizeof(conn8_3)/sizeof(conn8_3[0]));
1420 /* for 47, 56, 57, 75, 46, 64 we need to substract another link to
1422 static const u8 conn8_4[] = {
1445 6, 1, 7, // needed for via 5
1448 6, 3, 7, // needed for via 5
1450 7, 0, 6, // needed for via 4
1453 7, 2, 6, // needed for via 4
1458 opt_broadcast_rt_group(conn8_4, sizeof(conn8_4)/sizeof(conn8_4[0]));
1460 static const u8 conn8_5[] = {
1466 opt_broadcast_rt_plus_group(conn8_5, sizeof(conn8_5)/sizeof(conn8_5[0]));
1471 /* ready to enable RT for Node 7 */
1472 enable_routing(7); /* enable routing on node 7 (temp.) */
1477 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 6 */
1480 #if CONFIG_MAX_PHYSICAL_CPUS > 1
1482 static unsigned setup_smp(void)
1486 print_spew("Enabling SMP settings\r\n");
1488 nodes = setup_smp2();
1489 #if CONFIG_MAX_PHYSICAL_CPUS > 2
1491 nodes = setup_smp4();
1494 #if CONFIG_MAX_PHYSICAL_CPUS > 4
1496 nodes = setup_smp6();
1499 #if CONFIG_MAX_PHYSICAL_CPUS > 6
1501 nodes = setup_smp8();
1505 printk_debug("%02x nodes initialized.\r\n", nodes);
1507 print_debug_hex8(nodes);
1508 print_debug(" nodes initialized.\r\n");
1514 static unsigned verify_mp_capabilities(unsigned nodes)
1516 unsigned node, mask;
1518 mask = 0x06; /* BigMPCap */
1520 for (node=0; node<nodes; node++) {
1521 mask &= pci_read_config32(NODE_MC(node), 0xe8);
1525 #if CONFIG_MAX_PHYSICAL_CPUS > 2
1526 case 0x02: /* MPCap */
1528 print_err("Going back to DP\r\n");
1533 case 0x00: /* Non SMP */
1535 print_err("Going back to UP\r\n");
1546 static void clear_dead_routes(unsigned nodes)
1550 #if CONFIG_MAX_PHYSICAL_CPUS == 8
1551 if(nodes==8) return;/* don't touch (7,7)*/
1557 for(node = 7; node >= 0; node--) {
1558 for(row = 7; row >= last_row; row--) {
1559 fill_row(node, row, DEFAULT);
1563 /* Update the local row */
1564 for( node=0; node<nodes; node++) {
1566 for(row =0; row<nodes; row++) {
1567 val |= get_row(node, row);
1569 fill_row(node, node, (((val & 0xff) | ((val >> 8) & 0xff)) << 16) | 0x0101);
1572 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */
1574 #if CONFIG_LOGICAL_CPUS==1
1575 static unsigned verify_dualcore(unsigned nodes)
1577 unsigned node, totalcpus, tmp;
1580 for (node=0; node<nodes; node++) {
1581 tmp = (pci_read_config32(NODE_MC(node), 0xe8) >> 12) & 3 ;
1582 totalcpus += (tmp + 1);
1590 static void coherent_ht_finalize(unsigned nodes)
1594 #if CONFIG_LOGICAL_CPUS==1
1595 unsigned total_cpus;
1597 if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */
1598 total_cpus = verify_dualcore(nodes);
1605 /* set up cpu count and node count and enable Limit
1606 * Config Space Range for all available CPUs.
1607 * Also clear non coherent hypertransport bus range
1608 * registers on Hammer A0 revision.
1611 print_spew("coherent_ht_finalize\r\n");
1612 rev_a0 = is_cpu_rev_a0();
1613 for (node = 0; node < nodes; node++) {
1616 dev = NODE_HT(node);
1618 /* Set the Total CPU and Node count in the system */
1619 val = pci_read_config32(dev, 0x60);
1620 val &= (~0x000F0070);
1621 #if CONFIG_LOGICAL_CPUS==1
1622 val |= ((total_cpus-1)<<16)|((nodes-1)<<4);
1624 val |= ((nodes-1)<<16)|((nodes-1)<<4);
1626 pci_write_config32(dev, 0x60, val);
1628 /* Only respond to real cpu pci configuration cycles
1629 * and optimize the HT settings
1631 val=pci_read_config32(dev, HT_TRANSACTION_CONTROL);
1632 val &= ~((HTTC_BUF_REL_PRI_MASK << HTTC_BUF_REL_PRI_SHIFT) |
1633 (HTTC_MED_PRI_BYP_CNT_MASK << HTTC_MED_PRI_BYP_CNT_SHIFT) |
1634 (HTTC_HI_PRI_BYP_CNT_MASK << HTTC_HI_PRI_BYP_CNT_SHIFT));
1635 val |= HTTC_LIMIT_CLDT_CFG |
1636 (HTTC_BUF_REL_PRI_8 << HTTC_BUF_REL_PRI_SHIFT) |
1637 (3 << HTTC_MED_PRI_BYP_CNT_SHIFT) |
1638 (3 << HTTC_HI_PRI_BYP_CNT_SHIFT);
1639 pci_write_config32(dev, HT_TRANSACTION_CONTROL, val);
1642 pci_write_config32(dev, 0x94, 0);
1643 pci_write_config32(dev, 0xb4, 0);
1644 pci_write_config32(dev, 0xd4, 0);
1648 print_spew("done\r\n");
1651 static int apply_cpu_errata_fixes(unsigned nodes)
1654 int needs_reset = 0;
1655 for(node = 0; node < nodes; node++) {
1658 dev = NODE_MC(node);
1659 if (is_cpu_pre_c0()) {
1662 * Limit the number of downstream posted requests to 1
1664 cmd = pci_read_config32(dev, 0x70);
1665 if ((cmd & (3 << 0)) != 2) {
1668 pci_write_config32(dev, 0x70, cmd );
1671 cmd = pci_read_config32(dev, 0x7c);
1672 if ((cmd & (3 << 4)) != 0) {
1675 pci_write_config32(dev, 0x7c, cmd );
1678 /* Clock Power/Timing Low */
1679 cmd = pci_read_config32(dev, 0xd4);
1680 if (cmd != 0x000D0001) {
1682 pci_write_config32(dev, 0xd4, cmd);
1683 needs_reset = 1; /* Needed? */
1687 else if (is_cpu_pre_d0()) { // d0 later don't need it
1690 * Set Clk Ramp Hystersis to 7
1691 * Clock Power/Timing Low
1693 cmd_ref = 0x04e20707; /* Registered */
1694 cmd = pci_read_config32(dev, 0xd4);
1695 if(cmd != cmd_ref) {
1696 pci_write_config32(dev, 0xd4, cmd_ref );
1697 needs_reset = 1; /* Needed? */
1704 static int optimize_link_read_pointers(unsigned nodes)
1707 int needs_reset = 0;
1708 for(node = 0; node < nodes; node++) {
1709 device_t f0_dev, f3_dev;
1710 uint32_t cmd_ref, cmd;
1712 f0_dev = NODE_HT(node);
1713 f3_dev = NODE_MC(node);
1714 cmd_ref = cmd = pci_read_config32(f3_dev, 0xdc);
1715 for(link = 0; link < 3; link++) {
1718 /* This works on an Athlon64 because unimplemented links return 0 */
1719 reg = 0x98 + (link * 0x20);
1720 link_type = pci_read_config32(f0_dev, reg);
1721 /* Only handle coherent links */
1722 if ((link_type & (LinkConnected | InitComplete|NonCoherent)) ==
1723 (LinkConnected|InitComplete))
1725 cmd &= ~(0xff << (link *8));
1726 cmd |= 0x25 << (link *8);
1729 if (cmd != cmd_ref) {
1730 pci_write_config32(f3_dev, 0xdc, cmd);
1737 static int optimize_link_coherent_ht(void)
1739 int needs_reset = 0;
1743 nodes = get_nodes();
1745 #if CONFIG_MAX_PHYSICAL_CPUS > 1
1747 needs_reset |= optimize_connection(
1748 NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)),
1749 NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) );
1752 #if CONFIG_MAX_PHYSICAL_CPUS > 2
1754 /* optimize physical connections - by LYH */
1755 static const u8 opt_conn4[] = {
1760 needs_reset |= optimize_connection_group(opt_conn4, sizeof(opt_conn4)/sizeof(opt_conn4[0]));
1764 #if CONFIG_MAX_PHYSICAL_CPUS > 4
1766 static const uint8_t opt_conn6[] ={
1769 #if !CROSS_BAR_47_56
1773 needs_reset |= optimize_connection_group(opt_conn6, sizeof(opt_conn6)/sizeof(opt_conn6[0]));
1777 #if CONFIG_MAX_PHYSICAL_CPUS > 6
1779 static const uint8_t opt_conn8[] ={
1788 needs_reset |= optimize_connection_group(opt_conn8, sizeof(opt_conn8)/sizeof(opt_conn8[0]));
1794 needs_reset |= apply_cpu_errata_fixes(nodes);
1795 needs_reset |= optimize_link_read_pointers(nodes);
1800 #if RAMINIT_SYSINFO == 1
1801 static void setup_coherent_ht_domain(void)
1803 static int setup_coherent_ht_domain(void)
1809 enable_bsp_routing();
1811 #if CONFIG_MAX_PHYSICAL_CPUS > 1
1812 nodes = setup_smp();
1813 nodes = verify_mp_capabilities(nodes);
1814 clear_dead_routes(nodes);
1818 setup_uniprocessor();
1820 coherent_ht_finalize(nodes);
1822 #if RAMINIT_SYSINFO == 0
1823 return optimize_link_coherent_ht();