2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
5 * Copyright (C) 2010 Win Enterprises, Inc (anishp@win-ent.com)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <device/pci_def.h>
26 #include <device/pnp_def.h>
28 #include <console/console.h>
29 #include "lib/ramtest.c"
30 #include "cpu/x86/bist.h"
31 #include "cpu/x86/msr.h"
32 #include <cpu/amd/lxdef.h>
33 #include <cpu/amd/geode_post_code.h>
34 #include "southbridge/amd/cs5536/cs5536.h"
36 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
38 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
39 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
40 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
42 static inline int spd_read_byte(unsigned int device, unsigned int address)
44 return smbus_read_byte(device, address);
47 #define ManualConf 0 /* Do automatic strapped PLL config */
48 #define PLLMSRhi 0x00001490 /* Manual settings for the PLL */
49 #define PLLMSRlo 0x02000030
53 #include "northbridge/amd/lx/raminit.h"
54 #include "northbridge/amd/lx/pll_reset.c"
55 #include "northbridge/amd/lx/raminit.c"
56 #include "lib/generic_sdram.c"
57 #include "cpu/amd/model_lx/cpureginit.c"
58 #include "cpu/amd/model_lx/syspreinit.c"
59 #include "cpu/amd/model_lx/msrinit.c"
61 static void mb_gpio_init(void)
63 /* Early mainboard specific GPIO setup. */
66 void main(unsigned long bist)
70 static const struct mem_controller memctrl[] = {
71 {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
79 /* Note: must do this AFTER the early_setup! It is counting on some
80 * early MSR setup for CS5536.
82 w83627hf_set_clksel_48(SERIAL_DEV);
83 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
88 /* Halt if there was a built in self test failure */
89 report_bist_failure(bist);
91 pll_reset(ManualConf);
93 cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
95 sdram_initialize(1, memctrl);
98 /* ram_check(0x00000000, 640 * 1024); */
100 /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */