2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
5 * Copyright (C) 2010 Win Enterprises, Inc (anishp@win-ent.com)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <device/pci_def.h>
25 #include <device/pnp_def.h>
27 #include "pc80/serial.c"
28 #include "console/console.c"
29 #include "lib/ramtest.c"
30 #include "cpu/x86/bist.h"
31 #include "cpu/x86/msr.h"
32 #include <cpu/amd/lxdef.h>
33 #include <cpu/amd/geode_post_code.h>
34 #include "southbridge/amd/cs5536/cs5536.h"
36 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
37 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
39 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
40 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
41 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
43 static inline int spd_read_byte(unsigned int device, unsigned int address)
45 return smbus_read_byte(device, address);
48 #define ManualConf 0 /* Do automatic strapped PLL config */
49 #define PLLMSRhi 0x00001490 /* Manual settings for the PLL */
50 #define PLLMSRlo 0x02000030
54 #include "northbridge/amd/lx/raminit.h"
55 #include "northbridge/amd/lx/pll_reset.c"
56 #include "northbridge/amd/lx/raminit.c"
57 #include "lib/generic_sdram.c"
58 #include "cpu/amd/model_lx/cpureginit.c"
59 #include "cpu/amd/model_lx/syspreinit.c"
66 static const struct msrinit msr_table[] =
68 {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
69 * Rom Properties: Write Serialize, WriteProtect.
71 * SysTop to RomBase Properties: Write Serialize, Cache Disable.
73 * System Memory Properties: (Write Back) */
74 {CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
75 {CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
76 {CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
78 /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
79 {MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
80 {MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
81 {MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
82 {MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
83 {MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
84 {MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
87 static void msr_init(void)
90 for (i = 0; i < ARRAY_SIZE(msr_table); i++)
91 wrmsr(msr_table[i].msrnum, msr_table[i].msr);
94 static void mb_gpio_init(void)
96 /* Early mainboard specific GPIO setup. */
99 void cache_as_ram_main(void)
103 static const struct mem_controller memctrl[] = {
104 {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
110 cs5536_early_setup();
112 /* Note: must do this AFTER the early_setup! It is counting on some
113 * early MSR setup for CS5536.
115 w83627hf_set_clksel_48(SERIAL_DEV);
116 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
121 pll_reset(ManualConf);
125 sdram_initialize(1, memctrl);
128 /* ram_check(0x00000000, 640 * 1024); */
130 /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */