src/mainboard/tyan/s4882/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15
  16 #include <cpu/amd/model_fxx_rev.h>
  17 #include "northbridge/amd/amdk8/incoherent_ht.c"
  18 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  19 #include "northbridge/amd/amdk8/raminit.h"
  20 #include "cpu/amd/model_fxx/apic_timer.c"
  21 #include "lib/delay.c"
  22
  23 #if CONFIG_USE_INIT == 0
  24 #include "lib/memcpy.c"
  25 #endif
  26
  27 #include "cpu/x86/lapic/boot_cpu.c"
  28 #include "northbridge/amd/amdk8/reset_test.c"
  29 #include "northbridge/amd/amdk8/debug.c"
  30 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  31
  32 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  33 #include "cpu/x86/bist.h"
  34
  35 #include "northbridge/amd/amdk8/setup_resource_map.c"
  36
  37 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  38
  39
  40 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  41
  42 static void memreset_setup(void)
  43 {
  44    if (is_cpu_pre_c0()) {
  45         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  46    }
  47    else {
  48         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  49    }
  50         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  51 }
  52
  53 static void memreset(int controllers, const struct mem_controller *ctrl)
  54 {
  55    if (is_cpu_pre_c0()) {
  56         udelay(800);
  57         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  58         udelay(90);
  59    }
  60 }
  61 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  62 {
  63 #define SMBUS_HUB 0x18
  64         int ret,i;
  65         unsigned device=(ctrl->channel0[0])>>8;
  66         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  67         i=2;
  68         do {
  69                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  70         } while ((ret!=0) && (i-->0));
  71
  72         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  73 }
  74 #if 0
  75 static inline void change_i2c_mux(unsigned device)
  76 {
  77 #define SMBUS_HUB 0x18
  78         int ret, i;
  79         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
  80         i=2;
  81         do {
  82                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  83                 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
  84         } while ((ret!=0) && (i-->0));
  85         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  86         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
  87 }
  88 #endif
  89
  90 static inline int spd_read_byte(unsigned device, unsigned address)
  91 {
  92         return smbus_read_byte(device, address);
  93 }
  94
  95 #define K8_4RANK_DIMM_SUPPORT 1
  96
  97 #include "northbridge/amd/amdk8/raminit.c"
  98 #include "northbridge/amd/amdk8/coherent_ht.c"
  99 #include "sdram/generic_sdram.c"
 100
 101  /* tyan does not want the default */
 102 #include "resourcemap.c"
 103
 104 #if CONFIG_LOGICAL_CPUS==1
 105 #define SET_NB_CFG_54 1
 106 #endif
 107 #include "cpu/amd/dualcore/dualcore.c"
 108
 109 #define RC0 ((1<<2)<<8)
 110 #define RC1 ((1<<1)<<8)
 111 #define RC2 ((1<<4)<<8)
 112 #define RC3 ((1<<3)<<8)
 113
 114 #define DIMM0 0x50
 115 #define DIMM1 0x51
 116 #define DIMM2 0x52
 117 #define DIMM3 0x53
 118
 119 #include "cpu/amd/car/copy_and_run.c"
 120
 121 #include "cpu/amd/car/post_cache_as_ram.c"
 122
 123 #include "cpu/amd/model_fxx/init_cpus.c"
 124
 125 #if USE_FALLBACK_IMAGE == 1
 126
 127 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 128 #include "northbridge/amd/amdk8/early_ht.c"
 129
 130 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 131 {
 132         unsigned last_boot_normal_x = last_boot_normal();
 133
 134         /* Is this a cpu only reset? or Is this a secondary cpu? */
 135         if ((cpu_init_detectedx) || (!boot_cpu())) {
 136                 if (last_boot_normal_x) {
 137                         goto normal_image;
 138                 } else {
 139                         goto fallback_image;
 140                 }
 141         }
 142
 143         /* Nothing special needs to be done to find bus 0 */
 144         /* Allow the HT devices to be found */
 145
 146         enumerate_ht_chain();
 147
 148         amd8111_enable_rom();
 149
 150         /* Is this a deliberate reset by the bios */
 151         if (bios_reset_detected() && last_boot_normal_x) {
 152                 goto normal_image;
 153         }
 154         /* This is the primary cpu how should I boot? */
 155         else if (do_normal_boot()) {
 156                 goto normal_image;
 157         }
 158         else {
 159                 goto fallback_image;
 160         }
 161  normal_image:
 162         __asm__ volatile ("jmp __normal_image"
 163                 : /* outputs */
 164                 : "a" (bist), "b" ( cpu_init_detectedx ) /* inputs */
 165                 );
 166
 167  fallback_image:
 168         ;
 169 }
 170 #endif
 171
 172 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 173
 174 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 175 {
 176
 177 #if USE_FALLBACK_IMAGE == 1
 178         failover_process(bist, cpu_init_detectedx);
 179 #endif
 180         real_main(bist, cpu_init_detectedx);
 181
 182 }
 183
 184 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 185 {
 186         static const uint16_t spd_addr [] = {
 187                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 188                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 189 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 190                         RC1|DIMM0, RC1|DIMM2, 0, 0,
 191                         RC1|DIMM1, RC1|DIMM3, 0, 0,
 192 #endif
 193 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 194                         RC2|DIMM0, RC2|DIMM2, 0, 0,
 195                         RC2|DIMM1, RC2|DIMM3, 0, 0,
 196                         RC3|DIMM0, RC3|DIMM2, 0, 0,
 197                         RC3|DIMM1, RC3|DIMM3, 0, 0,
 198 #endif
 199         };
 200
 201         int needs_reset;
 202         unsigned bsp_apicid = 0;
 203
 204         struct mem_controller ctrl[8];
 205         unsigned nodes;
 206
 207         if (bist == 0) {
 208                 bsp_apicid = init_cpus(cpu_init_detectedx);
 209         }
 210
 211
 212         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 213         uart_init();
 214         console_init();
 215
 216         /* Halt if there was a built in self test failure */
 217         report_bist_failure(bist);
 218
 219         setup_s4882_resource_map();
 220
 221         needs_reset = setup_coherent_ht_domain();
 222
 223 #if CONFIG_LOGICAL_CPUS==1
 224         // It is said that we should start core1 after all core0 launched
 225         wait_all_core0_started();
 226         start_other_cores();
 227 #endif
 228
 229         wait_all_aps_started(bsp_apicid);
 230
 231         // automatically set that for you, but you might meet tight space
 232         needs_reset |= ht_setup_chains_x();
 233
 234         if (needs_reset) {
 235                 print_info("ht reset -\r\n");
 236                 soft_reset();
 237         }
 238
 239         allow_all_aps_stop(bsp_apicid);
 240
 241         nodes = get_nodes();
 242         //It's the time to set ctrl now;
 243         fill_mem_ctrl(nodes, ctrl, spd_addr);
 244
 245         enable_smbus();
 246
 247         memreset_setup();
 248         sdram_initialize(nodes, ctrl);
 249
 250         post_cache_as_ram();
 251
 252 }