5 #include <device/pci_def.h>
7 #include <device/pnp_def.h>
8 #include <arch/romcc_io.h>
9 #include <cpu/x86/lapic.h>
10 #include "option_table.h"
11 #include "pc80/mc146818rtc_early.c"
12 #include "pc80/serial.c"
13 #include "arch/i386/lib/console.c"
14 #include "ram/ramtest.c"
16 #include <cpu/amd/model_fxx_rev.h>
17 #include "northbridge/amd/amdk8/incoherent_ht.c"
18 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
19 #include "northbridge/amd/amdk8/raminit.h"
20 #include "cpu/amd/model_fxx/apic_timer.c"
21 #include "lib/delay.c"
23 #if CONFIG_USE_INIT == 0
24 #include "lib/memcpy.c"
27 #include "cpu/x86/lapic/boot_cpu.c"
28 #include "northbridge/amd/amdk8/reset_test.c"
29 #include "northbridge/amd/amdk8/debug.c"
30 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
32 #include "cpu/amd/mtrr/amd_earlymtrr.c"
33 #include "cpu/x86/bist.h"
35 #include "northbridge/amd/amdk8/setup_resource_map.c"
37 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
40 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
42 static void memreset_setup(void)
44 if (is_cpu_pre_c0()) {
45 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
48 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
50 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
53 static void memreset(int controllers, const struct mem_controller *ctrl)
55 if (is_cpu_pre_c0()) {
57 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
61 static inline void activate_spd_rom(const struct mem_controller *ctrl)
63 #define SMBUS_HUB 0x18
65 unsigned device=(ctrl->channel0[0])>>8;
66 /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
69 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
70 } while ((ret!=0) && (i-->0));
72 smbus_write_byte(SMBUS_HUB, 0x03, 0);
75 static inline void change_i2c_mux(unsigned device)
77 #define SMBUS_HUB 0x18
79 print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
82 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
83 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
84 } while ((ret!=0) && (i-->0));
85 ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
86 print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
90 static inline int spd_read_byte(unsigned device, unsigned address)
92 return smbus_read_byte(device, address);
95 #define QRANK_DIMM_SUPPORT 1
97 #include "northbridge/amd/amdk8/raminit.c"
98 #include "northbridge/amd/amdk8/coherent_ht.c"
99 #include "sdram/generic_sdram.c"
101 /* tyan does not want the default */
102 #include "resourcemap.c"
104 #if CONFIG_LOGICAL_CPUS==1
105 #define SET_NB_CFG_54 1
107 #include "cpu/amd/dualcore/dualcore.c"
109 #define RC0 ((1<<2)<<8)
110 #define RC1 ((1<<1)<<8)
111 #define RC2 ((1<<4)<<8)
112 #define RC3 ((1<<3)<<8)
119 #include "cpu/amd/car/copy_and_run.c"
121 #include "cpu/amd/car/post_cache_as_ram.c"
123 #include "cpu/amd/model_fxx/init_cpus.c"
125 #if USE_FALLBACK_IMAGE == 1
127 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
128 #include "northbridge/amd/amdk8/early_ht.c"
130 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
132 unsigned last_boot_normal_x = last_boot_normal();
134 /* Is this a cpu only reset? or Is this a secondary cpu? */
135 if ((cpu_init_detectedx) || (!boot_cpu())) {
136 if (last_boot_normal_x) {
143 /* Nothing special needs to be done to find bus 0 */
144 /* Allow the HT devices to be found */
146 enumerate_ht_chain();
148 amd8111_enable_rom();
150 /* Is this a deliberate reset by the bios */
151 if (bios_reset_detected() && last_boot_normal_x) {
154 /* This is the primary cpu how should I boot? */
155 else if (do_normal_boot()) {
162 __asm__ volatile ("jmp __normal_image"
164 : "a" (bist), "b" ( cpu_init_detectedx ) /* inputs */
172 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
174 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
177 #if USE_FALLBACK_IMAGE == 1
178 failover_process(bist, cpu_init_detectedx);
180 real_main(bist, cpu_init_detectedx);
184 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
186 static const uint16_t spd_addr [] = {
187 RC0|DIMM0, RC0|DIMM2, 0, 0,
188 RC0|DIMM1, RC0|DIMM3, 0, 0,
189 #if CONFIG_MAX_PHYSICAL_CPUS > 1
190 RC1|DIMM0, RC1|DIMM2, 0, 0,
191 RC1|DIMM1, RC1|DIMM3, 0, 0,
193 #if CONFIG_MAX_PHYSICAL_CPUS > 2
194 RC2|DIMM0, RC2|DIMM2, 0, 0,
195 RC2|DIMM1, RC2|DIMM3, 0, 0,
196 RC3|DIMM0, RC3|DIMM2, 0, 0,
197 RC3|DIMM1, RC3|DIMM3, 0, 0,
202 unsigned bsp_apicid = 0;
204 struct mem_controller ctrl[8];
208 bsp_apicid = init_cpus(cpu_init_detectedx);
212 w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
216 /* Halt if there was a built in self test failure */
217 report_bist_failure(bist);
219 setup_s4882_resource_map();
221 needs_reset = setup_coherent_ht_domain();
223 wait_all_core0_started();
224 #if CONFIG_LOGICAL_CPUS==1
225 // It is said that we should start core1 after all core0 launched
227 wait_all_other_cores_started(bsp_apicid);
230 // automatically set that for you, but you might meet tight space
231 needs_reset |= ht_setup_chains_x();
234 print_info("ht reset -\r\n");
238 allow_all_aps_stop(bsp_apicid);
241 //It's the time to set ctrl now;
242 fill_mem_ctrl(nodes, ctrl, spd_addr);
247 sdram_initialize(nodes, ctrl);