src/mainboard/tyan/s4882/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <stdlib.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  16 #include "northbridge/amd/amdk8/raminit.h"
  17 #include "cpu/amd/model_fxx/apic_timer.c"
  18 #include "lib/delay.c"
  19 #include "cpu/x86/lapic/boot_cpu.c"
  20 #include "northbridge/amd/amdk8/reset_test.c"
  21 #include "northbridge/amd/amdk8/debug.c"
  22 #include "northbridge/amd/amdk8/incoherent_ht.c"
  23 #include <cpu/amd/model_fxx_rev.h>
  24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  25 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27 #include "cpu/amd/dualcore/dualcore.c"
  28
  29 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  30
  31 /* Look up a which bus a given node/link combination is on.
  32  * return 0 when we can't find the answer.
  33  */
  34 static unsigned node_link_to_bus(unsigned node, unsigned link)
  35 {
  36         unsigned reg;
  37
  38         for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
  39                 unsigned config_map;
  40                 config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
  41                 if ((config_map & 3) != 3) {
  42                         continue;
  43                 }
  44                 if ((((config_map >> 4) & 7) == node) &&
  45                         (((config_map >> 8) & 3) == link))
  46                 {
  47                         return (config_map >> 16) & 0xff;
  48                 }
  49         }
  50         return 0;
  51 }
  52
  53 static void hard_reset(void)
  54 {
  55         device_t dev;
  56
  57         /* Find the device */
  58         dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 3);
  59
  60         set_bios_reset();
  61
  62         /* enable cf9 */
  63         pci_write_config8(dev, 0x41, 0xf1);
  64         /* reset */
  65         outb(0x0e, 0x0cf9);
  66 }
  67
  68 static void soft_reset(void)
  69 {
  70         device_t dev;
  71
  72         /* Find the device */
  73         dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 0);
  74
  75         set_bios_reset();
  76         pci_write_config8(dev, 0x47, 1);
  77 }
  78
  79 static void memreset_setup(void)
  80 {
  81    if (is_cpu_pre_c0()) {
  82         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  83    }
  84    else {
  85         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  86    }
  87         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  88 }
  89
  90 static void memreset(int controllers, const struct mem_controller *ctrl)
  91 {
  92    if (is_cpu_pre_c0()) {
  93         udelay(800);
  94         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  95         udelay(90);
  96    }
  97 }
  98
  99 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 100 {
 101 #define SMBUS_HUB 0x18
 102         int ret,i;
 103         unsigned device=(ctrl->channel0[0])>>8;
 104         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
 105         i=2;
 106         do {
 107                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
 108         } while ((ret!=0) && (i-->0));
 109
 110         smbus_write_byte(SMBUS_HUB, 0x03, 0);
 111 }
 112
 113 static inline int spd_read_byte(unsigned device, unsigned address)
 114 {
 115         return smbus_read_byte(device, address);
 116 }
 117
 118 #include "northbridge/amd/amdk8/setup_resource_map.c"
 119 #define QRANK_DIMM_SUPPORT 1
 120 #include "northbridge/amd/amdk8/raminit.c"
 121 #if 0
 122         #define ENABLE_APIC_EXT_ID 1
 123         #define APIC_ID_OFFSET 0x10
 124         #define LIFT_BSP_APIC_ID 0
 125 #else
 126         #define ENABLE_APIC_EXT_ID 0
 127 #endif
 128 #include "northbridge/amd/amdk8/coherent_ht.c"
 129 #include "sdram/generic_sdram.c"
 130
 131  /* tyan does not want the default */
 132 #include "resourcemap.c"
 133
 134 #define FIRST_CPU  1
 135 #define SECOND_CPU 1
 136
 137 #define THIRD_CPU  1
 138 #define FOURTH_CPU 1
 139
 140 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU)
 141
 142 #define RC0 ((1<<2)<<8)
 143 #define RC1 ((1<<1)<<8)
 144 #define RC2 ((1<<4)<<8)
 145 #define RC3 ((1<<3)<<8)
 146
 147 #define DIMM0 0x50
 148 #define DIMM1 0x51
 149 #define DIMM2 0x52
 150 #define DIMM3 0x53
 151
 152 static void main(unsigned long bist)
 153 {
 154         static const struct mem_controller cpu[] = {
 155 #if FIRST_CPU
 156                 {
 157                         .node_id = 0,
 158                         .f0 = PCI_DEV(0, 0x18, 0),
 159                         .f1 = PCI_DEV(0, 0x18, 1),
 160                         .f2 = PCI_DEV(0, 0x18, 2),
 161                         .f3 = PCI_DEV(0, 0x18, 3),
 162                         .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
 163                         .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
 164                 },
 165 #endif
 166 #if SECOND_CPU
 167                 {
 168                         .node_id = 1,
 169                         .f0 = PCI_DEV(0, 0x19, 0),
 170                         .f1 = PCI_DEV(0, 0x19, 1),
 171                         .f2 = PCI_DEV(0, 0x19, 2),
 172                         .f3 = PCI_DEV(0, 0x19, 3),
 173                         .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 },
 174                         .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 },
 175
 176                 },
 177 #endif
 178
 179 #if THIRD_CPU
 180                 {
 181                         .node_id = 2,
 182                         .f0 = PCI_DEV(0, 0x1a, 0),
 183                         .f1 = PCI_DEV(0, 0x1a, 1),
 184                         .f2 = PCI_DEV(0, 0x1a, 2),
 185                         .f3 = PCI_DEV(0, 0x1a, 3),
 186                         .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
 187                         .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
 188
 189                 },
 190 #endif
 191 #if FOURTH_CPU
 192                 {
 193                         .node_id = 3,
 194                         .f0 = PCI_DEV(0, 0x1b, 0),
 195                         .f1 = PCI_DEV(0, 0x1b, 1),
 196                         .f2 = PCI_DEV(0, 0x1b, 2),
 197                         .f3 = PCI_DEV(0, 0x1b, 3),
 198                         .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
 199                         .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
 200
 201                 },
 202 #endif
 203         };
 204         int i;
 205         int needs_reset;
 206
 207         if (bist == 0) {
 208                 k8_init_and_stop_secondaries();
 209         }
 210
 211         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 212         uart_init();
 213         console_init();
 214
 215         /* Halt if there was a built in self test failure */
 216         report_bist_failure(bist);
 217
 218         setup_s4882_resource_map();
 219
 220         needs_reset = setup_coherent_ht_domain();
 221
 222         needs_reset |= ht_setup_chains_x();
 223         if (needs_reset) {
 224                 print_info("ht reset -\r\n");
 225                 soft_reset();
 226         }
 227
 228         enable_smbus();
 229
 230         memreset_setup();
 231         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 232
 233 }