2 ## Compute the location and size of where this firmware image
3 ## (coreboot plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The coreboot bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
19 default CONFIG_ROM_PAYLOAD = 1
22 ## Compute where this copy of coreboot will start in the boot rom
24 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
27 ## Compute a range of ROM that can cached to speed up coreboot,
30 ## XIP_ROM_SIZE must be a power of 2.
31 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
33 default XIP_ROM_SIZE=65536
34 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
40 ## Build the objects we have code for in this directory.
44 if HAVE_MP_TABLE object mptable.o end
45 if HAVE_PIRQ_TABLE object irq_tables.o end
51 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
52 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
58 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
59 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
60 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
61 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
70 depends "$(MAINBOARD)/failover.c ../romcc"
71 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
74 makerule ./failover.inc
75 depends "$(MAINBOARD)/failover.c ../romcc"
76 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
80 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
81 action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
85 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
86 action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
92 mainboardinit cpu/x86/fpu/enable_fpu.inc
93 mainboardinit cpu/x86/mmx/enable_mmx.inc
94 mainboardinit cpu/x86/sse/enable_sse.inc
95 mainboardinit ./auto.inc
96 mainboardinit cpu/x86/sse/disable_sse.inc
97 mainboardinit cpu/x86/mmx/disable_mmx.inc
98 mainboardinit arch/i386/lib/jmp_auto_out.inc
103 ## Build our 16 bit and 32 bit coreboot entry code
105 if USE_FALLBACK_IMAGE
106 mainboardinit cpu/x86/16bit/entry16.inc
107 ldscript /cpu/x86/16bit/entry16.lds
110 mainboardinit cpu/x86/32bit/entry32.inc
114 ldscript /cpu/x86/32bit/entry32.lds
118 ldscript /cpu/amd/car/cache_as_ram.lds
124 ## Build our reset vector (This is where coreboot is entered)
126 if USE_FALLBACK_IMAGE
127 mainboardinit cpu/x86/16bit/reset16.inc
128 ldscript /cpu/x86/16bit/reset16.lds
130 mainboardinit cpu/x86/32bit/reset32.inc
131 ldscript /cpu/x86/32bit/reset32.lds
136 ### Should this be in the northbridge code?
137 mainboardinit arch/i386/lib/cpu_reset.inc
141 ## Include an id string (For safe flashing)
143 mainboardinit arch/i386/lib/id.inc
144 ldscript /arch/i386/lib/id.lds
149 ## Setup Cache-As-Ram
151 mainboardinit cpu/amd/car/cache_as_ram.inc
155 ### This is the early phase of coreboot startup
156 ### Things are delicate and we test to see if we should
157 ### failover to another image.
159 if USE_FALLBACK_IMAGE
161 ldscript /arch/i386/lib/failover.lds
163 ldscript /arch/i386/lib/failover.lds
164 mainboardinit ./failover.inc
176 mainboardinit ./auto.inc
182 mainboardinit arch/i386/lib/jmp_auto.inc
187 ## Include the secondary Configuration files
191 # sample config for tyan/s4882
192 chip northbridge/amd/amdk8/root_complex
193 device apic_cluster 0 on
194 chip cpu/amd/socket_940
198 device pci_domain 0 on
199 chip northbridge/amd/amdk8
200 device pci 18.0 on end # LDT0
201 device pci 18.0 on # northbridge
202 # devices on link 1, link 1 == LDT 1
203 chip southbridge/amd/amd8131
204 # the on/off keyword is mandatory
206 # chip drivers/lsi/53c1030
207 # device pci 4.0 on end
208 # device pci 4.1 on end
209 # register "fw_address" = "0xfff8c000"
211 chip drivers/pci/onboard
212 device pci 9.0 on end #Broadcom
213 device pci 9.1 on end
216 device pci 0.1 on end
217 device pci 1.0 on end
218 device pci 1.1 on end
220 chip southbridge/amd/amd8111
221 # this "device pci 0.0" is the parent the next one
224 device pci 0.0 on end
225 device pci 0.1 on end
226 device pci 0.2 off end
227 device pci 1.0 off end
228 #chip drivers/ati/ragexl
229 chip drivers/pci/onboard
230 device pci 6.0 on end
231 register "rom_address" = "0xfff80000"
233 chip drivers/pci/onboard
234 device pci 5.0 on end #SiI
238 chip superio/winbond/w83627hf
239 device pnp 2e.0 on # Floppy
244 device pnp 2e.1 off # Parallel Port
248 device pnp 2e.2 on # Com1
252 device pnp 2e.3 on # Com2
256 device pnp 2e.5 on # Keyboard
262 device pnp 2e.6 off # CIR
265 device pnp 2e.7 off # GAME_MIDI_GIPO1
270 device pnp 2e.8 off end # GPIO2
271 device pnp 2e.9 off end # GPIO3
272 device pnp 2e.a off end # ACPI
273 device pnp 2e.b on # HW Monitor
279 device pci 1.1 on end
280 device pci 1.2 on end
282 # chip drivers/i2c/i2cmux # pca9556 smbus mux
283 # device i2c 18 on #0 pca9516 2, 1
284 # chip drivers/i2c/lm63 #cpu0 temp
285 # device i2c 4c on end
288 # device i2c 18 on #1 pca9516 1, 1
289 # chip drivers/generic/generic #dimm 1-0-0
290 # device i2c 50 on end
292 # chip drivers/generic/generic #dimm 1-0-1
293 # device i2c 51 on end
295 # chip drivers/generic/generic #dimm 1-1-0
296 # device i2c 52 on end
298 # chip drivers/generic/generic #dimm 1-1-1
299 # device i2c 53 on end
302 # device i2c 18 on #2 pca9516 1, 2
303 # chip drivers/generic/generic #dimm 0-0-0
304 # device i2c 50 on end
306 # chip drivers/generic/generic #dimm 0-0-1
307 # device i2c 51 on end
309 # chip drivers/generic/generic #dimm 0-1-0
310 # device i2c 52 on end
312 # chip drivers/generic/generic #dimm 0-1-1
313 # device i2c 53 on end
316 # device i2c 18 on #3 pca9516 1, 3
317 # chip drivers/generic/generic #dimm 3-0-0
318 # device i2c 50 on end
320 # chip drivers/generic/generic #dimm 3-0-1
321 # device i2c 51 on end
323 # chip drivers/generic/generic #dimm 3-1-0
324 # device i2c 52 on end
326 # chip drivers/generic/generic #dimm 3-1-1
327 # device i2c 53 on end
330 # device i2c 18 on #4 pca9516 1, 4
331 # chip drivers/generic/generic #dimm 2-0-0
332 # device i2c 50 on end
334 # chip drivers/generic/generic #dimm 2-0-1
335 # device i2c 51 on end
337 # chip drivers/generic/generic #dimm 2-1-0
338 # device i2c 52 on end
340 # chip drivers/generic/generic #dimm 2-1-1
341 # device i2c 53 on end
344 # device i2c 18 on #5 pca9516 2, 2
345 # chip drivers/i2c/lm63 #cpu1 temp
346 # device i2c 4c on end
349 # device i2c 18 on #6 pca9516 2, 3
350 # chip drivers/i2c/lm63 #cpu2 temp
351 # device i2c 4c on end
354 # device i2c 18 on #7 pca9516 2, 4
355 # chip drivers/i2c/lm63 #cpu3 temp
356 # device i2c 4c on end
360 # chip drivers/i2c/adm1027 # ADM1027 CPU1 vid and System FAN...
361 # device i2c 2e on end
363 # chip drivers/generic/generic # Winbond HWM 0x54 CPU0 vid
364 # device i2c 2a on end
366 # chip drivers/generic/generic # Winbond HWM 0x92
367 # device i2c 49 on end
369 # chip drivers/generic/generic # Winbond HWM 0x94
370 # device i2c 4a on end
372 # chip drivers/generic/generic # ??
373 # device i2c 69 on end
376 device pci 1.5 off end
377 device pci 1.6 off end
378 register "ide0_enable" = "1"
379 register "ide1_enable" = "1"
381 end # device pci 18.0
383 device pci 18.0 on end
385 device pci 18.1 on end
386 device pci 18.2 on end
387 device pci 18.3 on end
391 # chip drivers/generic/debug
392 # device pnp 0.0 off end # chip name
393 # device pnp 0.1 off end # pci_regs_all
394 # device pnp 0.2 off end # mem
395 # device pnp 0.3 on end # cpuid
396 # device pnp 0.4 off end # smbus_regs_all
397 # device pnp 0.5 on end # dual core msr
398 # device pnp 0.6 on end # cache size
399 # device pnp 0.7 on end # tsc