src/mainboard/tyan/s4880/romstage.c

   1
   2 #include <stdint.h>
   3 #include <string.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <stdlib.h>
  10 #include <pc80/mc146818rtc.h>
  11 #include <console/console.h>
  12 #include <lib.h>
  13
  14 #include <cpu/amd/model_fxx_rev.h>
  15 #include "northbridge/amd/amdk8/incoherent_ht.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20
  21 #include "cpu/x86/lapic/boot_cpu.c"
  22 #include "northbridge/amd/amdk8/reset_test.c"
  23 #include "northbridge/amd/amdk8/debug.c"
  24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  25
  26 #include "cpu/x86/mtrr/earlymtrr.c"
  27 #include "cpu/x86/bist.h"
  28
  29 #include "northbridge/amd/amdk8/setup_resource_map.c"
  30
  31 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  32
  33 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  34
  35 static void memreset_setup(void)
  36 {
  37    if (is_cpu_pre_c0()) {
  38         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  39    }
  40    else {
  41         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  42    }
  43         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  44 }
  45
  46 static void memreset(int controllers, const struct mem_controller *ctrl)
  47 {
  48    if (is_cpu_pre_c0()) {
  49         udelay(800);
  50         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  51         udelay(90);
  52    }
  53 }
  54 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  55 {
  56 #define SMBUS_HUB 0x18
  57         unsigned device=(ctrl->channel0[0])>>8;
  58         smbus_write_byte(SMBUS_HUB, 0x01, device);
  59         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  60 }
  61 #if 0
  62 static inline void change_i2c_mux(unsigned device)
  63 {
  64 #define SMBUS_HUB 0x18
  65         int ret;
  66         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  67         ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  68         print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  69         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  70         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  71 }
  72 #endif
  73
  74 static inline int spd_read_byte(unsigned device, unsigned address)
  75 {
  76         return smbus_read_byte(device, address);
  77 }
  78
  79 #define QRANK_DIMM_SUPPORT 1
  80
  81 #include "northbridge/amd/amdk8/raminit.c"
  82 #include "northbridge/amd/amdk8/coherent_ht.c"
  83 #include "lib/generic_sdram.c"
  84
  85  /* tyan does not want the default */
  86 #include "resourcemap.c"
  87
  88 #if CONFIG_LOGICAL_CPUS==1
  89 #define SET_NB_CFG_54 1
  90 #endif
  91 #include "cpu/amd/dualcore/dualcore.c"
  92
  93 #define RC0 ((1<<2)<<8)
  94 #define RC1 ((1<<1)<<8)
  95 #define RC2 ((1<<4)<<8)
  96 #define RC3 ((1<<3)<<8)
  97
  98 #define DIMM0 0x50
  99 #define DIMM1 0x51
 100 #define DIMM2 0x52
 101 #define DIMM3 0x53
 102
 103
 104
 105 #include "cpu/amd/car/post_cache_as_ram.c"
 106
 107 #include "cpu/amd/model_fxx/init_cpus.c"
 108
 109 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 110 #include "northbridge/amd/amdk8/early_ht.c"
 111
 112 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 113 {
 114         static const struct mem_controller cpu[] = {
 115                 {
 116                         .node_id = 0,
 117                         .f0 = PCI_DEV(0, 0x18, 0),
 118                         .f1 = PCI_DEV(0, 0x18, 1),
 119                         .f2 = PCI_DEV(0, 0x18, 2),
 120                         .f3 = PCI_DEV(0, 0x18, 3),
 121                         .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
 122                         .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
 123                 },
 124 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 125                 {
 126                         .node_id = 1,
 127                         .f0 = PCI_DEV(0, 0x19, 0),
 128                         .f1 = PCI_DEV(0, 0x19, 1),
 129                         .f2 = PCI_DEV(0, 0x19, 2),
 130                         .f3 = PCI_DEV(0, 0x19, 3),
 131                         .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 },
 132                         .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 },
 133
 134                 },
 135 #endif
 136
 137 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 138                 {
 139                         .node_id = 2,
 140                         .f0 = PCI_DEV(0, 0x1a, 0),
 141                         .f1 = PCI_DEV(0, 0x1a, 1),
 142                         .f2 = PCI_DEV(0, 0x1a, 2),
 143                         .f3 = PCI_DEV(0, 0x1a, 3),
 144                         .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
 145                         .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
 146
 147                 },
 148                 {
 149                         .node_id = 3,
 150                         .f0 = PCI_DEV(0, 0x1b, 0),
 151                         .f1 = PCI_DEV(0, 0x1b, 1),
 152                         .f2 = PCI_DEV(0, 0x1b, 2),
 153                         .f3 = PCI_DEV(0, 0x1b, 3),
 154                         .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
 155                         .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
 156
 157                 },
 158 #endif
 159         };
 160
 161         int needs_reset;
 162
 163         if (!cpu_init_detectedx && boot_cpu()) {
 164                 /* Nothing special needs to be done to find bus 0 */
 165                 /* Allow the HT devices to be found */
 166
 167                 enumerate_ht_chain();
 168
 169                 amd8111_enable_rom();
 170         }
 171
 172         if (bist == 0) {
 173                 init_cpus(cpu_init_detectedx);
 174         }
 175
 176         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 177         uart_init();
 178         console_init();
 179
 180         /* Halt if there was a built in self test failure */
 181         report_bist_failure(bist);
 182
 183         setup_s4880_resource_map();
 184
 185         needs_reset = setup_coherent_ht_domain();
 186
 187 #if CONFIG_LOGICAL_CPUS==1
 188         // It is said that we should start core1 after all core0 launched
 189         start_other_cores();
 190 #endif
 191         // automatically set that for you, but you might meet tight space
 192         needs_reset |= ht_setup_chains_x();
 193
 194         if (needs_reset) {
 195                 print_info("ht reset -\n");
 196                 soft_reset();
 197         }
 198
 199         enable_smbus();
 200
 201         memreset_setup();
 202         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 203
 204         post_cache_as_ram();
 205 }
 206