src/mainboard/tyan/s4880/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <arch/cpu.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15 #include "northbridge/amd/amdk8/incoherent_ht.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include "northbridge/amd/amdk8/cpu_rev.c"
  24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  25 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  26 #include "cpu/x86/bist.h"
  27
  28 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  29
  30 /* Look up a which bus a given node/link combination is on.
  31  * return 0 when we can't find the answer.
  32  */
  33 static unsigned node_link_to_bus(unsigned node, unsigned link)
  34 {
  35         unsigned reg;
  36
  37         for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
  38                 unsigned config_map;
  39                 config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
  40                 if ((config_map & 3) != 3) {
  41                         continue;
  42                 }
  43                 if ((((config_map >> 4) & 7) == node) &&
  44                         (((config_map >> 8) & 3) == link))
  45                 {
  46                         return (config_map >> 16) & 0xff;
  47                 }
  48         }
  49         return 0;
  50 }
  51
  52 static void hard_reset(void)
  53 {
  54         device_t dev;
  55
  56         /* Find the device */
  57         dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3);
  58
  59         set_bios_reset();
  60
  61         /* enable cf9 */
  62         pci_write_config8(dev, 0x41, 0xf1);
  63         /* reset */
  64         outb(0x0e, 0x0cf9);
  65 }
  66
  67 static void soft_reset(void)
  68 {
  69         device_t dev;
  70
  71         /* Find the device */
  72         dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0);
  73
  74         set_bios_reset();
  75         pci_write_config8(dev, 0x47, 1);
  76 }
  77
  78 static void memreset_setup(void)
  79 {
  80    if (is_cpu_pre_c0()) {
  81         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  82    }
  83    else {
  84         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  85    }
  86         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  87 }
  88
  89 static void memreset(int controllers, const struct mem_controller *ctrl)
  90 {
  91    if (is_cpu_pre_c0()) {
  92         udelay(800);
  93         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  94         udelay(90);
  95    }
  96 }
  97
  98 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  99 {
 100 #define SMBUS_HUB 0x18
 101         unsigned device=(ctrl->channel0[0])>>8;
 102         smbus_write_byte(SMBUS_HUB , 0x01, device);
 103         smbus_write_byte(SMBUS_HUB , 0x03, 0);
 104 }
 105 #if 0
 106 static inline void change_i2c_mux(unsigned device)
 107 {
 108 #define SMBUS_HUB 0x18
 109         smbus_write_byte(SMBUS_HUB , 0x01, device);
 110         smbus_write_byte(SMBUS_HUB , 0x03, 0);
 111 }
 112 #endif
 113
 114 static inline int spd_read_byte(unsigned device, unsigned address)
 115 {
 116         return smbus_read_byte(device, address);
 117 }
 118
 119 #include "northbridge/amd/amdk8/setup_resource_map.c"
 120 #include "northbridge/amd/amdk8/raminit.c"
 121
 122 #include "northbridge/amd/amdk8/coherent_ht.c"
 123 #include "sdram/generic_sdram.c"
 124
 125  /* tyan does not want the default */
 126 #include "resourcemap.c"
 127
 128 #if CONFIG_LOGICAL_CPUS==1
 129 #define SET_NB_CFG_54 1
 130 #include "cpu/amd/dualcore/dualcore.c"
 131 #endif
 132
 133 #define FIRST_CPU  1
 134 #define SECOND_CPU 1
 135
 136 #define THIRD_CPU  1
 137 #define FOURTH_CPU 1
 138
 139 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU)
 140
 141 #define RC0 ((1<<1)<<8)
 142 #define RC1 ((1<<2)<<8)
 143 #define RC2 ((1<<3)<<8)
 144 #define RC3 ((1<<4)<<8)
 145
 146 #define DIMM0 0x50
 147 #define DIMM1 0x51
 148 #define DIMM2 0x52
 149 #define DIMM3 0x53
 150
 151 static void main(unsigned long bist)
 152 {
 153         static const struct mem_controller cpu[] = {
 154 #if FIRST_CPU
 155                 {
 156                         .node_id = 0,
 157                         .f0 = PCI_DEV(0, 0x18, 0),
 158                         .f1 = PCI_DEV(0, 0x18, 1),
 159                         .f2 = PCI_DEV(0, 0x18, 2),
 160                         .f3 = PCI_DEV(0, 0x18, 3),
 161                         .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
 162                         .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
 163                 },
 164 #endif
 165 #if SECOND_CPU
 166                 {
 167                         .node_id = 1,
 168                         .f0 = PCI_DEV(0, 0x19, 0),
 169                         .f1 = PCI_DEV(0, 0x19, 1),
 170                         .f2 = PCI_DEV(0, 0x19, 2),
 171                         .f3 = PCI_DEV(0, 0x19, 3),
 172                         .channel0 = { RC1|DIMM0, 0 , 0, 0 },
 173                         .channel1 = { RC1|DIMM1, 0, 0, 0 },
 174
 175                 },
 176 #endif
 177
 178 #if THIRD_CPU
 179                 {
 180                         .node_id = 2,
 181                         .f0 = PCI_DEV(0, 0x1a, 0),
 182                         .f1 = PCI_DEV(0, 0x1a, 1),
 183                         .f2 = PCI_DEV(0, 0x1a, 2),
 184                         .f3 = PCI_DEV(0, 0x1a, 3),
 185                         .channel0 = { RC2|DIMM0, 0, 0, 0 },
 186                         .channel1 = { RC2|DIMM1, 0, 0, 0 },
 187
 188                 },
 189 #endif
 190 #if FOURTH_CPU
 191                 {
 192                         .node_id = 3,
 193                         .f0 = PCI_DEV(0, 0x1b, 0),
 194                         .f1 = PCI_DEV(0, 0x1b, 1),
 195                         .f2 = PCI_DEV(0, 0x1b, 2),
 196                         .f3 = PCI_DEV(0, 0x1b, 3),
 197                         .channel0 = { RC3|DIMM0, 0, 0, 0 },
 198                         .channel1 = { RC3|DIMM1, 0, 0, 0 },
 199
 200                 },
 201 #endif
 202         };
 203         int i;
 204         int needs_reset;
 205 #if CONFIG_LOGICAL_CPUS==1
 206         struct node_core_id id;
 207 #else
 208         unsigned nodeid;
 209 #endif
 210
 211         if (bist == 0) {
 212                 /* Skip this if there was a built in self test failure */
 213                 amd_early_mtrr_init();
 214
 215 #if CONFIG_LOGICAL_CPUS==1
 216                 set_apicid_cpuid_lo();
 217 #endif
 218
 219                 enable_lapic();
 220                 init_timer();
 221
 222 #if CONFIG_LOGICAL_CPUS==1
 223                 id = get_node_core_id_x();
 224                 if(id.coreid == 0) {
 225                         if (cpu_init_detected(id.nodeid)) {
 226                                 asm volatile ("jmp __cpu_reset");
 227                         }
 228                         distinguish_cpu_resets(id.nodeid);
 229 //                        start_other_core(id.nodeid);
 230                 }
 231 #else
 232                 nodeid = lapicid();
 233                 if (cpu_init_detected(nodeid)) {
 234                         asm volatile ("jmp __cpu_reset");
 235                 }
 236                 distinguish_cpu_resets(nodeid);
 237 #endif
 238
 239                 if (!boot_cpu()
 240 #if CONFIG_LOGICAL_CPUS==1
 241                         || (id.coreid != 0)
 242 #endif
 243                 ) {
 244                         stop_this_cpu(); // it will stop all cores except core0 of cpu0
 245                 }
 246         }
 247
 248         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 249         uart_init();
 250         console_init();
 251
 252         /* Halt if there was a built in self test failure */
 253         report_bist_failure(bist);
 254
 255         setup_s4880_resource_map();
 256
 257         needs_reset = setup_coherent_ht_domain();
 258
 259 #if CONFIG_LOGICAL_CPUS==1
 260         start_other_cores();
 261 #endif
 262
 263         needs_reset |= ht_setup_chains_x();
 264
 265         if (needs_reset) {
 266                 print_info("ht reset -\r\n");
 267                 soft_reset();
 268         }
 269
 270 #if 0
 271         dump_pci_devices();
 272 #endif
 273         enable_smbus();
 274
 275         memreset_setup();
 276         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 277
 278 }